From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB20C21ADAE; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; cv=none; b=C8Q9ZP3/yM+ORilB/EZMdRSrM1p1JFXKsn0XK7e43MOBB065CTh5n3oL3X0BO4Do+MF78jpglSZ+tJG2eBj1VTyw8Pe4sd/Oi/hzfvyQ5bjwMNo0E0sj6l7jo2ZkCX/0oHXwYy1JvnJ0r1Cd+T8FqcLlbnCOauqu3U0cvZzcFZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; c=relaxed/simple; bh=ijo1hW/xWUy1/m3cbnSQCqYPTm7fk4/pyNoDtB66FEQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HAa0730A1VvTbz3o3rqA9Rfn5snlFa7gpx7DCRtdqQPW29dKjTQ8Lz3yR2N6CIThFqFumXnQY7nnhwERA1kWns1Pma5wcxCC9W4FyFvGRcozFo0ZtcEd1L2gpAtQT37Akpq/ouPqlk3P0XG+4nTl75BXqhN5IxX+phEnsvBN2o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qWerm7Pv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qWerm7Pv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3E97AC4CEF7; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=ijo1hW/xWUy1/m3cbnSQCqYPTm7fk4/pyNoDtB66FEQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qWerm7PvhC+FRMtxnYufAPBQprwLjvFkcA6/A07k70IekDAWpMWyC7IM/AlGvasUh 9oxKn6j6RhnY5eqG5QVnDHOSpETO/OicZ/ERbPtKzwabsJNOppU8D3XThFx1w/SN4J 3nzhbH4k0Co/835Zbp/FiCBhTx5mUYb9R4Ab9V8JW4hVuLPwDGo5VMIXX2UauQFDQC uNcNjXLHMSYNhiKIdHvJxYqVzWqQu3HaIAYJL1V4ggnZxUfd/wtsBgoqp6ztkD8O1b PWhRdXPRWOVZqZhwNDXUm0zHLLJDp1JxCbVbf5pj4GUg0BobV6t98n9+CIjLpOhBiP w/tI7jM7eKleQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CCB3CA1012; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:14 +0000 Subject: [PATCH v2 01/22] dt-bindings: usb: Add Apple dwc3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-1-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3085; i=sven@kernel.org; h=from:subject:message-id; bh=ijo1hW/xWUy1/m3cbnSQCqYPTm7fk4/pyNoDtB66FEQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesJlHJ09wPGhpqSoWlrB1t1jvi52zQmV2Nfv98rP6+ H/SmxfCHaUsDGIcDLJiiizb99ubPnn4RnDppkvvYeawMoEMYeDiFICJXFdk+MN34WbjvRwt82d8 fXHav37y/0w83TJzZbZV5ouycjOuvlRGhq9W7Y/atPWuu+y72HtviirTtCShvrvRFxZyr9hWPat xHQcA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Apple Silicon uses Synopsys DesignWare dwc3 based USB controllers for their Type-C ports. Signed-off-by: Sven Peter Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/usb/apple,dwc3.yaml | 80 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/apple,dwc3.yaml b/Docume= ntation/devicetree/bindings/usb/apple,dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7c8708143696faf2133c141d2a7= 8abd3b5813979 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/apple,dwc3.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/apple,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Silicon DWC3 USB controller + +maintainers: + - Sven Peter + +description: + Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for e= ach of + their Type-C ports. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - apple,t6000-dwc3 + - apple,t6020-dwc3 + - apple,t8112-dwc3 + - const: apple,t8103-dwc3 + - const: apple,t8103-dwc3 + + reg: + items: + - description: Core DWC3 region + - description: Apple-specific DWC3 region + + reg-names: + items: + - const: dwc3-core + - const: dwc3-apple + + interrupts: + maxItems: 1 + + iommus: + maxItems: 2 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - iommus + - resets + - power-domains + - usb-role-switch + +unevaluatedProperties: false + +examples: + - | + #include + #include + + usb@82280000 { + compatible =3D "apple,t8103-dwc3"; + reg =3D <0x82280000 0xce00>, <0x8228cd00 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupts =3D ; + iommus =3D <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + + power-domains =3D <&ps_atc0_usb>; + resets =3D <&atcphy0>; + + usb-role-switch; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa45799dfe07de2f54de6d6a1ce0615..0e085cb0762f765958d67be61ae= 0d3d773503431 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2399,6 +2399,7 @@ F: Documentation/devicetree/bindings/power/reset/appl= e,smc-reboot.yaml F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml F: Documentation/devicetree/bindings/spi/apple,spi.yaml F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml +F: Documentation/devicetree/bindings/usb/apple,dwc3.yaml F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/bluetooth/hci_bcm4377.c --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB1AA20469E; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; cv=none; b=HVOXv43rtfgCdaQesdcioWD3QbB6LBCSaI6FfXXBZnmF6ho3I4uYiiW8SWD1uon/C8aB8W8B9jdemdYxHQPaH8jrIJOxXhvpcjnV06kE61ONaYUQ8Pn8xi7pYsbQgabrxrlU+tCvhxJ0QwE9iXV7MZjUkBoO7eXZXfSiJDkQ1vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; c=relaxed/simple; bh=Q8PS/CHcVU9sVoFvstzk8Tw0m//oeM0x0Mm79e4aeeQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RScCXJsqzzY3sABVXQPtBYLf/rhKO8t5qsLQyOq3mMAOhsJPwMGaiEncvr7wvQy8Ts/J7bQ4poyg6JArIMJ/2fhr+6tbU/el3xMuDjGsZsmgDH+20vwSUuhx9h9aqeAzuBQ5uZw5PCBn3y/ZKYEKWjNxwdu5VCU5ACBmO2H2w4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZWA8+H3o; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZWA8+H3o" Received: by smtp.kernel.org (Postfix) with ESMTPS id 51894C4CEF9; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=Q8PS/CHcVU9sVoFvstzk8Tw0m//oeM0x0Mm79e4aeeQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZWA8+H3o5lxJeOz0/0ZNMqEOZ1XJgDCUXDnU+EyAZEJxThMe8qLib7FqcCigQyRv0 lsS4FIaDfDOhg8rzANlfvhOYvQEVaaDTj9EhlubhMT2LryGTLY9CVgR7lXhgtHmqD8 f1SFd7Ljc9bfNd5izXyE7qxcUyd6WLNYTbSLdZQink2CM3p6zGCDObQC/GuzWq7tSn 8BX2EUCyTPzELyzZxuMn0w6AgXaA05UislMxj4Suev5NL0ChH6zeNJedrsb4/bijVV 24UHW8rvQskhGIQsl2mf+AFNmGFA7yH8DviijBKxQWqsNUhQECQGG5gkmTE8cj4Ilr xUz3AWZItKUBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CFE2CA1002; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:15 +0000 Subject: [PATCH v2 02/22] usb: dwc3: dwc3_power_off_all_roothub_ports: Use ioremap_np when required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-2-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , stable@kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1330; i=sven@kernel.org; h=from:subject:message-id; bh=Q8PS/CHcVU9sVoFvstzk8Tw0m//oeM0x0Mm79e4aeeQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesNktsybFzVVaed8xlyc7weRDuT6/vvjjdfN7r61Rf JT+s3luRykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAia6Yw/I9KuJ5ww0JJXST2 usDtWCcJRrW1egs23c5g0n/g/756HRvD/7I81oyq2YXTBMt2dE0x8olUj6iwvPPhfaeK+McVTpP ZeAE= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 On Apple Silicon machines we can't use ioremap() / Device-nGnRE to map most regions but must use ioremap_np() / Device-nGnRnE whenever IORESOURCE_MEM_NONPOSTED is set. Make sure this is also done inside dwc3_power_off_all_roothub_ports to prevent SErrors. Fixes: 2d2a3349521d ("usb: dwc3: Add workaround for host mode VBUS glitch w= hen boot") Cc: stable@kernel.org Signed-off-by: Sven Peter --- drivers/usb/dwc3/host.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index 1c513bf8002ec9ec91b41bfd096cbd0da1dd2d2e..e77fd86d09cf0a36161c20ad3c8= 3f10e67099775 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -37,7 +37,10 @@ static void dwc3_power_off_all_roothub_ports(struct dwc3= *dwc) =20 /* xhci regs are not mapped yet, do it temporarily here */ if (dwc->xhci_resources[0].start) { - xhci_regs =3D ioremap(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END); + if (dwc->xhci_resources[0].flags & IORESOURCE_MEM_NONPOSTED) + xhci_regs =3D ioremap_np(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_E= ND); + else + xhci_regs =3D ioremap(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END); if (!xhci_regs) { dev_err(dwc->dev, "Failed to ioremap xhci_regs\n"); return; --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB267221DA5; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; cv=none; b=cFQ+yZwXQAh4LKq3V96xqIZHHS8bwg4+KzL6Q2Bq69v9lhUI0xivcVAXhUEDwf8Y2Al1XxupiGFWmCd3LN9Vo5dmNij2ZFG8IhmoyeC6sLlYH7zpuEUmyNIGQWwLUzX9KIlQPz+3pwk6fSBqBVu9qmGik1y3+xhSG0FaracqSFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173419; c=relaxed/simple; bh=IwSlnxJ2iq6EBFsK6qtAtYW5ioFRlILFFMPbZlRxlX4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qiCkdFOt3WtZx4Pp0ja36bv3jiaAAnyv6puRITxMCBEW9f+cUWvm6oGKzSHnXAzyjCLgvIxGTaqYTwVUr6zR5ih6aKYavWJ/Gs1+Qj725kgYTjAwFG+ZH7LKnRfLFgkaqsoDaI6vjc0f/hiKEvfmGPlau/O+lGPLv1KOF1T12Dw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N+iCzZly; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N+iCzZly" Received: by smtp.kernel.org (Postfix) with ESMTPS id 59EC3C4AF09; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=IwSlnxJ2iq6EBFsK6qtAtYW5ioFRlILFFMPbZlRxlX4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=N+iCzZlybG3lxFbOJUeEZOnutJZ4MfPOTSWPKeJu9ypAQEBgFMPWAdmR0X9c1JkOP CtHTpTl/9zNU2sP6o2zfdTwbq/dNQbTacirCpw/2WnKoKUmMSaKTuVrJVTNoHQhCri xeXmMYHZc/ZU1Mgvj3F9ZBPQDlCBckUeYCwe48uyGZZoia0VMJE4kEX5hCLo9DihpP Xl1VkKWmSfqsQNkZZHtW/+uhUpmC3YZkAPV2zsCtPkXVzZ4d4OT6kZelmQ7MGX5Odc Rkf0Xf+X5oZ5kVsTsJlVb9s8O3mT+OPykCQn4PDW+A/a28SVIgqdWNuXr7RykGnMlj okKjAIRELIXZw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BC35CAC582; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:16 +0000 Subject: [PATCH v2 03/22] usb: dwc3: glue: Allow more fine grained control over mode switches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-3-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5254; i=sven@kernel.org; h=from:subject:message-id; bh=IwSlnxJ2iq6EBFsK6qtAtYW5ioFRlILFFMPbZlRxlX4=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesDnPY2Ond928YnA9uuWW1bl/lYqLu3+/Zt9/kyfvy IrsBXpcHaUsDGIcDLJiiizb99ubPnn4RnDppkvvYeawMoEMYeDiFICJzFnGyLDYkctWMFzeSmRX RL6f4oKJaeohC9xK/zdNdPtj8OvXgQCG/7kKQWFudh5ibxl4uQ6frqlwey4ofdDK7eV3zp9z772 0ZAQA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 We need fine grained control over mode switched on the DWC3 controller present on Apple Silicon. Export core, host and gadget init and exit, ptrcap and susphy control functions. Also introduce an additional parameter to probe_data that allows to skip the final initialization step that would bring up host or gadget mode. Signed-off-by: Sven Peter --- drivers/usb/dwc3/core.c | 16 +++++++++++----- drivers/usb/dwc3/gadget.c | 2 ++ drivers/usb/dwc3/glue.h | 14 ++++++++++++++ drivers/usb/dwc3/host.c | 2 ++ 4 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8002c23a5a02acb8f3e87b2662a53998a4cf4f5c..18056fac44c8732278a650ac2be= 8b493892c92dd 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -132,6 +132,7 @@ void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); } } +EXPORT_SYMBOL_GPL(dwc3_enable_susphy); =20 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) { @@ -157,6 +158,7 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool i= gnore_susphy) =20 dwc->current_dr_role =3D mode; } +EXPORT_SYMBOL_GPL(dwc3_set_prtcap); =20 static void __dwc3_set_mode(struct work_struct *work) { @@ -974,7 +976,7 @@ static void dwc3_clk_disable(struct dwc3 *dwc) clk_disable_unprepare(dwc->bus_clk); } =20 -static void dwc3_core_exit(struct dwc3 *dwc) +void dwc3_core_exit(struct dwc3 *dwc) { dwc3_event_buffers_cleanup(dwc); dwc3_phy_power_off(dwc); @@ -982,6 +984,7 @@ static void dwc3_core_exit(struct dwc3 *dwc) dwc3_clk_disable(dwc); reset_control_assert(dwc->reset); } +EXPORT_SYMBOL_GPL(dwc3_core_exit); =20 static bool dwc3_core_is_valid(struct dwc3 *dwc) { @@ -1327,7 +1330,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) * * Returns 0 on success otherwise negative errno. */ -static int dwc3_core_init(struct dwc3 *dwc) +int dwc3_core_init(struct dwc3 *dwc) { unsigned int hw_mode; u32 reg; @@ -1527,6 +1530,7 @@ static int dwc3_core_init(struct dwc3 *dwc) =20 return ret; } +EXPORT_SYMBOL_GPL(dwc3_core_init); =20 static int dwc3_core_get_phy(struct dwc3 *dwc) { @@ -2298,9 +2302,11 @@ int dwc3_core_probe(const struct dwc3_probe_data *da= ta) dwc3_check_params(dwc); dwc3_debugfs_init(dwc); =20 - ret =3D dwc3_core_init_mode(dwc); - if (ret) - goto err_exit_debugfs; + if (!data->skip_core_init_mode) { + ret =3D dwc3_core_init_mode(dwc); + if (ret) + goto err_exit_debugfs; + } =20 pm_runtime_put(dev); =20 diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 25db36c63951bf5654f4bf5a98d7073a028364cd..7b92eb8c4ccf118b81f27afaf3f= 31bf56e1b6f74 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -4794,6 +4794,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) err0: return ret; } +EXPORT_SYMBOL_GPL(dwc3_gadget_init); =20 /* -----------------------------------------------------------------------= --- */ =20 @@ -4812,6 +4813,7 @@ void dwc3_gadget_exit(struct dwc3 *dwc) dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, dwc->ep0_trb, dwc->ep0_trb_addr); } +EXPORT_SYMBOL_GPL(dwc3_gadget_exit); =20 int dwc3_gadget_suspend(struct dwc3 *dwc) { diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h index 2efd00e763be4fc51911f32d43054059e61fb43a..633268c76fe4c7fdc312c9705df= a7cf7ccf3544c 100644 --- a/drivers/usb/dwc3/glue.h +++ b/drivers/usb/dwc3/glue.h @@ -15,16 +15,30 @@ * @res: resource for the DWC3 core mmio region * @ignore_clocks_and_resets: clocks and resets defined for the device sho= uld * be ignored by the DWC3 core, as they are managed by the glue + * @skip_core_init_mode: skip the finial initialization of the target mode= , as + * it must be managed by the glue */ struct dwc3_probe_data { struct dwc3 *dwc; struct resource *res; bool ignore_clocks_and_resets; + bool skip_core_init_mode; }; =20 int dwc3_core_probe(const struct dwc3_probe_data *data); void dwc3_core_remove(struct dwc3 *dwc); =20 +int dwc3_core_init(struct dwc3 *dwc); +void dwc3_core_exit(struct dwc3 *dwc); + +int dwc3_host_init(struct dwc3 *dwc); +void dwc3_host_exit(struct dwc3 *dwc); +int dwc3_gadget_init(struct dwc3 *dwc); +void dwc3_gadget_exit(struct dwc3 *dwc); + +void dwc3_enable_susphy(struct dwc3 *dwc, bool enable); +void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy); + int dwc3_runtime_suspend(struct dwc3 *dwc); int dwc3_runtime_resume(struct dwc3 *dwc); int dwc3_runtime_idle(struct dwc3 *dwc); diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index e77fd86d09cf0a36161c20ad3c83f10e67099775..cf6512ed17a69134e6ca1b884f7= 6c1439693fab1 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -220,6 +220,7 @@ int dwc3_host_init(struct dwc3 *dwc) platform_device_put(xhci); return ret; } +EXPORT_SYMBOL_GPL(dwc3_host_init); =20 void dwc3_host_exit(struct dwc3 *dwc) { @@ -230,3 +231,4 @@ void dwc3_host_exit(struct dwc3 *dwc) platform_device_unregister(dwc->xhci); dwc->xhci =3D NULL; } +EXPORT_SYMBOL_GPL(dwc3_host_exit); --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 067BD28642A; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=mnzkPfMmCYeO7Fdy1rm63Bse7+6iI1GoBIb83FbgAC+VaY6xU6K9z0o0UQScIzsUFgLkWtORDKHAhimzPodi6wpk2sB9Gn824fzddBbfP4ephTjWuFGjrTLqsVKQLDh07l/kxQZaTEDJ7CbstQtAkjK9PL+e/D6Q28fC1T1bHog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=WGR1Ei6umo7JOvKNb22kiN6fvXUGcDGeVS4t2p3ndto=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=br4RJTOLth4k+0zGmMnYJbJns6DdorDUwGK33qCVs6UUmOP7dAsLYj8KQWMde0v0t3QuX9IsUQFscuClUwE7Y8ew9g43AvuL33XhT2QVYc1KrQ1XYYO7xQ9+RRNuAIorN50B+2rqCe2csCzQYYx+g7X5tXAdUSLGzV9ss/W7LUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L6ASt8z7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L6ASt8z7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 66766C113D0; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=WGR1Ei6umo7JOvKNb22kiN6fvXUGcDGeVS4t2p3ndto=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L6ASt8z7PGCih2VDOfQ89ftQIJn9cAxh0LGv890SGMMTiTwAOsAp8cLG9Nxndq/6R W+UHlXBF3ggAJYAOfwo7nmpxsqT1V3Sh6NG0BzvKCw2p9iL1tmK941kFMoJzbGpCLf 4VmodiK7bHpY00Nd4alnLHoGErxiO+C5T2vjV3y1Jqs0vP6uLhBWxIicIatTONjR/Q 7Fl6LRnjnAOHbbWCPqZOtOwA1CsrpDZqba3DVpuSs/2pS/PpdiAhgi2NC6QPVooIpW X+RIRaq4SrVl7zKUsV8i1XJ/glTVC2zNolIowr3umOMsicqEsm318TwL1mhot4YGcV eIx4VNn/pL+oA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C66ACAC581; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:17 +0000 Subject: [PATCH v2 04/22] usb: dwc3: Add Apple Silicon DWC3 glue layer driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-4-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=17012; i=sven@kernel.org; h=from:subject:message-id; bh=WGR1Ei6umo7JOvKNb22kiN6fvXUGcDGeVS4t2p3ndto=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesLmr7nTtmVbpJ5D2SbXhqITUWYdy30BH7YaIib57f IOUgxd3lLIwiHEwyIopsmzfb2/65OEbwaWbLr2HmcPKBDKEgYtTACZyM42R4cIetV3HjotfuvyD m3dlkIwC25rIzT6PGr9uVl/35z/jKieG/1GlRyq1LS3/NXNMVjlT+rn1y+Nbv9vMWeKUjTdt9Ps bzwMA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 As mad as it sounds, the dwc3 controller present on the Apple M1 must be reset and reinitialized whenever a device is unplugged from the root port or when the PHY mode is changed. This is required for at least the following reasons: - The USB2 D+/D- lines are connected through a stateful eUSB2 repeater which in turn is controlled by a variant of the TI TPS6598x USB PD chip. When the USB PD controller detects a hotplug event it resets the eUSB2 repeater. Afterwards, no new device is recognized before the DWC3 core and PHY are reset as well because the eUSB2 repeater and the PHY/dwc3 block disagree about the current state. - It's possible to completely break the dwc3 controller by switching it to device mode and unplugging the cable at just the wrong time. If this happens dwc3 behaves as if no device is connected. CORESOFTRESET will also never clear after it has been set. The only workaround is to trigger a hard reset of the entire dwc3 core with its external reset line. - Whenever the PHY mode is changed (to e.g. transition to DisplayPort alternate mode or USB4) dwc3 has to be shutdown and reinitialized. Otherwise the Type-C port will not be usable until the entire SoC has been reset. Additionally, these controllers have a Apple-specific MMIO region after the common dwc3 region where some controls have to be updated. PHY bringup and shutdown also requires SUSPHY to be enabled for the ports to work correctly. In the future, this driver will also gain support for USB3-via-USB4 tunneling which will require additional tweaks. Add a glue driver that takes of all of these constraints. Signed-off-by: Sven Peter --- MAINTAINERS | 1 + drivers/usb/dwc3/Kconfig | 11 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-apple.c | 425 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 438 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0e085cb0762f765958d67be61ae0d3d773503431..e147e1b919d5737a34e684ec587= 872ce591c641a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2424,6 +2424,7 @@ F: drivers/pwm/pwm-apple.c F: drivers/soc/apple/* F: drivers/spi/spi-apple.c F: drivers/spmi/spmi-apple-controller.c +F: drivers/usb/dwc3/dwc3-apple.c F: drivers/video/backlight/apple_dwi_bl.c F: drivers/watchdog/apple_wdt.c F: include/dt-bindings/interrupt-controller/apple-aic.h diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 310d182e10b50b253d7e5a51674806e6ec442a2a..8161cd8f5d0d82826262518a1ae= fa3096aae83a8 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -189,4 +189,15 @@ config USB_DWC3_RTK or dual-role mode. Say 'Y' or 'M' if you have such device. =20 +config USB_DWC3_APPLE + tristate "Apple Silicon DWC3 Platform Driver" + depends on OF && ARCH_APPLE + default USB_DWC3 + select USB_ROLE_SWITCH + help + Support Apple Silicon SoCs with DesignWare Core USB3 IP. + The DesignWare Core USB3 IP has to be used in dual-role + mode on these machines. + Say 'Y' or 'M' if you have such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..10b5e68cfd68d5ca9aa5a27b04f= 349f9bf58e65c 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -43,6 +43,7 @@ endif ## =20 obj-$(CONFIG_USB_DWC3_AM62) +=3D dwc3-am62.o +obj-$(CONFIG_USB_DWC3_APPLE) +=3D dwc3-apple.o obj-$(CONFIG_USB_DWC3_OMAP) +=3D dwc3-omap.o obj-$(CONFIG_USB_DWC3_EXYNOS) +=3D dwc3-exynos.o obj-$(CONFIG_USB_DWC3_PCI) +=3D dwc3-pci.o diff --git a/drivers/usb/dwc3/dwc3-apple.c b/drivers/usb/dwc3/dwc3-apple.c new file mode 100644 index 0000000000000000000000000000000000000000..27674f0c284104cbbe75f51cd55= 593a964c8c9d6 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-apple.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Apple Silicon DWC3 Glue driver + * Copyright (C) The Asahi Linux Contributors + * + * Based on: + * - dwc3-qcom.c Copyright (c) 2018, The Linux Foundation. All rights res= erved. + * - dwc3-of-simple.c Copyright (c) 2015 Texas Instruments Incorporated -= https://www.ti.com + */ + +#include +#include +#include +#include +#include + +#include "glue.h" + +enum dwc3_apple_mode { + DWC3_APPLE_OFF, + DWC3_APPLE_HOST, + DWC3_APPLE_DEVICE, +}; + +/** + * struct dwc3_apple - Apple-specific DWC3 USB controller + * @dwc: Core DWC3 structure + * @dev: Pointer to the device structure + * @mmio_resource: Resource to be passed to dwc3_core_probe + * @apple_regs: Apple-specific DWC3 registers + * @resets: Reset control + * @role_sw: USB role switch + * @lock: Mutex for synchronizing access + * @core_probe_done: True if dwc3_core_probe was already called after the = first plug + * @mode: Current mode of the controller (off/host/device) + */ +struct dwc3_apple { + struct dwc3 dwc; + + struct device *dev; + struct resource *mmio_resource; + void __iomem *apple_regs; + + struct reset_control *resets; + struct usb_role_switch *role_sw; + + struct mutex lock; + + bool core_probe_done; + enum dwc3_apple_mode mode; +}; + +#define to_dwc3_apple(d) container_of((d), struct dwc3_apple, dwc) + +/* + * Apple Silicon dwc3 vendor-specific registers + * + * These registers were identified by tracing XNU's memory access patterns + * and correlating them with debug output over serial to determine their n= ames. + * We don't exactly know what these do but without these USB3 devices some= times + * don't work. + */ +#define APPLE_DWC3_REGS_START 0xcd00 +#define APPLE_DWC3_REGS_END 0xcdff + +#define APPLE_DWC3_CIO_LFPS_OFFSET 0xcd38 +#define APPLE_DWC3_CIO_LFPS_OFFSET_VALUE 0xf800f80 + +#define APPLE_DWC3_CIO_BW_NGT_OFFSET 0xcd3c +#define APPLE_DWC3_CIO_BW_NGT_OFFSET_VALUE 0xfc00fc0 + +#define APPLE_DWC3_CIO_LINK_TIMER 0xcd40 +#define APPLE_DWC3_CIO_PENDING_HP_TIMER GENMASK(23, 16) +#define APPLE_DWC3_CIO_PENDING_HP_TIMER_VALUE 0x14 +#define APPLE_DWC3_CIO_PM_LC_TIMER GENMASK(15, 8) +#define APPLE_DWC3_CIO_PM_LC_TIMER_VALUE 0xa +#define APPLE_DWC3_CIO_PM_ENTRY_TIMER GENMASK(7, 0) +#define APPLE_DWC3_CIO_PM_ENTRY_TIMER_VALUE 0x10 + +static inline void dwc3_apple_writel(struct dwc3_apple *appledwc, u32 offs= et, u32 value) +{ + writel(value, appledwc->apple_regs + offset - APPLE_DWC3_REGS_START); +} + +static inline u32 dwc3_apple_readl(struct dwc3_apple *appledwc, u32 offset) +{ + return readl(appledwc->apple_regs + offset - APPLE_DWC3_REGS_START); +} + +static inline void dwc3_apple_mask(struct dwc3_apple *appledwc, u32 offset= , u32 mask, u32 value) +{ + u32 reg; + + reg =3D dwc3_apple_readl(appledwc, offset); + reg &=3D ~mask; + reg |=3D value; + dwc3_apple_writel(appledwc, offset, reg); +} + +static void dwc3_apple_setup_cio(struct dwc3_apple *appledwc) +{ + dwc3_apple_writel(appledwc, APPLE_DWC3_CIO_LFPS_OFFSET, APPLE_DWC3_CIO_LF= PS_OFFSET_VALUE); + dwc3_apple_writel(appledwc, APPLE_DWC3_CIO_BW_NGT_OFFSET, + APPLE_DWC3_CIO_BW_NGT_OFFSET_VALUE); + dwc3_apple_mask(appledwc, APPLE_DWC3_CIO_LINK_TIMER, APPLE_DWC3_CIO_PENDI= NG_HP_TIMER, + APPLE_DWC3_CIO_PENDING_HP_TIMER_VALUE); + dwc3_apple_mask(appledwc, APPLE_DWC3_CIO_LINK_TIMER, APPLE_DWC3_CIO_PM_LC= _TIMER, + APPLE_DWC3_CIO_PM_LC_TIMER_VALUE); + dwc3_apple_mask(appledwc, APPLE_DWC3_CIO_LINK_TIMER, APPLE_DWC3_CIO_PM_EN= TRY_TIMER, + APPLE_DWC3_CIO_PM_ENTRY_TIMER_VALUE); +} + +static void dwc3_apple_set_ptrcap(struct dwc3_apple *appledwc, u32 mode) +{ + guard(spinlock_irqsave)(&appledwc->dwc.lock); + dwc3_set_prtcap(&appledwc->dwc, mode, false); +} + +static int dwc3_apple_core_probe(struct dwc3_apple *appledwc) +{ + struct dwc3_probe_data probe_data =3D {}; + int ret; + + lockdep_assert_held(&appledwc->lock); + WARN_ON_ONCE(appledwc->core_probe_done); + + appledwc->dwc.dev =3D appledwc->dev; + probe_data.dwc =3D &appledwc->dwc; + probe_data.res =3D appledwc->mmio_resource; + probe_data.ignore_clocks_and_resets =3D true; + probe_data.skip_core_init_mode =3D true; + + ret =3D dwc3_core_probe(&probe_data); + if (ret) + return ret; + + appledwc->core_probe_done =3D true; + return 0; +} + +static int dwc3_apple_core_init(struct dwc3_apple *appledwc) +{ + int ret; + + lockdep_assert_held(&appledwc->lock); + + if (appledwc->core_probe_done) { + ret =3D dwc3_core_init(&appledwc->dwc); + if (ret) + dev_err(appledwc->dev, "Failed to initialize DWC3 Core, err=3D%d\n", re= t); + } else { + ret =3D dwc3_apple_core_probe(appledwc); + if (ret) + dev_err(appledwc->dev, "Failed to probe DWC3 Core, err=3D%d\n", ret); + } + + return ret; +} + +static void dwc3_apple_phy_set_mode(struct dwc3_apple *appledwc, enum phy_= mode mode) +{ + lockdep_assert_held(&appledwc->lock); + + /* + * This platform requires SUSPHY to be enabled here already in order to p= roperly + * configure the PHY + */ + dwc3_enable_susphy(&appledwc->dwc, true); + phy_set_mode(appledwc->dwc.usb2_generic_phy[0], mode); + phy_set_mode(appledwc->dwc.usb3_generic_phy[0], mode); +} + +static int dwc3_apple_init(struct dwc3_apple *appledwc, enum dwc3_apple_mo= de mode) +{ + int ret, ret_reset; + + lockdep_assert_held(&appledwc->lock); + + ret =3D reset_control_deassert(appledwc->resets); + if (ret) { + dev_err(appledwc->dev, "Failed to deassert resets, err=3D%d\n", ret); + return ret; + } + + ret =3D dwc3_apple_core_init(appledwc); + if (ret) + goto reset_assert; + + /* + * Now that the core is initialized and already went through dwc3_core_so= ft_reset we can + * configure some unknown Apple-specific settings. + */ + dwc3_apple_setup_cio(appledwc); + + switch (mode) { + case DWC3_APPLE_HOST: + appledwc->dwc.dr_mode =3D USB_DR_MODE_HOST; + dwc3_apple_set_ptrcap(appledwc, DWC3_GCTL_PRTCAP_HOST); + dwc3_apple_phy_set_mode(appledwc, PHY_MODE_USB_HOST); + ret =3D dwc3_host_init(&appledwc->dwc); + if (ret) { + dev_err(appledwc->dev, "Failed to initialize host, ret=3D%d\n", ret); + goto core_exit; + } + + break; + case DWC3_APPLE_DEVICE: + appledwc->dwc.dr_mode =3D USB_DR_MODE_PERIPHERAL; + dwc3_apple_set_ptrcap(appledwc, DWC3_GCTL_PRTCAP_DEVICE); + dwc3_apple_phy_set_mode(appledwc, PHY_MODE_USB_DEVICE); + ret =3D dwc3_gadget_init(&appledwc->dwc); + if (ret) { + dev_err(appledwc->dev, "Failed to initialize gadget, ret=3D%d\n", ret); + goto core_exit; + } + break; + default: + /* Unreachable unless there's a bug in this driver */ + WARN_ON_ONCE(1); + ret =3D -EINVAL; + goto core_exit; + } + + appledwc->mode =3D mode; + return 0; + +core_exit: + dwc3_core_exit(&appledwc->dwc); +reset_assert: + ret_reset =3D reset_control_assert(appledwc->resets); + if (ret_reset) + dev_warn(appledwc->dev, "Failed to assert resets, err=3D%d\n", ret_reset= ); + + return ret; +} + +static int dwc3_apple_exit(struct dwc3_apple *appledwc) +{ + int ret =3D 0; + + lockdep_assert_held(&appledwc->lock); + + switch (appledwc->mode) { + case DWC3_APPLE_OFF: + /* Nothing to do if we're already off */ + return 0; + case DWC3_APPLE_DEVICE: + dwc3_gadget_exit(&appledwc->dwc); + break; + case DWC3_APPLE_HOST: + dwc3_host_exit(&appledwc->dwc); + break; + } + + /* This platform requires SUSPHY to be enabled in order to properly power= down the PHY */ + dwc3_enable_susphy(&appledwc->dwc, true); + dwc3_core_exit(&appledwc->dwc); + appledwc->mode =3D DWC3_APPLE_OFF; + + ret =3D reset_control_assert(appledwc->resets); + if (ret) { + dev_err(appledwc->dev, "Failed to assert resets, err=3D%d\n", ret); + return ret; + } + + return 0; +} + +static int dwc3_usb_role_switch_set(struct usb_role_switch *sw, enum usb_r= ole role) +{ + struct dwc3_apple *appledwc =3D usb_role_switch_get_drvdata(sw); + int ret; + + guard(mutex)(&appledwc->lock); + + /* + * The USB2 D+/D- lines are connected through a stateful eUSB2 repeater w= hich in turn is + * controlled by a variant of the TI TPS6598x USB PD chip. When the USB P= D controller + * detects a hotplug event it resets the eUSB2 repeater. Afterwards, no n= ew device is + * recognized before the DWC3 core and PHY are reset as well because the = eUSB2 repeater + * and the PHY/dwc3 block disagree about the current state. + * Additionally, the PHY is also incapable of switching between arbitrary= modes when dwc3 + * is kept online. It's also possible to get dwc3 into a state where no n= ew device is + * recognized and even a soft reset is not enough to recover when unplugg= ing a cable at the + * wrong time while in gadget mode. Only a hard reset triggered via the e= xternal reset line + * is able to recover from this state. + * We thus tear all of dwc3 down here and re-initialize it every time we = get a plug change + * (or even mode change) event. + */ + ret =3D dwc3_apple_exit(appledwc); + if (ret) + return ret; + + switch (role) { + case USB_ROLE_NONE: + /* Nothing to do if no cable is connected */ + return 0; + case USB_ROLE_HOST: + return dwc3_apple_init(appledwc, DWC3_APPLE_HOST); + case USB_ROLE_DEVICE: + return dwc3_apple_init(appledwc, DWC3_APPLE_DEVICE); + default: + dev_err(appledwc->dev, "Invalid target role: %d\n", role); + return -EINVAL; + } +} + +static enum usb_role dwc3_usb_role_switch_get(struct usb_role_switch *sw) +{ + struct dwc3_apple *appledwc =3D usb_role_switch_get_drvdata(sw); + + guard(mutex)(&appledwc->lock); + + switch (appledwc->mode) { + case DWC3_APPLE_HOST: + return USB_ROLE_HOST; + case DWC3_APPLE_DEVICE: + return USB_ROLE_DEVICE; + case DWC3_APPLE_OFF: + return USB_ROLE_NONE; + default: + /* Unreachable unless there's a bug in this driver */ + WARN_ON_ONCE(1); + return USB_ROLE_NONE; + } +} + +static int dwc3_apple_setup_role_switch(struct dwc3_apple *appledwc) +{ + struct usb_role_switch_desc dwc3_role_switch =3D { NULL }; + + dwc3_role_switch.fwnode =3D dev_fwnode(appledwc->dev); + dwc3_role_switch.set =3D dwc3_usb_role_switch_set; + dwc3_role_switch.get =3D dwc3_usb_role_switch_get; + dwc3_role_switch.driver_data =3D appledwc; + appledwc->role_sw =3D usb_role_switch_register(appledwc->dev, &dwc3_role_= switch); + if (IS_ERR(appledwc->role_sw)) + return PTR_ERR(appledwc->role_sw); + + return 0; +} + +static int dwc3_apple_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dwc3_apple *appledwc; + int ret; + + appledwc =3D devm_kzalloc(&pdev->dev, sizeof(*appledwc), GFP_KERNEL); + if (!appledwc) + return -ENOMEM; + + appledwc->dev =3D &pdev->dev; + mutex_init(&appledwc->lock); + + appledwc->resets =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(appledwc->resets)) + return dev_err_probe(&pdev->dev, PTR_ERR(appledwc->resets), + "Failed to get resets\n"); + + ret =3D reset_control_assert(appledwc->resets); + if (ret) { + dev_err(&pdev->dev, "Failed to assert resets, err=3D%d\n", ret); + return ret; + } + + appledwc->mmio_resource =3D platform_get_resource_byname(pdev, IORESOURCE= _MEM, "dwc3-core"); + if (!appledwc->mmio_resource) { + dev_err(dev, "Failed to get DWC3 MMIO\n"); + return -EINVAL; + } + + appledwc->apple_regs =3D devm_platform_ioremap_resource_byname(pdev, "dwc= 3-apple"); + if (IS_ERR(appledwc->apple_regs)) + return dev_err_probe(dev, PTR_ERR(appledwc->apple_regs), + "Failed to map Apple-specific MMIO\n"); + + /* + * Note that we only bring up dwc3 once the first device is attached beca= use we need to know + * the role (e.g. host), mode (e.g. USB3) and lane orientation to bring u= p the PHY which is + * tightly coupled to dwc3. + */ + appledwc->mode =3D DWC3_APPLE_OFF; + appledwc->core_probe_done =3D false; + ret =3D dwc3_apple_setup_role_switch(appledwc); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to setup role switch\n"); + + return 0; +} + +static void dwc3_apple_remove(struct platform_device *pdev) +{ + struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_apple *appledwc =3D to_dwc3_apple(dwc); + + guard(mutex)(&appledwc->lock); + + usb_role_switch_unregister(appledwc->role_sw); + + dwc3_apple_exit(appledwc); + if (appledwc->core_probe_done) + dwc3_core_remove(&appledwc->dwc); +} + +static const struct of_device_id dwc3_apple_of_match[] =3D { + { .compatible =3D "apple,t8103-dwc3" }, + {} +}; +MODULE_DEVICE_TABLE(of, dwc3_apple_of_match); + +static struct platform_driver dwc3_apple_driver =3D { + .probe =3D dwc3_apple_probe, + .remove =3D dwc3_apple_remove, + .driver =3D { + .name =3D "dwc3-apple", + .of_match_table =3D dwc3_apple_of_match, + }, +}; + +module_platform_driver(dwc3_apple_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("DesignWare DWC3 Apple Silicon Glue Driver"); --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A6F028726E; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=k7CPRnL+c5JOwyA/5o1UFeROq4t6LJPAcmnt07IEHd78HAewiPjBbWS1CfkOUdQrXUqXRIC1MI/ugmtlp20DU58c+TyhNDdZ6u1dyW1PYVmLcQJXKJN+MoBYAxFEMSlHg3F+jz/W5WY64mmTtzTBP0fKH9KUKHLdwkcvpdFy1Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=15pym0980OuqLrEYjjB149fk5uGZSOarunjihhfaJPQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OgEVgDZb87vWeI7FpA5WyrcrJEkAaQb+UNyAdDz4pSGr4eamOfpFZYNEauyTenNly3c7boHYmgvp4X6U9KRsc9vOg9Uq6rQJusXEp1rJNnlyecWHCoqiRHZQ+JG2lNkI8mebBbTWHMITfbT3la5hptdy4LSrBLnPw7MDSEWFxQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z9yl4jEb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z9yl4jEb" Received: by smtp.kernel.org (Postfix) with ESMTPS id 77C85C116D0; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=15pym0980OuqLrEYjjB149fk5uGZSOarunjihhfaJPQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Z9yl4jEbrHKxFRJ7MslmozJQ9zaI3RNGvTHoZsnFRcDlksxUocIo5I45ELw6uRMfe FeNMNjegSjO9zNe2lIanB0XKWndpuuWrxrE7/6y5365JKDS3sxfLXorX/7LtmXadvF aRu69Kzq1cRN47/Hwlfxqf85GuKLuV/JvWzGxeI5ISUaqM4AWkHCsVLB+ylSJtmUfg 9U5AQShKa+yJcT20qgbNrTXTlhe4bs4udA7eDfBxszTeqOlk8anXu2q10kKb1TbFDT SwaXd5Qq7Z33FO65hzbyGNO3491d02rNqfBWsrBKl2Z6Uj+h/icGLNb7TJnXz/7MkR WtYbgmKwN6BXQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D3E4CAC583; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:18 +0000 Subject: [PATCH v2 05/22] usb: typec: tipd: Clear interrupts first Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-5-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , stable@kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3392; i=sven@kernel.org; h=from:subject:message-id; bh=15pym0980OuqLrEYjjB149fk5uGZSOarunjihhfaJPQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesLm+enUZnyVMG4Lu6VTucDnbnVBV66Aququgf037O dFOmWsdpSwMYhwMsmKKLNv325s+efhGcOmmS+9h5rAygQxh4OIUgIloGDAybD0eNiHfe/opE21f Xbea/rvM8QvF5vR9WSq7/fp5+ZLJZxn+F816IKz8doNEY/4/9zPfz2dfKuDeo9L/8pt88vaLxxt /cwAA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Right now the interrupt handler first reads all updated status registers and only then clears the interrupts. It's possible that a duplicate interrupt for a changed register or plug state comes in after the interrupts have been processed but before they have been cleared: * plug is inserted, TPS_REG_INT_PLUG_EVENT is set * TPS_REG_INT_EVENT1 is read * tps6598x_handle_plug_event() has run and registered the plug * plug is removed again, TPS_REG_INT_PLUG_EVENT is set (again) * TPS_REG_INT_CLEAR1 is written, TPS_REG_INT_PLUG_EVENT is cleared We then have no plug connected and no pending interrupt but the tipd core still thinks there is a plug. It's possible to trigger this with e.g. a slightly broken Type-C to USB A converter. Fix this by first clearing the interrupts and only then reading the updated registers. Fixes: 45188f27b3d0 ("usb: typec: tipd: Add support for Apple CD321X") Fixes: 0a4c005bd171 ("usb: typec: driver for TI TPS6598x USB Power Delivery= controllers") Cc: stable@kernel.org Reviewed-by: Heikki Krogerus Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index dcf141ada07812295a6f07e41d77f95f98116010..1c80296c3b273e24ceacb3feff4= 32c4f6e6835cc 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -545,24 +545,23 @@ static irqreturn_t cd321x_interrupt(int irq, void *da= ta) if (!event) goto err_unlock; =20 + tps6598x_write64(tps, TPS_REG_INT_CLEAR1, event); + if (!tps6598x_read_status(tps, &status)) - goto err_clear_ints; + goto err_unlock; =20 if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) if (!tps6598x_read_power_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) if (!tps6598x_read_data_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 /* Handle plug insert or removal */ if (event & APPLE_CD_REG_INT_PLUG_EVENT) tps6598x_handle_plug_event(tps, status); =20 -err_clear_ints: - tps6598x_write64(tps, TPS_REG_INT_CLEAR1, event); - err_unlock: mutex_unlock(&tps->lock); =20 @@ -668,25 +667,24 @@ static irqreturn_t tps6598x_interrupt(int irq, void *= data) if (!(event1[0] | event1[1] | event2[0] | event2[1])) goto err_unlock; =20 + tps6598x_block_write(tps, TPS_REG_INT_CLEAR1, event1, intev_len); + tps6598x_block_write(tps, TPS_REG_INT_CLEAR2, event2, intev_len); + if (!tps6598x_read_status(tps, &status)) - goto err_clear_ints; + goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_POWER_STATUS_UPDATE) if (!tps6598x_read_power_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_DATA_STATUS_UPDATE) if (!tps6598x_read_data_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 /* Handle plug insert or removal */ if ((event1[0] | event2[0]) & TPS_REG_INT_PLUG_EVENT) tps6598x_handle_plug_event(tps, status); =20 -err_clear_ints: - tps6598x_block_write(tps, TPS_REG_INT_CLEAR1, event1, intev_len); - tps6598x_block_write(tps, TPS_REG_INT_CLEAR2, event2, intev_len); - err_unlock: mutex_unlock(&tps->lock); =20 --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0868D2868B3; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=CNcd9Ey31/GByniRrDhvIzFt8+LAw6kSKIXdabzDNQ1gBQ+sdSjuFtxYA94ybZETElOsinsQPmUE+TLEXWoDmFsOBgCEDXm2PjZHpAOsEPzPbTlipSeStSrgSl7d+E9hbBR8GDK/o9D/JFerEUsabO+4tWkS+5NpqoS91BR1ey8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=4iyRo+oPyIYx/la+0wXxRCeKpjuTn6CQPw93KZYaon8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e9RV336L4Oh1w3R1aihoOFQ3v81+Qnz89R4Z9haQvrRwlCHIZhLBIBRNA/UNZKvPmbDa82Vksato9QtOqwtaS1UkdvdYY9+p/tK5thOKC0bd7CMvZlKQW3CokctJOZM5dSz4g9u0P4jXyf9MAf2RfXECOtu54hVvjOb/buHbZo0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FPm3/xx3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FPm3/xx3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8907FC4CEFA; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=4iyRo+oPyIYx/la+0wXxRCeKpjuTn6CQPw93KZYaon8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FPm3/xx3GGdyCTrGbBSXlCUKuJYpd9ECMDpiLytrUb0z6vOyBT7JImdksXtMAF33o 0sPs0yHw+jzZXnat/I6RK21pa1YkePVBNMkr2l8Zh8IIqeI9mS4SQrMWlgaufE7XNS eKPB0N+I9WTeKvQ5k/VCwx9JeupkZY/Kzg4uub1+d2IhigoLL7GB9mVfYufa6maJJ/ CAuZ90JUc5rdr2Wet978L1CTf//BeULSbRIoAUJ64BO616BY8kQnYdttFEMqEuJ4M5 CvfSaW2yANLpMSBHJoKEi2uBUirvrsI9eid6KYEzojcg3XZ5VVlp5LRQcNpMARwZYw RJg9lO2wEAJQA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E0FCCA0FED; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:19 +0000 Subject: [PATCH v2 06/22] usb: typec: tipd: Move initial irq mask to tipd_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-6-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3232; i=sven@kernel.org; h=from:subject:message-id; bh=4iyRo+oPyIYx/la+0wXxRCeKpjuTn6CQPw93KZYaon8=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesHlJ0w2m5jeHz80z3hT8JuZkV8RBRRb+//Xz0n1WW omKv7zfUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZjI8v+MDEdOn/xkeqI/buId g2Lh1ZEbuF+U50lubTWO3bVAZllIUCbD/+Rbt662Snxb+kqfOe5MwaQz9YeSJ/15mfBq9Y6ZkSy HnBkA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Since the irq mask was originally added more tipd variants have been introduced and there's now struct tipd_data. Move the initial mask in there. Reviewed-by: Heikki Krogerus Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 1c80296c3b273e24ceacb3feff432c4f6e6835cc..6d8bcbc9cad8a1394e066504d4c= 5ca570edd4e4f 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -112,6 +112,7 @@ struct tps6598x; =20 struct tipd_data { irq_handler_t irq_handler; + u64 irq_mask1; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); @@ -1298,7 +1299,6 @@ static int tps6598x_probe(struct i2c_client *client) u32 status; u32 vid; int ret; - u64 mask1; =20 tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); if (!tps) @@ -1337,16 +1337,6 @@ static int tps6598x_probe(struct i2c_client *client) if (ret) return ret; =20 - /* CD321X chips have all interrupts masked initially */ - mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | - APPLE_CD_REG_INT_DATA_STATUS_UPDATE | - APPLE_CD_REG_INT_PLUG_EVENT; - - } else { - /* Enable power status, data status and plug event interrupts */ - mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | - TPS_REG_INT_DATA_STATUS_UPDATE | - TPS_REG_INT_PLUG_EVENT; } =20 tps->data =3D i2c_get_match_data(client); @@ -1364,7 +1354,7 @@ static int tps6598x_probe(struct i2c_client *client) return ret; } =20 - ret =3D tps6598x_write64(tps, TPS_REG_INT_MASK1, mask1); + ret =3D tps6598x_write64(tps, TPS_REG_INT_MASK1, tps->data->irq_mask1); if (ret) goto err_reset_controller; =20 @@ -1527,6 +1517,9 @@ static const struct dev_pm_ops tps6598x_pm_ops =3D { =20 static const struct tipd_data cd321x_data =3D { .irq_handler =3D cd321x_interrupt, + .irq_mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | + APPLE_CD_REG_INT_DATA_STATUS_UPDATE | + APPLE_CD_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1536,6 +1529,9 @@ static const struct tipd_data cd321x_data =3D { =20 static const struct tipd_data tps6598x_data =3D { .irq_handler =3D tps6598x_interrupt, + .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | + TPS_REG_INT_DATA_STATUS_UPDATE | + TPS_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1546,6 +1542,9 @@ static const struct tipd_data tps6598x_data =3D { =20 static const struct tipd_data tps25750_data =3D { .irq_handler =3D tps25750_interrupt, + .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | + TPS_REG_INT_DATA_STATUS_UPDATE | + TPS_REG_INT_PLUG_EVENT, .register_port =3D tps25750_register_port, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E61C289E07; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=UIMi6cMeTvfYD753yOnPB9a7e+ycai0BtgnLgpD7xbvOQYYj13eVqnNKW/Ls5sEMn8qbhCqy91f5NKaCn6dHH7MOJcjVYXFJ7n6vDUOa57kEHyKVJpgv1tneFoVcLMxT4rTDzoBuCHYidLMP21BTAkaINfON/3iboHxKqL6jEL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=W4i17xp3u3JigmcFedI8/zdpo2DC0szFJNzKL3OP7zQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ez8weMInI/0h6lG8tnXvt81XjLuXKXKR/WgVF91PX6H9oxpEAg2C2xp1nKQH5kM8gHQplhwywTmjtrp616OglviRgKEqwNyJZD/45tFRq2n4cGrkVYCP0AgmrdloBG0gJOzsE1QuP0zKHy+2qOPpukdrAeOAWoh0kIas2o4FAsI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GXSU2X0y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GXSU2X0y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 97278C2BC87; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=W4i17xp3u3JigmcFedI8/zdpo2DC0szFJNzKL3OP7zQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GXSU2X0yuqEqcgIXw4++1duW1AvkYDAuvZmLpnXa3GR1D+aKkDBBH0Jg2Op16r6Oc AJNOGu7drmRw9QBs2nAMlKtNwNU15Y6v5/JuI8X8ssTJR2cM1EmTOSYqU9a4ce5IVV hmG+i5lBW2eJbtSqZNjI5nLyuL5LcuAg/bA6IHppw+T53nh9QAkpaAi3Ogbz2cwRQc 3aDJyBeV2IS/zhnJfhxgr4exY0YAt3BTf5Zz66d9Zn5/Ro0hHBF9UgQXx0hk5hYB/F OHCpOgPSR3+IMKshLhjJlh2Z0N3w2ui5N5qsi9obeFup+aq4MCL2NskWFA8gnx1kpx N36nLmCec72gQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D0C9CA1002; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:20 +0000 Subject: [PATCH v2 07/22] usb: typec: tipd: Move switch_power_state to tipd_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-7-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2323; i=sven@kernel.org; h=from:subject:message-id; bh=W4i17xp3u3JigmcFedI8/zdpo2DC0szFJNzKL3OP7zQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesHlWOivDd/tkmESs+yyWuFftTt0avnk3Xc+7scton voS7veuo5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjCR5+mMDOcMTYXn9vFtStKY wZMepSfj5MT6dubPbw+7SuoWxpzuPsrwP/ZkmxbPp/NbvU7MOah9UEB8oueR+Pv32i9KMbTyvNY 5xwkA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 When support for CD321x was originally added no other hardware variant was supported and there was no need for struct tipd_data. Now that it exists move the special case in there so that we can drop the of_device_is_compatible_check entirely. Reviewed-by: Heikki Krogerus Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 6d8bcbc9cad8a1394e066504d4c5ca570edd4e4f..4815c5c462837865a5f9d37bbc1= 39249c82c2f75 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -118,6 +118,7 @@ struct tipd_data { void (*trace_status)(u32 status); int (*apply_patch)(struct tps6598x *tps); int (*init)(struct tps6598x *tps); + int (*switch_power_state)(struct tps6598x *tps, u8 target_state); int (*reset)(struct tps6598x *tps); }; =20 @@ -1293,7 +1294,6 @@ tps25750_register_port(struct tps6598x *tps, struct f= wnode_handle *fwnode) =20 static int tps6598x_probe(struct i2c_client *client) { - struct device_node *np =3D client->dev.of_node; struct tps6598x *tps; struct fwnode_handle *fwnode; u32 status; @@ -1331,18 +1331,16 @@ static int tps6598x_probe(struct i2c_client *client) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) tps->i2c_protocol =3D true; =20 - if (np && of_device_is_compatible(np, "apple,cd321x")) { - /* Switch CD321X chips to the correct system power state */ - ret =3D cd321x_switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); - if (ret) - return ret; - - } - tps->data =3D i2c_get_match_data(client); if (!tps->data) return -EINVAL; =20 + if (tps->data->switch_power_state) { + ret =3D tps->data->switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); + if (ret) + return ret; + } + /* Make sure the controller has application firmware running */ ret =3D tps6598x_check_mode(tps); if (ret < 0) @@ -1525,6 +1523,7 @@ static const struct tipd_data cd321x_data =3D { .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, .reset =3D cd321x_reset, + .switch_power_state =3D cd321x_switch_power_state, }; =20 static const struct tipd_data tps6598x_data =3D { --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0E6F28488F; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=uZOoE9WTkzHgP3yzEv9l7jzsezZtpsK2C5QJJPQiwSyQkTPfbz9juzoj5cPvgKVVVjixKo987rxLvGDc/UufgjPmRL7rAwxNRSE8gPEp8NWdwcIyfq6fgQ+AzL8JdH/p5cUtTd87IXWHmZks9cAWIU/eAV/+cJ2w/4EWXTR3A08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=Xg9QJiSBBIwd6sYFd4P5Er5AJf6QTVlzXtTmrm9L9YQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XICzTxhau49Pvig0xt7aRdFkA2uLghcPC95aiQ8MILrPLSI0tgtCIouHVxeooYCqQnG6WDxBgygU7130/iLgPvATwftrIjspsr+Orzu3scQwiYfQuyjK43KQmJ9kx0txgIjx1x63stxKCgUm8TGppr+ypP4ZIdyJEQZXARwYw5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=thU1Yi3U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="thU1Yi3U" Received: by smtp.kernel.org (Postfix) with ESMTPS id A8D12C2BCAF; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=Xg9QJiSBBIwd6sYFd4P5Er5AJf6QTVlzXtTmrm9L9YQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=thU1Yi3U5IIXEBXKBA7HcqyHHBfCkMPqXRl/zO2eZlH/6r6txATifLn8InixYei1X 8pfYGLonQ+83/F3NRMTvBnDFJiwts3Ze5vs/sOBeDyS1KvuzGG0VFEeNKDr8BaI9WR JIKq8gRMAZ+62r6AanhJVE5Uf4SrQ/P9ktXs1nCyY5txlqNbuhR1RDOkCWAvS8hfJ4 9Y9rmPxFDYXFdKDGk5m031TTwbDrgl1wwuJXr4IAtRpWdyX/2uJpTf/v0+XGFhhF74 VGvN/jer9YI0F8NNlbqEEBFWggXn053YSGwrjMQrARzomD4oy27IOiHihzvS58FU2/ xyEIQOp8TzUYQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F48FCA1012; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:21 +0000 Subject: [PATCH v2 08/22] usb: typec: tipd: Trace data status for CD321x correctly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-8-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5697; i=sven@kernel.org; h=from:subject:message-id; bh=Xg9QJiSBBIwd6sYFd4P5Er5AJf6QTVlzXtTmrm9L9YQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesPnbv/qwGHjIlK87sXONUYreKd8fK89yixpk/Xtz/ PcF+blCHaUsDGIcDLJiiizb99ubPnn4RnDppkvvYeawMoEMYeDiFICJ/GFhZLj954lK5UbBYouu mvJv/iXdh9Zrx2f8vcA5L8TTa8vJo2yMDMvCds4zvKW3Kl5w0QK1Jsn2tIPNH9YlHroj9u9V+rM KdX4A X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Some bits inside the CD321x TPS_DATA_STATUS register have a different function compared to the original tipd chip. Add these and introduce a separate trace function to show them correctly. Reviewed-by: Heikki Krogerus Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 8 +++++++- drivers/usb/typec/tipd/tps6598x.h | 5 +++++ drivers/usb/typec/tipd/trace.h | 39 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 4815c5c462837865a5f9d37bbc139249c82c2f75..19d713937870304e68325a441b0= de63eb5db3b80 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -114,6 +114,7 @@ struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); + void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); int (*apply_patch)(struct tps6598x *tps); @@ -492,7 +493,9 @@ static bool tps6598x_read_data_status(struct tps6598x *= tps) dev_err(tps->dev, "failed to read data status: %d\n", ret); return false; } - trace_tps6598x_data_status(data_status); + + if (tps->data->trace_data_status) + tps->data->trace_data_status(data_status); =20 return true; } @@ -1519,6 +1522,7 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, + .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, @@ -1532,6 +1536,7 @@ static const struct tipd_data tps6598x_data =3D { TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, + .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .apply_patch =3D tps6598x_apply_patch, @@ -1545,6 +1550,7 @@ static const struct tipd_data tps25750_data =3D { TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, .register_port =3D tps25750_register_port, + .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, .apply_patch =3D tps25750_apply_patch, diff --git a/drivers/usb/typec/tipd/tps6598x.h b/drivers/usb/typec/tipd/tps= 6598x.h index cecb8d11d23972dab0d8c15458b4052af7510b03..03edbb77bbd6d8093b2560db83e= 5913e25d06154 100644 --- a/drivers/usb/typec/tipd/tps6598x.h +++ b/drivers/usb/typec/tipd/tps6598x.h @@ -197,6 +197,11 @@ #define TPS_DATA_STATUS_FORCE_LSX BIT(23) #define TPS_DATA_STATUS_POWER_MISMATCH BIT(24) =20 +/* modified TPS_REG_DATA_STATUS bits for CD321x (and likely also TPS65987D= DK) */ +#define CD321X_DATA_STATUS_HPD_IRQ BIT(14) +#define CD321X_DATA_STATUS_HPD_LEVEL BIT(15) +#define CD321X_DATA_STATUS_USB4_CONNECTION BIT(23) + #define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK GENMASK(11, 10) #define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT(x) \ TPS_FIELD_GET(TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK, (x)) diff --git a/drivers/usb/typec/tipd/trace.h b/drivers/usb/typec/tipd/trace.h index bea383f2db9de5bbf1804fbad9ee6b134407b932..e9e40425138a01f15e35867f38f= 62e13623dbcec 100644 --- a/drivers/usb/typec/tipd/trace.h +++ b/drivers/usb/typec/tipd/trace.h @@ -217,6 +217,26 @@ { TPS_DATA_STATUS_FORCE_LSX, "FORCE_LSX" }, \ { TPS_DATA_STATUS_POWER_MISMATCH, "POWER_MISMATCH" }) =20 +#define show_cd321x_data_status_flags(data_status) \ + __print_flags(data_status & TPS_DATA_STATUS_FLAGS_MASK, "|", \ + { TPS_DATA_STATUS_DATA_CONNECTION, "DATA_CONNECTION" }, \ + { TPS_DATA_STATUS_UPSIDE_DOWN, "DATA_UPSIDE_DOWN" }, \ + { TPS_DATA_STATUS_ACTIVE_CABLE, "ACTIVE_CABLE" }, \ + { TPS_DATA_STATUS_USB2_CONNECTION, "USB2_CONNECTION" }, \ + { TPS_DATA_STATUS_USB3_CONNECTION, "USB3_CONNECTION" }, \ + { TPS_DATA_STATUS_USB3_GEN2, "USB3_GEN2" }, \ + { TPS_DATA_STATUS_USB_DATA_ROLE, "USB_DATA_ROLE" }, \ + { TPS_DATA_STATUS_DP_CONNECTION, "DP_CONNECTION" }, \ + { TPS_DATA_STATUS_DP_SINK, "DP_SINK" }, \ + { CD321X_DATA_STATUS_HPD_IRQ, "HPD_IRQ" }, \ + { CD321X_DATA_STATUS_HPD_LEVEL, "HPD_LEVEL" }, \ + { TPS_DATA_STATUS_TBT_CONNECTION, "TBT_CONNECTION" }, \ + { TPS_DATA_STATUS_TBT_TYPE, "TBT_TYPE" }, \ + { TPS_DATA_STATUS_OPTICAL_CABLE, "OPTICAL_CABLE" }, \ + { TPS_DATA_STATUS_ACTIVE_LINK_TRAIN, "ACTIVE_LINK_TRAIN" }, \ + { CD321X_DATA_STATUS_USB4_CONNECTION, "USB4" }, \ + { TPS_DATA_STATUS_POWER_MISMATCH, "POWER_MISMATCH" }) + #define show_data_status_dp_pin_assignment(data_status) \ __print_symbolic(TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT(data_status), \ { TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_E, "E" }, \ @@ -388,6 +408,25 @@ TRACE_EVENT(tps6598x_data_status, ) ); =20 +TRACE_EVENT(cd321x_data_status, + TP_PROTO(u32 data_status), + TP_ARGS(data_status), + + TP_STRUCT__entry( + __field(u32, data_status) + ), + + TP_fast_assign( + __entry->data_status =3D data_status; + ), + + TP_printk("%s%s%s", + show_cd321x_data_status_flags(__entry->data_status), + __entry->data_status & TPS_DATA_STATUS_DP_CONNECTION ? ", DP pinout " = : "", + maybe_show_data_status_dp_pin_assignment(__entry->data_status) + ) +); + #endif /* _TPS6598X_TRACE_H_ */ =20 /* This part must be outside protection */ --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EA3B28C864; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=Syl6psxerNJT9E/3vu6v1ERC7PBx93ZvDDZWTSafLvmy1DVd6uBAItm4oMoEcltRLMnkR4KaiC8P4cgG3eUGRNJlfKMTztyCRiYkANvPSRRqtM1rlbEIKO5NRIidZu61T/qgIZp1m0nYf87qd0f/AX3gf9HO34wim7/50tURuuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=lo20hMZGHXyN8QQJOTqJCcsm2KhwrQXpkI5DiyZfPqE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ieMP7TYGaNqyqiROSFMCunH0zWLHMPRNc50uJJfeOXTf5RopKQzWR2+oq4xlZNMurM9phVszHZVQmc3ZAtKy21mn3Weg91Qk/PgY0zjpAQ1ktn7jbofx9aG+kCIyv5esnSkVJXzEV1MRVjVOsqhN/NYBBu3mdLuaz7qJvCT6Czk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JjZXxOjv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JjZXxOjv" Received: by smtp.kernel.org (Postfix) with ESMTPS id B5C65C4CEFB; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=lo20hMZGHXyN8QQJOTqJCcsm2KhwrQXpkI5DiyZfPqE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JjZXxOjvF9FOKnuhGXKjTnp/kyKZnHpWQbWT3P6q4SUsW5bCZuVJG8bYkUupEXHeu dtwAiEIewqfOKcT/syuVIXTTr5DEItsobOD3OkYoyXCg/VnTF7HyjepFo5zoxRsob1 tPAIQ38NpEwxRgS6Pm2Ju/LTFwGIX+exTTHh84HCZRCI3n8pSG8TWRNjp4oZoMftU6 JDDLMT7vA2J8Cu1nJitF4n/P8loxRk1N7j0uV3vvluBkIfTKDVnpTxWpa/LdfmWFM9 raUmk88FH40SMy8IS3z3VtZU8HiRAFvNRjRXZGUODg8LEzp0YomVeVXpm7fePY2juC 395jalVe5xNTg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEE97CAC581; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:22 +0000 Subject: [PATCH v2 09/22] usb: typec: tipd: Add cd321x struct with separate size Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-9-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3570; i=sven@kernel.org; h=from:subject:message-id; bh=lo20hMZGHXyN8QQJOTqJCcsm2KhwrQXpkI5DiyZfPqE=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesPmP7I6crGCrlj/I+yonfsWDsl02Lz4c/let3usn9 TyQl/t1RykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAipzoYGd6+ZhH1XtWq15cu KPSSa7bynyMrfkceLDo6Qcqa7faOJ08Z/hlMPyfHOZHzzG92rl0v1Mu4dNbdW3vgj9F59tfiD66 7LWcGAA== X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 We're about to add more fields to struct tps6598x which are only relevant for Apple's CD321x and to ensure that we don't waste memory everywhere for those add a separate struct for cd321x and prepare to allocate more space inside probe. Reviewed-by: Heikki Krogerus Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 19d713937870304e68325a441b0de63eb5db3b80..51b0f3be8b66a743ddc3ea96c1b= 25f597a1e8f6c 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -113,6 +113,7 @@ struct tps6598x; struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; + size_t tps_struct_size; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); @@ -148,6 +149,10 @@ struct tps6598x { const struct tipd_data *data; }; =20 +struct cd321x { + struct tps6598x tps; +}; + static enum power_supply_property tps6598x_psy_props[] =3D { POWER_SUPPLY_PROP_USB_TYPE, POWER_SUPPLY_PROP_ONLINE, @@ -1297,18 +1302,24 @@ tps25750_register_port(struct tps6598x *tps, struct= fwnode_handle *fwnode) =20 static int tps6598x_probe(struct i2c_client *client) { + const struct tipd_data *data; struct tps6598x *tps; struct fwnode_handle *fwnode; u32 status; u32 vid; int ret; =20 - tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); + data =3D i2c_get_match_data(client); + if (!data) + return -EINVAL; + + tps =3D devm_kzalloc(&client->dev, data->tps_struct_size, GFP_KERNEL); if (!tps) return -ENOMEM; =20 mutex_init(&tps->lock); tps->dev =3D &client->dev; + tps->data =3D data; =20 tps->reset =3D devm_gpiod_get_optional(tps->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(tps->reset)) @@ -1334,10 +1345,6 @@ static int tps6598x_probe(struct i2c_client *client) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) tps->i2c_protocol =3D true; =20 - tps->data =3D i2c_get_match_data(client); - if (!tps->data) - return -EINVAL; - if (tps->data->switch_power_state) { ret =3D tps->data->switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); if (ret) @@ -1521,6 +1528,7 @@ static const struct tipd_data cd321x_data =3D { .irq_mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct cd321x), .register_port =3D tps6598x_register_port, .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, @@ -1535,6 +1543,7 @@ static const struct tipd_data tps6598x_data =3D { .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps6598x_register_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, @@ -1549,6 +1558,7 @@ static const struct tipd_data tps25750_data =3D { .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps25750_register_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CBBE289811; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=twVrm3wwEiJ7KCEFS8xyXP8FL96gc8FzOj3tNG0xjbnuzCR4yUTG2ok2ysUwWEP0iZ44K2p0JJ6MzushxtwatnHxs/Kcxl6MZzcikv0iY9dGw98yhzGOqsyGKsw8ijzfxT4bUBjsytTGljMJadT3h4qw7XygVxt/qtt5wyo+P+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=MXTlQV6o7leJfeFdeDCCrl77XRrADXKq1orvTlMWuSE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GlmFdpDwYAXZNPnYvJZCxbOqP4KiBK86ENx2YtyjuLrNMfH2Q01HocbWIuRLYi5KWC51WG8KWwHMNHEZgVGNLYoBtXG4GeukR3gKrQGl2bM4KXfaPcTgP2CMezQgzzCtY+EeNiP0WyYBZ8q38uDCj2t8TLp3TsbjoWxaZjAftFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X8GCzBCY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X8GCzBCY" Received: by smtp.kernel.org (Postfix) with ESMTPS id C8EF1C19423; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=MXTlQV6o7leJfeFdeDCCrl77XRrADXKq1orvTlMWuSE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=X8GCzBCYW4oU9ibDevb0oMcDM0BkNM32sjnjq7oLsuPtnMTQqUMnTwtu2JjHY1VYk pWhCje9yNi0ecX0KUtyZs5jqr4Yy27ujGMdh0vg5WDYgWYv0bEYmC2WEzFQYvIQeGK 7oMZrKsT9uioFIAXjGZcimUOI1elnPldoUcrPa3cgan+pE+G2eXnqOAE+l2taoCkFR KfHo4hejVKWSEt49ooNMPngm1xHaGE/jnoDXuyXbBJkr/hvl9kCFNUbvNgkQ9eIGI8 uenzVPOZEssQZ9Tnr/d0MD34GLIbCk7sIStLTLFnxMfQNzbrfScEtOxOZSdNJZciUM ertyBdrQ+sSoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF913CAC582; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:23 +0000 Subject: [PATCH v2 10/22] usb: typec: tipd: Read USB4, Thunderbolt and DisplayPort status for cd321x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-10-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5684; i=sven@kernel.org; h=from:subject:message-id; bh=MXTlQV6o7leJfeFdeDCCrl77XRrADXKq1orvTlMWuSE=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesAWNRvvnRCyI3bSDP+VTBPvSx5P+3tUWT5ZQMlmqs nx+2lPLjlIWBjEOBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBEdixgZPhen/Y5wM8itrAl m/Wr6Z8DfqbHlkoGfzLzCKkTMvwhk8nIcOfQHysL9aIFd9RZv0wRX+n/cQNX1RlLxnLVxR2JPrK WTAA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 CD321x supports various alternate modes and stores information once these are entered into separate status registers. Read those when they are active when reading TPS_DATA_STATUS to prepare supporting these. Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 80 +++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 76 insertions(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 51b0f3be8b66a743ddc3ea96c1b25f597a1e8f6c..afd11b3e1ae596c7f3283e4336a= aa57874c9378d 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -35,14 +35,18 @@ #define TPS_REG_INT_MASK2 0x17 #define TPS_REG_INT_CLEAR1 0x18 #define TPS_REG_INT_CLEAR2 0x19 -#define TPS_REG_SYSTEM_POWER_STATE 0x20 #define TPS_REG_STATUS 0x1a +#define TPS_REG_SYSTEM_POWER_STATE 0x20 +#define TPS_REG_USB4_STATUS 0x24 #define TPS_REG_SYSTEM_CONF 0x28 #define TPS_REG_CTRL_CONF 0x29 #define TPS_REG_BOOT_STATUS 0x2D #define TPS_REG_POWER_STATUS 0x3f #define TPS_REG_PD_STATUS 0x40 #define TPS_REG_RX_IDENTITY_SOP 0x48 +#define TPS_REG_CF_VID_STATUS 0x5e +#define TPS_REG_DP_SID_STATUS 0x58 +#define TPS_REG_INTEL_VID_STATUS 0x59 #define TPS_REG_DATA_STATUS 0x5f #define TPS_REG_SLEEP_CONF 0x70 =20 @@ -85,6 +89,31 @@ struct tps6598x_rx_identity_reg { struct usb_pd_identity identity; } __packed; =20 +/* TPS_REG_USB4_STATUS */ +struct tps6598x_usb4_status_reg { + u8 mode_status; + __le32 eudo; + __le32 unknown; +} __packed; + +/* TPS_REG_DP_SID_STATUS */ +struct tps6598x_dp_sid_status_reg { + u8 mode_status; + __le32 status_tx; + __le32 status_rx; + __le32 configure; + __le32 mode_data; +} __packed; + +/* TPS_REG_INTEL_VID_STATUS */ +struct tps6598x_intel_vid_status_reg { + u8 mode_status; + __le32 attention_vdo; + __le16 enter_vdo; + __le16 device_mode; + __le16 cable_mode; +} __packed; + /* Standard Task return codes */ #define TPS_TASK_TIMEOUT 1 #define TPS_TASK_REJECTED 3 @@ -121,6 +150,7 @@ struct tipd_data { int (*apply_patch)(struct tps6598x *tps); int (*init)(struct tps6598x *tps); int (*switch_power_state)(struct tps6598x *tps, u8 target_state); + bool (*read_data_status)(struct tps6598x *tps); int (*reset)(struct tps6598x *tps); }; =20 @@ -151,6 +181,10 @@ struct tps6598x { =20 struct cd321x { struct tps6598x tps; + + struct tps6598x_dp_sid_status_reg dp_sid_status; + struct tps6598x_intel_vid_status_reg intel_vid_status; + struct tps6598x_usb4_status_reg usb4_status; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -505,6 +539,41 @@ static bool tps6598x_read_data_status(struct tps6598x = *tps) return true; } =20 +static bool cd321x_read_data_status(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + int ret; + + ret =3D tps6598x_read_data_status(tps); + if (ret < 0) + return false; + + if (tps->data_status & TPS_DATA_STATUS_DP_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_DP_SID_STATUS, + &cd321x->dp_sid_status, sizeof(cd321x->dp_sid_status)); + if (ret) + dev_err(tps->dev, "Failed to read DP SID Status: %d\n", + ret); + } + + if (tps->data_status & TPS_DATA_STATUS_TBT_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_INTEL_VID_STATUS, + &cd321x->intel_vid_status, sizeof(cd321x->intel_vid_status)); + if (ret) + dev_err(tps->dev, "Failed to read Intel VID Status: %d\n", ret); + } + + if (tps->data_status & CD321X_DATA_STATUS_USB4_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_USB4_STATUS, + &cd321x->usb4_status, sizeof(cd321x->usb4_status)); + if (ret) + dev_err(tps->dev, + "Failed to read USB4 Status: %d\n", ret); + } + + return true; +} + static bool tps6598x_read_power_status(struct tps6598x *tps) { u16 pwr_status; @@ -565,7 +634,7 @@ static irqreturn_t cd321x_interrupt(int irq, void *data) goto err_unlock; =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_unlock; =20 /* Handle plug insert or removal */ @@ -614,7 +683,7 @@ static irqreturn_t tps25750_interrupt(int irq, void *da= ta) goto err_clear_ints; =20 if (event[0] & TPS_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_clear_ints; =20 /* @@ -688,7 +757,7 @@ static irqreturn_t tps6598x_interrupt(int irq, void *da= ta) goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_unlock; =20 /* Handle plug insert or removal */ @@ -1534,6 +1603,7 @@ static const struct tipd_data cd321x_data =3D { .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, + .read_data_status =3D cd321x_read_data_status, .reset =3D cd321x_reset, .switch_power_state =3D cd321x_switch_power_state, }; @@ -1550,6 +1620,7 @@ static const struct tipd_data tps6598x_data =3D { .trace_status =3D trace_tps6598x_status, .apply_patch =3D tps6598x_apply_patch, .init =3D tps6598x_init, + .read_data_status =3D tps6598x_read_data_status, .reset =3D tps6598x_reset, }; =20 @@ -1565,6 +1636,7 @@ static const struct tipd_data tps25750_data =3D { .trace_status =3D trace_tps25750_status, .apply_patch =3D tps25750_apply_patch, .init =3D tps25750_init, + .read_data_status =3D tps6598x_read_data_status, .reset =3D tps25750_reset, }; =20 --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1570B2877EE; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=hceyq50nrVPieUimNzYSnw4qujzFhgFx+US9grP2dgoyGHtExuP3U1e7+WfPzYbvbp6OIVWSqGTqWAvmunsbJVTdtVBopXBoA5ccMo4bThXcClyPzwlp0S9naKNbbUxpp2bt8ZzucSrsks+97Q/Mt9jwkji8kn6WIIF/3QAOrR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=sNTZAaAEhZ4bZmshDMImxkogVK30dZbNtflvQruejvE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AOtokY0ouIMyuaTbb3z8/oGGJrZgiYI8M9w0X6zsI8Dmvhwc3w5/ElJ5HUGKG8haJuZff/JniEkyJq56q76gu5qsX/upJEJaUogpPXS7rReZhWvhtK5pb6FWjMIaA+qA8zFNjVKU48RoqJo4gjNgenaHmiINJB4c1hR1mtXKBZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kmOayccZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kmOayccZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id D9DB4C4CEFE; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173419; bh=sNTZAaAEhZ4bZmshDMImxkogVK30dZbNtflvQruejvE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kmOayccZkJJMb63vm0aS7JLNNdJhS6PbG3OWEQwS8KtzMkIr77criH2f8uyMJpDrH bK3motw7FPQBK3kRkcmv0tznlgxFgClAas3laNJPGqHl7CBKTnb9yWTjOEWW/lT7oh cq39FCWN5mZmbTCvnHfUAM0surpmUkVglT+S8HOGWj4FrZp7xGuCiMvx4oAvkFPbLQ Bfcxi/rXbVRbgjhn1fRjMvqzqD18T5liFhM4uwCdPeBeDhRhWqAuBLZBU2JxczEmo6 maUIJM1XYh6/xZ9OpMjQjiIn7ASGILssKhUtfqJNp/CsjKNW5gvwmL9DMEf2c+CWXb ESR37MuJDPVOA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0183CA1012; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:24 +0000 Subject: [PATCH v2 11/22] usb: typec: tipd: Register DisplayPort and Thunderbolt altmodes for cd321x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-11-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5545; i=sven@kernel.org; h=from:subject:message-id; bh=sNTZAaAEhZ4bZmshDMImxkogVK30dZbNtflvQruejvE=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesAWq7/26v3KU6b/5FV7sJCgg+cC670702QUWsgt/i shbd+zvKGVhEONgkBVTZNm+3970ycM3gks3XXoPM4eVCWQIAxenAExEso/hf23UuqatXw5m7eMV UzawcguYtjD8tOoJLe31k1wCLy0sWsjwP/7XzPnr76v6H9bQmBo+OY1j4/nveuzZFsxG7123xh1 LZAUA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Ports equipped with a CD321x are only found on Apple Silicon machines and always support DisplayPort, Thunderbolt and USB4. Register these port modes unconditionally. Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 85 +++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 82 insertions(+), 3 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index afd11b3e1ae596c7f3283e4336aaa57874c9378d..c7cf936e5a61a331271c05b68ff= 1b77b89c0f643 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -144,6 +146,7 @@ struct tipd_data { u64 irq_mask1; size_t tps_struct_size; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); + void (*unregister_port)(struct tps6598x *tps); void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); @@ -185,6 +188,9 @@ struct cd321x { struct tps6598x_dp_sid_status_reg dp_sid_status; struct tps6598x_intel_vid_status_reg intel_vid_status; struct tps6598x_usb4_status_reg usb4_status; + + struct typec_altmode *port_altmode_dp; + struct typec_altmode *port_altmode_tbt; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -964,6 +970,76 @@ tps6598x_register_port(struct tps6598x *tps, struct fw= node_handle *fwnode) return 0; } =20 +static int cd321x_register_port_altmodes(struct cd321x *cd321x) +{ + struct typec_altmode_desc desc; + struct typec_altmode *amode; + + memset(&desc, 0, sizeof(desc)); + desc.svid =3D USB_TYPEC_DP_SID; + desc.mode =3D USB_TYPEC_DP_MODE; + desc.vdo =3D DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASS= IGN_D)); + desc.vdo |=3D DP_CAP_DFP_D; + amode =3D typec_port_register_altmode(cd321x->tps.port, &desc); + if (IS_ERR(amode)) + return PTR_ERR(amode); + cd321x->port_altmode_dp =3D amode; + + memset(&desc, 0, sizeof(desc)); + desc.svid =3D USB_TYPEC_TBT_SID; + desc.mode =3D TYPEC_ANY_MODE; + amode =3D typec_port_register_altmode(cd321x->tps.port, &desc); + if (IS_ERR(amode)) { + typec_unregister_altmode(cd321x->port_altmode_dp); + cd321x->port_altmode_dp =3D NULL; + return PTR_ERR(amode); + } + cd321x->port_altmode_tbt =3D amode; + + return 0; +} + +static int +cd321x_register_port(struct tps6598x *tps, struct fwnode_handle *fwnode) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + int ret; + + ret =3D tps6598x_register_port(tps, fwnode); + if (ret) + return ret; + + ret =3D cd321x_register_port_altmodes(cd321x); + if (ret) + goto err_unregister_port; + + typec_set_mode(tps->port, TYPEC_STATE_SAFE); + + return 0; + +err_unregister_port: + typec_unregister_port(tps->port); + return ret; +} + +static void +tps6598x_unregister_port(struct tps6598x *tps) +{ + typec_unregister_port(tps->port); +} + +static void +cd321x_unregister_port(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + typec_unregister_altmode(cd321x->port_altmode_dp); + cd321x->port_altmode_dp =3D NULL; + typec_unregister_altmode(cd321x->port_altmode_tbt); + cd321x->port_altmode_tbt =3D NULL; + typec_unregister_port(tps->port); +} + static int tps_request_firmware(struct tps6598x *tps, const struct firmwar= e **fw, const char **firmware_name) { @@ -1505,7 +1581,7 @@ static int tps6598x_probe(struct i2c_client *client) err_disconnect: tps6598x_disconnect(tps, 0); err_unregister_port: - typec_unregister_port(tps->port); + tps->data->unregister_port(tps); err_role_put: usb_role_switch_put(tps->role_sw); err_fwnode_put: @@ -1529,7 +1605,7 @@ static void tps6598x_remove(struct i2c_client *client) devm_free_irq(tps->dev, client->irq, tps); =20 tps6598x_disconnect(tps, 0); - typec_unregister_port(tps->port); + tps->data->unregister_port(tps); usb_role_switch_put(tps->role_sw); =20 /* Reset PD controller to remove any applied patch */ @@ -1598,7 +1674,8 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct cd321x), - .register_port =3D tps6598x_register_port, + .register_port =3D cd321x_register_port, + .unregister_port =3D cd321x_unregister_port, .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1615,6 +1692,7 @@ static const struct tipd_data tps6598x_data =3D { TPS_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps6598x_register_port, + .unregister_port =3D tps6598x_unregister_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1631,6 +1709,7 @@ static const struct tipd_data tps25750_data =3D { TPS_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps25750_register_port, + .unregister_port =3D tps6598x_unregister_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52AAE2ED871; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=odcVBvBpdq4sXOGRtWdhPgOwr7kvyk+vepz3nmIuPLHBmkAQKG7vy9yr6IPjcLOlPvPUPH5i7vjhWtxsDMQWgOCyWtKvwUoWoFKVbjBNY9kxG8911uZ3xEZFDdSZlgkFgLSewqfeFOFiJojGfzXHS3oKrEhzfNUyJPuhE6qlBeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=jQdetY7GRNst+fAdMazOXWq4v9pFdWCONcHGsoymkA0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F3KoMIMeZ+vLIXgaGF47hnOfyJl8jYs/fBNGcIsW4wTLnMitZtOsEnOwCl3JnHWCw1Do+Ig5VRUKYs6B44/XeB4ZJkT6PQi5ldosT6zxR0V4/7oiMiH8KVDII/38ccWtMirEDQBS9/LSSWwzxLCaHDiHoQM95bElZkn9TuFRDBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mWijnsA5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mWijnsA5" Received: by smtp.kernel.org (Postfix) with ESMTPS id E8983C116C6; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=jQdetY7GRNst+fAdMazOXWq4v9pFdWCONcHGsoymkA0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mWijnsA5JVbBpy0d9QBMQ9/UBtnQDmpAWh6oGiyY9FfhojNgqlmqOIycsiIgbSAKs 5Ntt8lMAJRjUWPbXz0TJrvebmLuZNaicpiBxHgyqOgphUx1MZ1iTrg14KUxGbYI465 mtiNcAOApb3OMh6d1kSqEnASIKU7P5ij/DOqmRQOjA2Ymwim/9IOQgA0qblZQchzDg N911DYDdIYW9cfKt4ddksMteuTXtqJs8pCGTcm+b1URs6AWEaQ8ufbNpIADyITINcD fSgt+Nt458I+lRLLEi0dV3Zh7URm37oLm2W6XPoxTvpmXIOlTQe32nBh9Tjal6Rtih 2KaSVgebyUmIA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDCE4CA1002; Sat, 6 Sep 2025 15:43:39 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:25 +0000 Subject: [PATCH v2 12/22] usb: typec: tipd: Update partner identity when power status was updated Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-12-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1307; i=sven@kernel.org; h=from:subject:message-id; bh=QDhuS+HKxdzHgchZ8cpnBXq7l32Qnci0SI3jtXHi3pQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesIUHfP/51Dx+HjI3fP1Hv+ZfgQwqE5nKfC9U7fw/e arHnF/vO0pZGMQ4GGTFFFm277c3ffLwjeDSTZfew8xhZQIZwsDFKQAT0T/H8JNRIG1pgkTFy6vB XlWOy2dUiNh+v/ZrXryi7/v1nHEstfMZ/hltPOX0rJLl0ONzDFv1f/kn9zfYOJj/l9N8LcircKb nAzsA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Whenever the power status is changed make sure to also update the partner identity to be able to detect changes once de-bouncing and mode changes are added for CD321x. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index c7cf936e5a61a331271c05b68ff1b77b89c0f643..cd427eecd8a594b7e609a20de27= a9722055307d8 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -635,9 +635,16 @@ static irqreturn_t cd321x_interrupt(int irq, void *dat= a) if (!tps6598x_read_status(tps, &status)) goto err_unlock; =20 - if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) + if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) { if (!tps6598x_read_power_status(tps)) goto err_unlock; + if (TPS_POWER_STATUS_PWROPMODE(tps->pwr_status) =3D=3D TYPEC_PWR_MODE_PD= ) { + if (tps6598x_read_partner_identity(tps)) { + dev_err(tps->dev, "failed to partner identity\n"); + tps->partner_identity =3D (struct usb_pd_identity) {0}; + } + } + } =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) if (!tps->data->read_data_status(tps)) --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7AA2BE65C; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=drEhiBoX3oGjIy36vlsLea967OvT1zYfvzLW09QJx2HmGF2zkAT045Ecfkr0jtZE6J0dShdiSA8w8MuRCuMtRSwH1u1iAHl1oesmfa2Vd2M+QjRkPQyt3YhKEHAKFSy3+xB/j5yg2YiVYvrLQar9qLD1iGbIpXwTZrVcLHZ/EvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=6hJc+1Kc7zJ4dqjuwSYvv6Ldou9XTFOwmoh/VJLGXVA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B+ikf3IYzE8cVyYbdSzKHoA39mxy2XevzMfWiO5DRTK0r2GDGZL8tNcWWjfp+BNenZksS1HisiShJetonYPVBxdh+pAOjlTh378iSC7XE5y/JTGCZUpGwqxrgtuuC7wKLTV8ucNScRRLRZ9LoMdNlLlVFNlxwlkZgeQW/lCmGPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bC8B3EAw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bC8B3EAw" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0CAD0C4CEFC; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=6hJc+1Kc7zJ4dqjuwSYvv6Ldou9XTFOwmoh/VJLGXVA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bC8B3EAwHvLt7mvv0lnE0JCLeq6XG7U7HmYMonRKsp0U+npLmfFVobfxBSnQ127yA 7hFjgaMyA3XS/n3DZEIfK45gkhY1kbsb0YH9EG8wTGfefDLMManF7TJQi/QNjSuiit TJTDzlOb6rFc6hjpJNLRbMu54yOsWCM33fB05ZJ8syVZximB02gpPtdsnV/+9t9V/X 1MdxeI1HOC6VcKT5lALzhOkm4xTtXPGH7Vi+5adbMvRWSOo1nSOQAGytgxxXEZMAEI RENzVAcZjOTo6LQtAg2kkxnnHmhd7XVWNGhp9D/Rtq4+5XEBybFf5lESJUySmxe442 OlojJBGuIwwKA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04D0DCAC581; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:26 +0000 Subject: [PATCH v2 13/22] usb: typec: tipd: Use read_power_status function in probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-13-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=sven@kernel.org; h=from:subject:message-id; bh=a8r41F+GXMooCUu+KjgVBdiu8UWVrFpb7Loq9EHEDqI=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesIV/d0vKnJ/dnraFIay9qvF9XIIp29ULZyyCEpu2G 5X6hhR3lLIwiHEwyIopsmzfb2/65OEbwaWbLr2HmcPKBDKEgYtTACayOZrhv9NakSfS94v+J8+5 ErajgbnGc2f2u9PfX8a9/K6t/GXHSmWGv9IPOr6nP56efXPBXW/RpVsfSBtPOXuwN/ffv375ivc T5fkB X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin We need the initial power status to be able to reliably detect connector changes once we introduce de-bouncing for CD321x next. read_power_status takes care of this and also forwards the status to the trace subsystem so let's use that instead of open-coding it inside probe. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index cd427eecd8a594b7e609a20de27a9722055307d8..e6e9730ee6dacd8c1271b1d52a0= 2da49ff248d3e 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -1549,11 +1549,8 @@ static int tps6598x_probe(struct i2c_client *client) goto err_role_put; =20 if (status & TPS_STATUS_PLUG_PRESENT) { - ret =3D tps6598x_read16(tps, TPS_REG_POWER_STATUS, &tps->pwr_status); - if (ret < 0) { - dev_err(tps->dev, "failed to read power status: %d\n", ret); + if (!tps6598x_read_power_status(tps)) goto err_unregister_port; - } ret =3D tps6598x_connect(tps, status); if (ret) dev_err(&client->dev, "failed to register partner\n"); --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA532EBBBC; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=avejxuMOdFXX/q/tBrdmLjHogJTJcyN539aWkiqDrtBAg70xWpbvyZLFq17fFB90lUswsD/ZzwKiNDeFl5PRgDrMULPfPTxhYbQh70ke2lyWep6FnULWebzt7u3rQOlkWaFNs3qsg8fC2f2J7xs4WbfNZHxHcDMXCtxcdtGqt5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=da0nPHLb+kjJFizEGwI7X27ZL2AoDem8fuVWASExNUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bSrWVn9XkQgEOp960rKS56eGbLzEPjui3mac7PHB123Ptf0Nzd07HU1T/pjRFqYldQ44vsYNSo1kqCmLDM8rxQKJ7SXbfXaQ4hZxNW6qrIcRG2VMDXYxCzN0DxNJnVUoxZB6gApM4AHBTqDsyoHir299scECFeFkz1Ca+XrUixo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YtWb0fpG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YtWb0fpG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1C70DC113CF; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=da0nPHLb+kjJFizEGwI7X27ZL2AoDem8fuVWASExNUk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YtWb0fpGpaC5RQFl1oG57UBX04lywvgRfn7jPwrdJFTkMWs+DQhLOTMe0gqjuUotY DNtdIBxgOCis28lb+2W+fIu/SbXE0DewOHj2Nf+IoHt179LCMUfTiwRC6jMWY76wQB 4s3cDO4mFLINRHNAdlLDw+pQ9UuIDCYqgbSHgYZWIq0xccrgzyDPaHMD7sa6/tB3AU dlTYUjPdLL3gs7YUCb8cy76eeFc2tU8zN4833pn6njP4yNkWI9D2PCqThSNk0OntcV nrC1XbBmwO6X8o+cxyO24FHmH3IZ8PCH5XxLfI4MO9qRv0oFNwlVVQNX80q8q2Y78r iNmibGXZmEpyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13A5CCA1002; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:27 +0000 Subject: [PATCH v2 14/22] usb: typec: tipd: Read data status in probe and cache its value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-14-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1479; i=sven@kernel.org; h=from:subject:message-id; bh=apIjO4uQjpk9TWGcbO53K/zBq9zHh6dxC3iJN9qbzAg=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesEWvvkpfDdwbIq58dkrs5JWbO3Nq4j/uNK7eMb9P2 nWR0XT1jlIWBjEOBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBEzigy/C9iTP1zclKuQOgN HQa1o2vmyBk161wzFDCcO8vjY/S+gJWMDMdfcIcKb9p3e2Ko995NBRkib2UeFs6zcP9z5umx0p7 F+pwA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Just like for power status we also need to keep track of data status to be able to detect mode changes once we introduce de-bouncing for CD321x. Read it during probe and keep a cached copy of its value. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index e6e9730ee6dacd8c1271b1d52a02da49ff248d3e..b558fc5ecbc35a9dabbf33c444f= 38173740af7c3 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -176,6 +176,7 @@ struct tps6598x { =20 int wakeup; u32 status; /* status reg */ + u32 data_status; u16 pwr_status; struct delayed_work wq_poll; =20 @@ -538,6 +539,7 @@ static bool tps6598x_read_data_status(struct tps6598x *= tps) dev_err(tps->dev, "failed to read data status: %d\n", ret); return false; } + tps->data_status =3D data_status; =20 if (tps->data->trace_data_status) tps->data->trace_data_status(data_status); @@ -1551,6 +1553,8 @@ static int tps6598x_probe(struct i2c_client *client) if (status & TPS_STATUS_PLUG_PRESENT) { if (!tps6598x_read_power_status(tps)) goto err_unregister_port; + if (!tps->data->read_data_status(tps)) + goto err_unregister_port; ret =3D tps6598x_connect(tps, status); if (ret) dev_err(&client->dev, "failed to register partner\n"); --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56C372EDD65; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=gTatnYs35Gxzb0YN/6h/KaXnmYMVyf1O5dPyG0cbGSXCCx/PVFyUaArzPhTXLfh5813gjD62yGqOBNpfKbPZZcjJmgG6rNhhKI+b11haUUKLMk1TY9z/UgT5wWjWeIM5hZWAEfrGWaR2+aNAFCCkBUSI0jrYZzlDQjhm861k300= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=vTOzT8r2YeUKns548xNws17SI6VqxW0xAr9JLLUMYnA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TynsF+A73O0d/5URoqZFwjwlcZcpRBNv5wY22k6qXzs4JTdkf2BhGLP0CzDigHPqPCMuMWZ96mN1h+6sQLPaVPsK2VFrrxcNDR74/mfxycPpgb8hn6mte7Z7yQCSNRFWePsw50CBTkIcn/p3fhBIPATtfW8YZljGolyGVILWO1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KDt9SkZj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KDt9SkZj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2BED2C4CEF9; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=vTOzT8r2YeUKns548xNws17SI6VqxW0xAr9JLLUMYnA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KDt9SkZjLUsy7OTrLX65YM7bIhj1wMiItq7ko9UyFER6tv5tVDfWDnju/ajw43/t9 zKeuuQIErMR/e5cOaq7Knqoxgl6uYg74XEUclhJlNsjWe84whZpNh30cBC0FHsn7L/ 9tlG5f/NdkraHPdsCHpA7Geoiuhe0ZH4H0jhhLjwjBi/taLG3R9vRC0XgBnjwM0/to vvItIUHo/M0LL4ybEjSTlGjCS9FXYFqnQHj7S0sucK0IvYaZ4WH3f4Hyar762PIATm TzcPaRF5mRK414n6XUJikNcf6zMqvN1Oj7aj9dE59YDJtBB8/QglAlFg0FKY4PZTby TZUS+vERIlDVQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22DE1CAC582; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:28 +0000 Subject: [PATCH v2 15/22] usb: typec: tipd: Handle mode transitions for CD321x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-15-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16156; i=sven@kernel.org; h=from:subject:message-id; bh=BPw90ansI4AI6ftYUAHh2O+6y+Wx73TtD8G3wAHsLlM=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesMUpE37xvbJastc1QXE/Y3vUhM6FPL/TWoRnst6bw m710PtORykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAiASmMDJO2Fzf8nbv9xF3/ og2TAvfoTG4xFA1ZlaujsOL52vNPdJgY/vvtLde0WW1yc25EuIRt4MTKx9+Njnb8NlhUcvFtxes lp5kB X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin On Apple Silicon machines there is no control over which alt mode is chosen. The CD321x' firmware negotiates the target mode on its own and only lets the main CPU know after the mode has already been chosen. Especially after plugging a new cable in this can result to quick mode changes from e.g. power only -> USB3 only -> USB3+DisplayPort in a short time. It is not possile to influence this in any way and we also do not get direct access to the PDOs or VDOs exchanged via USB PD. Additionally, mode changes must be tightly synchronized between DWC3 and the Type C PHY and most mode changes require a full reset of DWC3 to make the port work correctly. On the machines the usb role change is used to reset the controller. The role change is additionally done synchronously from the callback instead of relying on a workqueue as usual in order to avoid any races which can, in the worst case, result in resetting the entire SoC if Type-C PHY and DWC3 are out of sync. To be able to control all this we trigger the entire process in the correct order directly from the TIPD driver and de-bounce any mode changes to avoid tearing down and re-setting DWC3 back up multiple times any time a new connection is made. Signed-off-by: Hector Martin Co-developed-by: Sven Peter Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 297 ++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 293 insertions(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index b558fc5ecbc35a9dabbf33c444f38173740af7c3..95218e8be65dbbb594465961b1f= da76eed1e266c 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,9 @@ struct tps6598x_intel_vid_status_reg { #define TPS_TASK_TIMEOUT 1 #define TPS_TASK_REJECTED 3 =20 +/* Debounce delay for mode changes, in milliseconds */ +#define CD321X_DEBOUNCE_DELAY_MS 500 + enum { TPS_MODE_APP, TPS_MODE_BOOT, @@ -145,6 +149,7 @@ struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; size_t tps_struct_size; + void (*remove)(struct tps6598x *tps); int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*unregister_port)(struct tps6598x *tps); void (*trace_data_status)(u32 status); @@ -155,6 +160,7 @@ struct tipd_data { int (*switch_power_state)(struct tps6598x *tps, u8 target_state); bool (*read_data_status)(struct tps6598x *tps); int (*reset)(struct tps6598x *tps); + int (*connect)(struct tps6598x *tps, u32 status); }; =20 struct tps6598x { @@ -183,6 +189,17 @@ struct tps6598x { const struct tipd_data *data; }; =20 +struct cd321x_status { + u32 status; + u32 pwr_status; + u32 data_status; + u32 status_changed; + struct usb_pd_identity partner_identity; + struct tps6598x_dp_sid_status_reg dp_sid_status; + struct tps6598x_intel_vid_status_reg intel_vid_status; + struct tps6598x_usb4_status_reg usb4_status; +}; + struct cd321x { struct tps6598x tps; =20 @@ -192,6 +209,13 @@ struct cd321x { =20 struct typec_altmode *port_altmode_dp; struct typec_altmode *port_altmode_tbt; + + struct typec_mux *mux; + struct typec_mux_state state; + + struct cd321x_status update_status; + struct delayed_work update_work; + struct usb_pd_identity cur_partner_identity; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -613,9 +637,229 @@ static void tps6598x_handle_plug_event(struct tps6598= x *tps, u32 status) } } =20 +static void cd321x_typec_update_mode(struct tps6598x *tps, struct cd321x_s= tatus *st) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + if (!(st->data_status & TPS_DATA_STATUS_DATA_CONNECTION)) { + if (cd321x->state.mode =3D=3D TYPEC_STATE_SAFE) + return; + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & TPS_DATA_STATUS_DP_CONNECTION) { + struct typec_displayport_data dp_data; + unsigned long mode; + + switch (TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT(st->data_status)) { + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_A: + mode =3D TYPEC_DP_STATE_A; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_B: + mode =3D TYPEC_DP_STATE_B; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_C: + mode =3D TYPEC_DP_STATE_C; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_D: + mode =3D TYPEC_DP_STATE_D; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_E: + mode =3D TYPEC_DP_STATE_E; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_F: + mode =3D TYPEC_DP_STATE_F; + break; + default: + dev_err(tps->dev, "Invalid DP pin assignment\n"); + return; + } + + if (cd321x->state.alt =3D=3D cd321x->port_altmode_dp && + cd321x->state.mode =3D=3D mode) { + return; + } + + dp_data.status =3D le32_to_cpu(st->dp_sid_status.status_rx); + dp_data.conf =3D le32_to_cpu(st->dp_sid_status.configure); + cd321x->state.alt =3D cd321x->port_altmode_dp; + cd321x->state.data =3D &dp_data; + cd321x->state.mode =3D mode; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & TPS_DATA_STATUS_TBT_CONNECTION) { + struct typec_thunderbolt_data tbt_data; + + if (cd321x->state.alt =3D=3D cd321x->port_altmode_tbt && + cd321x->state.mode =3D=3D TYPEC_TBT_MODE) + return; + + tbt_data.cable_mode =3D le16_to_cpu(st->intel_vid_status.cable_mode); + tbt_data.device_mode =3D le16_to_cpu(st->intel_vid_status.device_mode); + tbt_data.enter_vdo =3D le16_to_cpu(st->intel_vid_status.enter_vdo); + cd321x->state.alt =3D cd321x->port_altmode_tbt; + cd321x->state.mode =3D TYPEC_TBT_MODE; + cd321x->state.data =3D &tbt_data; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & CD321X_DATA_STATUS_USB4_CONNECTION) { + struct enter_usb_data eusb_data; + + if (cd321x->state.alt =3D=3D NULL && cd321x->state.mode =3D=3D TYPEC_MOD= E_USB4) + return; + + eusb_data.eudo =3D le32_to_cpu(st->usb4_status.eudo); + eusb_data.active_link_training =3D + !!(st->data_status & TPS_DATA_STATUS_ACTIVE_LINK_TRAIN); + + cd321x->state.alt =3D NULL; + cd321x->state.data =3D &eusb_data; + cd321x->state.mode =3D TYPEC_MODE_USB4; + typec_mux_set(cd321x->mux, &cd321x->state); + } else { + if (cd321x->state.alt =3D=3D NULL && cd321x->state.mode =3D=3D TYPEC_STA= TE_USB) + return; + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_USB; + cd321x->state.data =3D NULL; + typec_mux_set(cd321x->mux, &cd321x->state); + } +} + +static void cd321x_update_work(struct work_struct *work) +{ + struct cd321x *cd321x =3D container_of(to_delayed_work(work), + struct cd321x, update_work); + struct tps6598x *tps =3D &cd321x->tps; + struct cd321x_status st; + + guard(mutex)(&tps->lock); + + st =3D cd321x->update_status; + cd321x->update_status.status_changed =3D 0; + + bool old_connected =3D !!tps->partner; + bool new_connected =3D st.status & TPS_STATUS_PLUG_PRESENT; + bool was_disconnected =3D st.status_changed & TPS_STATUS_PLUG_PRESENT; + + bool usb_connection =3D st.data_status & + (TPS_DATA_STATUS_USB2_CONNECTION | TPS_DATA_STATUS_USB3_CONNECTIO= N); + + enum usb_role old_role =3D usb_role_switch_get_role(tps->role_sw); + enum usb_role new_role =3D USB_ROLE_NONE; + enum typec_pwr_opmode pwr_opmode =3D TYPEC_PWR_MODE_USB; + enum typec_orientation orientation =3D TYPEC_ORIENTATION_NONE; + + if (usb_connection) { + if (tps->data_status & TPS_DATA_STATUS_USB_DATA_ROLE) + new_role =3D USB_ROLE_DEVICE; + else + new_role =3D USB_ROLE_HOST; + } + + if (new_connected) { + pwr_opmode =3D TPS_POWER_STATUS_PWROPMODE(st.pwr_status); + orientation =3D TPS_STATUS_TO_UPSIDE_DOWN(st.status) ? + TYPEC_ORIENTATION_REVERSE : TYPEC_ORIENTATION_NORMAL; + } + + bool is_pd =3D pwr_opmode =3D=3D TYPEC_PWR_MODE_PD; + bool partner_changed =3D old_connected && new_connected && + (was_disconnected || + (is_pd && memcmp(&st.partner_identity, + &cd321x->cur_partner_identity, sizeof(struct usb_pd_identity)))); + + /* If we are switching from an active role, transition to USB_ROLE_NONE f= irst */ + if (old_role !=3D USB_ROLE_NONE && (new_role !=3D old_role || was_disconn= ected)) + usb_role_switch_set_role(tps->role_sw, USB_ROLE_NONE); + + /* Process partner disconnection or change */ + if (!new_connected || partner_changed) { + if (!IS_ERR(tps->partner)) + typec_unregister_partner(tps->partner); + tps->partner =3D NULL; + } + + /* If there was a disconnection, set PHY to off */ + if (!new_connected || was_disconnected) { + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; + typec_set_mode(tps->port, TYPEC_STATE_SAFE); + } + + /* Update Type-C properties */ + typec_set_pwr_opmode(tps->port, pwr_opmode); + typec_set_pwr_role(tps->port, TPS_STATUS_TO_TYPEC_PORTROLE(st.status)); + typec_set_vconn_role(tps->port, TPS_STATUS_TO_TYPEC_VCONN(st.status)); + typec_set_orientation(tps->port, orientation); + typec_set_data_role(tps->port, TPS_STATUS_TO_TYPEC_DATAROLE(st.status)); + power_supply_changed(tps->psy); + + /* If the plug is disconnected, we are done */ + if (!new_connected) + return; + + /* Set up partner if we were previously disconnected (or changed). */ + if (!tps->partner) { + struct typec_partner_desc desc; + + desc.usb_pd =3D is_pd; + desc.accessory =3D TYPEC_ACCESSORY_NONE; /* XXX: handle accessories */ + desc.identity =3D NULL; + + if (desc.usb_pd) + desc.identity =3D &st.partner_identity; + + tps->partner =3D typec_register_partner(tps->port, &desc); + if (IS_ERR(tps->partner)) + dev_warn(tps->dev, "%s: failed to register partnet\n", __func__); + + if (desc.identity) { + typec_partner_set_identity(tps->partner); + cd321x->cur_partner_identity =3D st.partner_identity; + } + } + + /* Update the TypeC MUX/PHY state */ + cd321x_typec_update_mode(tps, &st); + + /* Launch the USB role switch */ + usb_role_switch_set_role(tps->role_sw, new_role); + + power_supply_changed(tps->psy); +} + +static void cd321x_queue_status(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + cd321x->update_status.status_changed |=3D cd321x->update_status.status ^ = tps->status; + + cd321x->update_status.status =3D tps->status; + cd321x->update_status.pwr_status =3D tps->pwr_status; + cd321x->update_status.data_status =3D tps->data_status; + + cd321x->update_status.partner_identity =3D tps->partner_identity; + cd321x->update_status.dp_sid_status =3D cd321x->dp_sid_status; + cd321x->update_status.intel_vid_status =3D cd321x->intel_vid_status; + cd321x->update_status.usb4_status =3D cd321x->usb4_status; +} + +static int cd321x_connect(struct tps6598x *tps, u32 status) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + tps->status =3D status; + cd321x_queue_status(tps); + schedule_delayed_work(&cd321x->update_work, msecs_to_jiffies(CD321X_DEBOU= NCE_DELAY_MS)); + + return 0; +} + static irqreturn_t cd321x_interrupt(int irq, void *data) { struct tps6598x *tps =3D data; + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); u64 event =3D 0; u32 status; int ret; @@ -652,9 +896,15 @@ static irqreturn_t cd321x_interrupt(int irq, void *dat= a) if (!tps->data->read_data_status(tps)) goto err_unlock; =20 - /* Handle plug insert or removal */ - if (event & APPLE_CD_REG_INT_PLUG_EVENT) - tps6598x_handle_plug_event(tps, status); + tps->status =3D status; + cd321x_queue_status(tps); + + /* + * Cancel pending work if not already running. + * We will requeue the work after CD321X_DEBOUNCE_DELAY_MS regardless. + */ + cancel_delayed_work(&cd321x->update_work); + schedule_delayed_work(&cd321x->update_work, msecs_to_jiffies(CD321X_DEBOU= NCE_DELAY_MS)); =20 err_unlock: mutex_unlock(&tps->lock); @@ -1014,6 +1264,13 @@ cd321x_register_port(struct tps6598x *tps, struct fw= node_handle *fwnode) struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); int ret; =20 + /* + * This is only called from _probe such that update_work can be + * initialized and then scheduled for the first time to handle + * plugs already connected at boot time. + */ + INIT_DELAYED_WORK(&cd321x->update_work, cd321x_update_work); + ret =3D tps6598x_register_port(tps, fwnode); if (ret) return ret; @@ -1022,10 +1279,26 @@ cd321x_register_port(struct tps6598x *tps, struct f= wnode_handle *fwnode) if (ret) goto err_unregister_port; =20 + cd321x->mux =3D fwnode_typec_mux_get(fwnode); + if (IS_ERR(cd321x->mux)) { + ret =3D PTR_ERR(cd321x->mux); + goto err_unregister_altmodes; + } + + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; typec_set_mode(tps->port, TYPEC_STATE_SAFE); =20 return 0; =20 +err_unregister_altmodes: + if (cd321x->port_altmode_dp) + typec_unregister_altmode(cd321x->port_altmode_dp); + if (cd321x->port_altmode_tbt) + typec_unregister_altmode(cd321x->port_altmode_tbt); + cd321x->port_altmode_dp =3D NULL; + cd321x->port_altmode_tbt =3D NULL; err_unregister_port: typec_unregister_port(tps->port); return ret; @@ -1042,6 +1315,8 @@ cd321x_unregister_port(struct tps6598x *tps) { struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); =20 + if (cd321x->mux) + typec_mux_put(cd321x->mux); typec_unregister_altmode(cd321x->port_altmode_dp); cd321x->port_altmode_dp =3D NULL; typec_unregister_altmode(cd321x->port_altmode_tbt); @@ -1454,6 +1729,13 @@ tps25750_register_port(struct tps6598x *tps, struct = fwnode_handle *fwnode) return 0; } =20 +static void cd321x_remove(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + cancel_delayed_work_sync(&cd321x->update_work); +} + static int tps6598x_probe(struct i2c_client *client) { const struct tipd_data *data; @@ -1555,7 +1837,7 @@ static int tps6598x_probe(struct i2c_client *client) goto err_unregister_port; if (!tps->data->read_data_status(tps)) goto err_unregister_port; - ret =3D tps6598x_connect(tps, status); + ret =3D tps->data->connect(tps, status); if (ret) dev_err(&client->dev, "failed to register partner\n"); } @@ -1612,6 +1894,9 @@ static void tps6598x_remove(struct i2c_client *client) else devm_free_irq(tps->dev, client->irq, tps); =20 + if (tps->data->remove) + tps->data->remove(tps); + tps6598x_disconnect(tps, 0); tps->data->unregister_port(tps); usb_role_switch_put(tps->role_sw); @@ -1682,6 +1967,7 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct cd321x), + .remove =3D cd321x_remove, .register_port =3D cd321x_register_port, .unregister_port =3D cd321x_unregister_port, .trace_data_status =3D trace_cd321x_data_status, @@ -1691,6 +1977,7 @@ static const struct tipd_data cd321x_data =3D { .read_data_status =3D cd321x_read_data_status, .reset =3D cd321x_reset, .switch_power_state =3D cd321x_switch_power_state, + .connect =3D cd321x_connect, }; =20 static const struct tipd_data tps6598x_data =3D { @@ -1708,6 +1995,7 @@ static const struct tipd_data tps6598x_data =3D { .init =3D tps6598x_init, .read_data_status =3D tps6598x_read_data_status, .reset =3D tps6598x_reset, + .connect =3D tps6598x_connect, }; =20 static const struct tipd_data tps25750_data =3D { @@ -1725,6 +2013,7 @@ static const struct tipd_data tps25750_data =3D { .init =3D tps25750_init, .read_data_status =3D tps6598x_read_data_status, .reset =3D tps25750_reset, + .connect =3D tps6598x_connect, }; =20 static const struct of_device_id tps6598x_of_match[] =3D { --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D492F067F; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=LeahsBqpyUcVYMzbMBerJXfqdWJguMmJvJABtI41Ht0+b+81WQyhDsFXuHG32KbxpnDJ6gI1QMWYw/L+qZ1LcYiKIkU0C+WkezeraG/+0Xk+tRLHo36odLe3vUuGoLMqTwY7SIq0TquUu8gA8N1trpTpL3bJaOhM6Ug4HNGh1wU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=osM0eVhm5EoDlyY0FaSY3Lj8njN0B4a30sboZPHWvdE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mgtJTqIkAo06TpeC5bQH+SAXJl2yYzr4Skksc2IL3qSwkywv4dSKh0H7nzxbCRJ3WiJQmCAsOL9leVlmcc8D2GHNih+bKRQNmUgC+RMHpUdgmQlGV7LUf62v+58CtAkQEfimFNtbjyUkVMDyr0JOQ4xUho+KD3p1RI0LBCb3apA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uNlgs0cg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uNlgs0cg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3B8C8C4AF10; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=osM0eVhm5EoDlyY0FaSY3Lj8njN0B4a30sboZPHWvdE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uNlgs0cgIfXVTqUOgzBPJyDbsBhQ5DgX8JsXcG5fxshtzIkJbR6KTgFdguI4+YX7X gldL7olsKsz+941SFtMWC/8G2NhbkmtS67EfPSMO+8Ay3nLOtsB0fQkGZAwP6/YQt/ /oq5oZ7ejnATZcX4g7iCIfjeuxWf5dUjZKB4f7ybLAD+QjKstelg5liiXoSpacdf+5 o23W9Xzj+s7PdXa8ARh8fAoIHiinMzdnmlRRzsYrg7/iPfrwmqA3Aq397BCjiFrJZk 14jZWORpn+ztYMYw2qsH1V5tXoPrYmUQZHQGwGGYySFW9axJd2ZJc7zkcX1tae433W ilp1fS7jg125A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32424CA1012; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:29 +0000 Subject: [PATCH v2 16/22] dt-bindings: phy: Add Apple Type-C PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-16-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7993; i=sven@kernel.org; h=from:subject:message-id; bh=osM0eVhm5EoDlyY0FaSY3Lj8njN0B4a30sboZPHWvdE=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesCX61T8PcMzoLs+VkV5dP5frQfnk3W+9O7tu5Rqym 5w9XZ3aUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZjI5zUM//TaEk33/1SYHdl7 1jrvbWsfS4JT/4SHRTpuK2xS/rf3/WZkmJB/WfqI+Pyz3y9GGxqEepqknuhviFXqWipx2fLxrhU lDAA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Apple's Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs. The PHY handles muxing between these different protocols and also provides the reset controller for the attached dwc3 USB controller. Signed-off-by: Sven Peter --- .../devicetree/bindings/phy/apple,atcphy.yaml | 213 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/apple,atcphy.yaml b/Docu= mentation/devicetree/bindings/phy/apple,atcphy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a863fe3a8f6d80a113e495e8425= 775c91e4cd10c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/apple,atcphy.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Type-C PHY (ATCPHY) + +maintainers: + - Sven Peter + +description: + The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, + USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon So= Cs. + + The PHY handles muxing between these different protocols and also provid= es the + reset controller for the attached DWC3 USB controller. + + The PHY is designed for USB4 operation and does not handle individual + differential pairs as distinct DisplayPort lanes. Any reference to lane = in + this binding hence refers to two differential pairs (RX and TX) as used = in USB + terminology. + +allOf: + - $ref: /schemas/usb/usb-switch.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - apple,t6000-atcphy + - apple,t6020-atcphy + - apple,t8112-atcphy + - const: apple,t8103-atcphy + - const: apple,t8103-atcphy + + reg: + items: + - description: Common controls for all PHYs (USB2/3/4, DisplayPort, = Thunderbolt) + - description: DisplayPort Alternate Mode PHY specific controls + - description: AXI to Apple Fabric interconnect controls, only modif= ied by tunables + - description: USB2 PHY specific controls + - description: USB3 PIPE interface controls + + reg-names: + items: + - const: core + - const: lpdptx + - const: axi2af + - const: usb2phy + - const: pipehandler + + "#phy-cells": + const: 1 + + "#reset-cells": + const: 0 + + mode-switch: true + orientation-switch: true + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB3 controller + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the DisplayPort controller + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB4/Thunderbolt controller + + apple,tunable-axi2af: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + AXI2AF tunables. + + This array is filled with 3-tuples each containing three 32-bit valu= es + , , and by the bootloader. + The driver will use these to configure the PHY by reading from each + register, ANDing it with , ORing it with , and storing = the + result back to the register. + These values slightly differ even between different chips of the same + generation and are likely calibration values determined by Apple at + manufacturing time. + + apple,tunable-common: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Common tunables required for all modes, see apple,tunable-axi2af for= details. + + apple,tunable-fuses: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Fuse based tunables required for all modes, see apple,tunable-axi2af= for details. + + apple,tunable-lane0-usb: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB tunables on lane 0, see apple,tunable-axi2af for details. + + apple,tunable-lane1-usb: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB tunables on lane 1, see apple,tunable-axi2af for details. + + apple,tunable-lane0-cio: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB4/Thunderbolt ("converged IO") tunables on lane 0, see apple,tuna= ble-axi2af for details. + + apple,tunable-lane1-cio: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB4/Thunderbolt ("converged IO") tunables on lane 1, see apple,tuna= ble-axi2af for details. + + apple,tunable-lane0-dp: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + DisplayPort tunables on lane 0, see apple,tunable-axi2af for details. + + Note that lane here refers to a USB RX and TX pair re-used for Displ= ayPort + and not to an individual DisplayPort differential lane. + + apple,tunable-lane1-dp: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + DisplayPort tunables on lane 1, see apple,tunable-axi2af for details. + + Note that lane here refers to a USB RX and TX pair re-used for Displ= ayPort + and not to an individual DisplayPort differential lane. + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - "#reset-cells" + - orientation-switch + - mode-switch + - power-domains + - ports + +additionalProperties: false + +examples: + - | + phy@83000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x83000000 0x4c000>, + <0x83050000 0x8000>, + <0x80000000 0x4000>, + <0x82a90000 0x4000>, + <0x82a84000 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc0_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&typec_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&dwc3_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + endpoint { + remote-endpoint =3D <&dcp_dp_out>; + }; + }; + + port@3 { + reg =3D <3>; + + endpoint { + remote-endpoint =3D <&acio_tbt_out>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e147e1b919d5737a34e684ec587872ce591c641a..c4cbae63b0c0d42042e12d366e4= a32d7ca3711ea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2393,6 +2393,7 @@ F: Documentation/devicetree/bindings/nvme/apple,nvme-= ans.yaml F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml F: Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml +F: Documentation/devicetree/bindings/phy/apple,atcphy.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B7FC2F3617; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=iMbJAvQJv35ibef+ArCYkOYx4VTsJCGRdMIMvAQmWEX/bwjZBpGPtL+100y0KvqRiyQSBdrHokaae5yU8zp1XOn/gg9y2AzpcMe6ZXquuxP+0NMi7+LrjOOIpePF1DmOcUD/9cFRF4hzMhAnSuCUDb5qgMuSo+OhUexzO01L+X4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=lzelPEXSZTkAt+allO9OotxrvW+99EFSJPCR1h9x6Yo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BlqozIgYoEog9QXOvNSSbcfziIeTPq3Pd2skyrvawrFrhXtJS/JwYlRYZa5ZFGTRnMjGy8FwnHM5x2qkJp/gegxvL+HyInKnJe8hEYx6wlKQEeUH58vSE85rLr2xobuFqPVsKHQfK+ZnfqmdMEu/g1HybEncLmvgpTZE/IkYAhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LJqTYWep; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LJqTYWep" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5981CC113D0; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=lzelPEXSZTkAt+allO9OotxrvW+99EFSJPCR1h9x6Yo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LJqTYWepXzKTLRMxGgLVWIEHNdEEjcdx9WpG0AKmkfVkRta0jqV7Foh0Hq6EX5Abb 7b3ozwsHhDGtEQetpvBNrwkRCiTGD/Za3SY0v+V5vacrgyy+obWnjWXGFnj9DJAgaI GU3bl8iIxYddARwxe5CTo3UwDfLgmDJyCthWv1XtGCqaXdB70h3lXKDcvtK0NYtMhb AoYb6RXv/XAcI+Bmw/6YClBGQDIqKWDK3XBdlXkwfsMGyPDUAOQ6SqrGp4JxSG4awP MxgsdGd3LMcbl7RQOjCOqqeLrBCsHbJGtecOh1wrM6/0lFcGaX9GC4VbxbE4RBFyum HzxwSfbe/QRUA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 406B6CA0FED; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:30 +0000 Subject: [PATCH v2 17/22] soc: apple: Add hardware tunable support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-17-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6132; i=sven@kernel.org; h=from:subject:message-id; bh=lzelPEXSZTkAt+allO9OotxrvW+99EFSJPCR1h9x6Yo=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesCXvLq1+k2bPsV9yM+OsT+ZKdhFWjw5f750Yn9zU5 FKXtI+vo5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjCRO6UM/7NfTLpgeGPuFkWB 7ewfrU44BidaOa/blxpYMM11XVXgnmcM//Q6X7Qadql9VdPLPp6qcbuj7l7dxJnxrnfVfIz9Rb4 bsAEA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Various hardware, like the Type-C PHY or the Thunderbolt/USB4 NHI, present on Apple SoCs need machine-specific tunables passed from our bootloader m1n1 to the device tree. Add generic helpers so that we don't have to duplicate this across multiple drivers. Signed-off-by: Sven Peter Reviewed-by: Alyssa Rosenzweig --- drivers/soc/apple/Kconfig | 4 +++ drivers/soc/apple/Makefile | 3 ++ drivers/soc/apple/tunable.c | 71 +++++++++++++++++++++++++++++++++++= ++++ include/linux/soc/apple/tunable.h | 60 +++++++++++++++++++++++++++++++++ 4 files changed, 138 insertions(+) diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig index 6388cbe1e56b5a9d90acad3ee2377ed6ac0d207d..f266b70fd9620cc940dc685f7eb= 2972c21a361df 100644 --- a/drivers/soc/apple/Kconfig +++ b/drivers/soc/apple/Kconfig @@ -41,6 +41,10 @@ config APPLE_SART =20 Say 'y' here if you have an Apple SoC. =20 +config APPLE_TUNABLE + tristate + depends on ARCH_APPLE || COMPILE_TEST + endmenu =20 endif diff --git a/drivers/soc/apple/Makefile b/drivers/soc/apple/Makefile index 4d9ab8f3037b7159771d8817fa507ba29f99ae10..0b85ab61aefe131349a67d0aa80= 204edd8e89925 100644 --- a/drivers/soc/apple/Makefile +++ b/drivers/soc/apple/Makefile @@ -8,3 +8,6 @@ apple-rtkit-y =3D rtkit.o rtkit-crashlog.o =20 obj-$(CONFIG_APPLE_SART) +=3D apple-sart.o apple-sart-y =3D sart.o + +obj-$(CONFIG_APPLE_TUNABLE) +=3D apple-tunable.o +apple-tunable-y =3D tunable.o diff --git a/drivers/soc/apple/tunable.c b/drivers/soc/apple/tunable.c new file mode 100644 index 0000000000000000000000000000000000000000..c54da8ef28cef16118c518c761f= 95e8dd9f78002 --- /dev/null +++ b/drivers/soc/apple/tunable.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from dev= ice + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#include +#include +#include +#include + +struct apple_tunable *devm_apple_tunable_parse(struct device *dev, + struct device_node *np, + const char *name) +{ + struct apple_tunable *tunable; + struct property *prop; + const __be32 *p; + size_t sz; + int i; + + prop =3D of_find_property(np, name, NULL); + if (!prop) + return ERR_PTR(-ENOENT); + + if (prop->length % (3 * sizeof(u32))) + return ERR_PTR(-EINVAL); + sz =3D prop->length / (3 * sizeof(u32)); + + tunable =3D devm_kzalloc(dev, + sizeof(*tunable) + sz * sizeof(*tunable->values), + GFP_KERNEL); + if (!tunable) + return ERR_PTR(-ENOMEM); + tunable->sz =3D sz; + + for (i =3D 0, p =3D NULL; i < tunable->sz; ++i) { + p =3D of_prop_next_u32(prop, p, &tunable->values[i].offset); + p =3D of_prop_next_u32(prop, p, &tunable->values[i].mask); + p =3D of_prop_next_u32(prop, p, &tunable->values[i].value); + } + + return tunable; +} +EXPORT_SYMBOL(devm_apple_tunable_parse); + +void apple_tunable_apply(void __iomem *regs, struct apple_tunable *tunable) +{ + size_t i; + + for (i =3D 0; i < tunable->sz; ++i) { + u32 val, old_val; + + val =3D old_val =3D readl_relaxed(regs + tunable->values[i].offset); + val &=3D ~tunable->values[i].mask; + val |=3D tunable->values[i].value; + if (val !=3D old_val) + writel_relaxed(val, regs + tunable->values[i].offset); + } +} +EXPORT_SYMBOL(apple_tunable_apply); + +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple Silicon hardware tunable support"); diff --git a/include/linux/soc/apple/tunable.h b/include/linux/soc/apple/tu= nable.h new file mode 100644 index 0000000000000000000000000000000000000000..3785ee2c898993328356005b636= 82f4848fc2f22 --- /dev/null +++ b/include/linux/soc/apple/tunable.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from dev= ice + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#ifndef _LINUX_SOC_APPLE_TUNABLE_H_ +#define _LINUX_SOC_APPLE_TUNABLE_H_ + +#include +#include + +/** + * Struct to store an Apple Silicon hardware tunable. + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from dev= ice + * to device such that they cannot be hardcoded in the individual drivers. + * + * @param sz Number of [offset, mask, value] tuples stored in values. + * @param values [offset, mask, value] array. + */ +struct apple_tunable { + size_t sz; + struct { + u32 offset; + u32 mask; + u32 value; + } values[]; +}; + +/** + * Parse an array of hardware tunables from the device tree. + * + * @dev: Device node used for devm_kzalloc internally. + * @np: Device node which contains the tunable array. + * @name: Name of the device tree property which contains the tunables. + * + * @return: devres allocated struct on success or PTR_ERR on failure. + */ +struct apple_tunable *devm_apple_tunable_parse(struct device *dev, + struct device_node *np, + const char *name); + +/** + * Apply a previously loaded hardware tunable. + * + * @param regs: MMIO to which the tunable will be applied. + * @param tunable: Pointer to the tunable. + */ +void apple_tunable_apply(void __iomem *regs, struct apple_tunable *tunable= ); + +#endif --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B98A2F3621; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=m+A1aYSn0pzAzXWzm6tLBU6wt5gO7+D7C3VCQr0MlgyW20p8gsSN6uklPAG6tKBaeMhET/6aAB0nPInBRmKyEWdIjtulcBu3ZDfgzurVgot9DwoNurNQuUFw0PrvdTqm0R9Hsg7tLHN/ogSfYmDq3s121FujYTi0/0NDxbDLi0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=JlounR2B218/5GDB/DzoDGbujS2tERlkkizEl5xNCH4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L9yXzZN+bHk5bNSY8g9GJ8Ia/ff5q7lSuragjF8apdwooT+qMgEJ6jYPu8qqtA3LImgzDTrz2S79WefTL2j68jlTp74gC7NXVPcqIRz8BkLDiUw08tBPREjWlX5G0R8yMf9tLIpz7EItv89IogjUahLe0n29X1LXYlHADvhB9r0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IJMZgeRP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IJMZgeRP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 66A41C4AF0E; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=JlounR2B218/5GDB/DzoDGbujS2tERlkkizEl5xNCH4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IJMZgeRP5+mWvTOFA1Psqj09AzHAxfkdSns67uh7I0+toTuKSoxB8AiHsxjSWwOzv 5TCmkOAyQu/e8CJa4OW8wHG8JF68PKLUR5ztzvLDSCnJokUHSjb5buTJUkA4hFDc3u +ZviU9WU1iLMmgLqzmia03vatbfKbTjvbnoPFh/ci2bqwyGjhu57cKlw5jJD04jXg+ ADMnfHwDLBDZpuKDmlf5zzUV4FWqp3eGJpCVYCgAStJFMWzHMQohAJ61r01+YrT4sx Ta26ZU3YG9QsXEjJAuLxHaYCCdWFKZHQu44KdxIufQQLi++39yhx2IO1FWnt3nElp5 RdmLhgQLRf5Bg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F02CA1002; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:31 +0000 Subject: [PATCH v2 18/22] phy: apple: Add Apple Type-C PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-18-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=82566; i=sven@kernel.org; h=from:subject:message-id; bh=JlounR2B218/5GDB/DzoDGbujS2tERlkkizEl5xNCH4=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesKVxWvWT7k5pdDRnPc5otHb2mtIr77b2/vTnuyL9w SNtTn5uRykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAiun6MDIemz/cvSXtlu761 +eGqFc3FfzPPPhL7x84RvSte8v3XD/aMDJ83M07q6dfrmrK7Qdl32t26p9uuPFjaOyeyh0Vjnft UVTYA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs. The PHY handles muxing between these different protocols and also provides the reset controller for the attached dwc3 USB controller. There is no documentation available for this PHY and the entire sequence of MMIO pokes has been figured out by tracing all MMIO access of Apple's driver under a thin hypervisor and correlating the register reads/writes to their kernel's debug output to find their names. Deviations from this sequence generally results in the port not working or, especially when the mode is switched to USB4 or Thunderbolt, to some watchdog resetting the entire SoC. This initial commit already introduces support for Display Port and USB4/Thunderbolt but the drivers for these are not ready. We cannot control the alternate mode negotiation and are stuck with whatever Apple's firmware decides such that any DisplayPort or USB4/Thunderbolt device will result in a correctly setup PHY but not be usable until the other drivers are upstreamed as well. Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Sven Peter Reviewed-by: Philipp Zabel --- MAINTAINERS | 1 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/apple/Kconfig | 14 + drivers/phy/apple/Makefile | 4 + drivers/phy/apple/atc.c | 2214 ++++++++++++++++++++++++++++++++++++++++= ++++ 6 files changed, 2235 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c4cbae63b0c0d42042e12d366e4a32d7ca3711ea..0f9f00f6c783531c2ddabd013f0= 2e96de15edbca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2419,6 +2419,7 @@ F: drivers/mfd/macsmc.c F: drivers/nvme/host/apple.c F: drivers/nvmem/apple-efuses.c F: drivers/nvmem/apple-spmi-nvmem.c +F: drivers/phy/apple/ F: drivers/pinctrl/pinctrl-apple-gpio.c F: drivers/power/reset/macsmc-reboot.c F: drivers/pwm/pwm-apple.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d20a0398f02550e938ce62633230d4..602339a1f14e35f1941880c71c4= 442b5fa73c9f9 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222 =20 source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" +source "drivers/phy/apple/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac46807863c9ef990beb149082238ad16..e5933f7c38337e0745ec0e32bed= 0c544e4af383a 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-y +=3D allwinner/ \ amlogic/ \ + apple/ \ broadcom/ \ cadence/ \ freescale/ \ diff --git a/drivers/phy/apple/Kconfig b/drivers/phy/apple/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..67f460512592602ae60b2245b15= 62f5f667488c9 --- /dev/null +++ b/drivers/phy/apple/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +config PHY_APPLE_ATC + tristate "Apple Type-C PHY" + depends on (ARM64 && ARCH_APPLE) || (COMPILE_TEST && !GENERIC_ATOMIC64) + depends on TYPEC + select GENERIC_PHY + select APPLE_TUNABLE + help + Enable this to add support for the Apple Type-C PHY found in + Apple Silicon M-series SoCs. This PHY supports USB2, + USB3, USB4, Thunderbolt, and DisplayPort. + + If M is selected the module will be called 'phy-apple-atc'. + diff --git a/drivers/phy/apple/Makefile b/drivers/phy/apple/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e02836a63df3b5324c5ac102b37= 9b12a24494301 --- /dev/null +++ b/drivers/phy/apple/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause + +obj-$(CONFIG_PHY_APPLE_ATC) +=3D phy-apple-atc.o +phy-apple-atc-y :=3D atc.o diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c new file mode 100644 index 0000000000000000000000000000000000000000..9213485234873fcaafeb1d1d9de= 3ddf07767d552 --- /dev/null +++ b/drivers/phy/apple/atc.c @@ -0,0 +1,2214 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* + * Apple Type-C PHY driver + * + * Copyright (C) The Asahi Linux Contributors + * Author: Sven Peter + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AUSPLL_FSM_CTRL 0x1014 + +#define AUSPLL_APB_CMD_OVERRIDE 0x2000 +#define AUSPLL_APB_CMD_OVERRIDE_REQ BIT(0) +#define AUSPLL_APB_CMD_OVERRIDE_ACK BIT(1) +#define AUSPLL_APB_CMD_OVERRIDE_UNK28 BIT(28) +#define AUSPLL_APB_CMD_OVERRIDE_CMD GENMASK(27, 3) + +#define AUSPLL_FREQ_DESC_A 0x2080 +#define AUSPLL_FD_FREQ_COUNT_TARGET GENMASK(9, 0) +#define AUSPLL_FD_FBDIVN_HALF BIT(10) +#define AUSPLL_FD_REV_DIVN GENMASK(13, 11) +#define AUSPLL_FD_KI_MAN GENMASK(17, 14) +#define AUSPLL_FD_KI_EXP GENMASK(21, 18) +#define AUSPLL_FD_KP_MAN GENMASK(25, 22) +#define AUSPLL_FD_KP_EXP GENMASK(29, 26) +#define AUSPLL_FD_KPKI_SCALE_HBW GENMASK(31, 30) + +#define AUSPLL_FREQ_DESC_B 0x2084 +#define AUSPLL_FD_FBDIVN_FRAC_DEN GENMASK(13, 0) +#define AUSPLL_FD_FBDIVN_FRAC_NUM GENMASK(27, 14) + +#define AUSPLL_FREQ_DESC_C 0x2088 +#define AUSPLL_FD_SDM_SSC_STEP GENMASK(7, 0) +#define AUSPLL_FD_SDM_SSC_EN BIT(8) +#define AUSPLL_FD_PCLK_DIV_SEL GENMASK(13, 9) +#define AUSPLL_FD_LFSDM_DIV GENMASK(15, 14) +#define AUSPLL_FD_LFCLK_CTRL GENMASK(19, 16) +#define AUSPLL_FD_VCLK_OP_DIVN GENMASK(21, 20) +#define AUSPLL_FD_VCLK_PRE_DIVN BIT(22) + +#define AUSPLL_DCO_EFUSE_SPARE 0x222c +#define AUSPLL_RODCO_ENCAP_EFUSE GENMASK(10, 9) +#define AUSPLL_RODCO_BIAS_ADJUST_EFUSE GENMASK(14, 12) + +#define AUSPLL_FRACN_CAN 0x22a4 +#define AUSPLL_DLL_START_CAPCODE GENMASK(18, 17) + +#define AUSPLL_CLKOUT_MASTER 0x2200 +#define AUSPLL_CLKOUT_MASTER_PCLK_DRVR_EN BIT(2) +#define AUSPLL_CLKOUT_MASTER_PCLK2_DRVR_EN BIT(4) +#define AUSPLL_CLKOUT_MASTER_REFBUFCLK_DRVR_EN BIT(6) + +#define AUSPLL_CLKOUT_DIV 0x2208 +#define AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI GENMASK(20, 16) + +#define AUSPLL_BGR 0x2214 +#define AUSPLL_BGR_CTRL_AVAIL BIT(0) + +#define AUSPLL_CLKOUT_DTC_VREG 0x2220 +#define AUSPLL_DTC_VREG_ADJUST GENMASK(16, 14) +#define AUSPLL_DTC_VREG_BYPASS BIT(7) + +#define AUSPLL_FREQ_CFG 0x2224 +#define AUSPLL_FREQ_REFCLK GENMASK(1, 0) + +#define AUS_COMMON_SHIM_BLK_VREG 0x0a04 +#define AUS_VREG_TRIM GENMASK(6, 2) + +#define AUS_UNK_A20 0x0a20 +#define AUS_UNK_A20_TX_CAL_CODE GENMASK(23, 20) + +#define ACIOPHY_CMN_SHM_STS_REG0 0x0a74 +#define ACIOPHY_CMN_SHM_STS_REG0_CMD_READY BIT(0) + +#define CIO3PLL_CLK_CTRL 0x2a00 +#define CIO3PLL_CLK_PCLK_EN BIT(1) +#define CIO3PLL_CLK_REFCLK_EN BIT(5) + +#define CIO3PLL_DCO_NCTRL 0x2a38 +#define CIO3PLL_DCO_COARSEBIN_EFUSE0 GENMASK(6, 0) +#define CIO3PLL_DCO_COARSEBIN_EFUSE1 GENMASK(23, 17) + +#define CIO3PLL_FRACN_CAN 0x2aa4 +#define CIO3PLL_DLL_CAL_START_CAPCODE GENMASK(18, 17) + +#define CIO3PLL_DTC_VREG 0x2a20 +#define CIO3PLL_DTC_VREG_ADJUST GENMASK(16, 14) + +#define ACIOPHY_CFG0 0x08 +#define ACIOPHY_CFG0_COMMON_BIG_OV BIT(1) +#define ACIOPHY_CFG0_COMMON_SMALL_OV BIT(3) +#define ACIOPHY_CFG0_COMMON_CLAMP_OV BIT(5) +#define ACIOPHY_CFG0_RX_SMALL_OV GENMASK(9, 8) +#define ACIOPHY_CFG0_RX_BIG_OV GENMASK(13, 12) +#define ACIOPHY_CFG0_RX_CLAMP_OV GENMASK(17, 16) + +#define ACIOPHY_CROSSBAR 0x4c +#define ACIOPHY_CROSSBAR_PROTOCOL GENMASK(4, 0) +#define ACIOPHY_CROSSBAR_PROTOCOL_USB4 0x0 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED 0x1 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3 0xa +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED 0xb +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP 0x10 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP_SWAPPED 0x11 +#define ACIOPHY_CROSSBAR_PROTOCOL_DP 0x14 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA GENMASK(16, 5) +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE 0x0000 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK100 0x100 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008 0x008 +#define ACIOPHY_CROSSBAR_DP_BOTH_PMA BIT(17) + +#define ACIOPHY_LANE_MODE 0x48 +#define ACIOPHY_LANE_MODE_RX0 GENMASK(2, 0) +#define ACIOPHY_LANE_MODE_TX0 GENMASK(5, 3) +#define ACIOPHY_LANE_MODE_RX1 GENMASK(8, 6) +#define ACIOPHY_LANE_MODE_TX1 GENMASK(11, 9) +#define ACIOPHY_LANE_MODE_USB4 0 +#define ACIOPHY_LANE_MODE_USB3 1 +#define ACIOPHY_LANE_MODE_DP 2 +#define ACIOPHY_LANE_MODE_OFF 3 + +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1 0x84 +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN BIT(27) +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN BIT(28) + +#define ACIOPHY_TOP_BIST_OV_CFG 0x8c +#define ACIOPHY_TOP_BIST_OV_CFG_LN0_RESET_N_OV BIT(13) +#define ACIOPHY_TOP_BIST_OV_CFG_LN0_PWR_DOWN_OV BIT(25) + +#define ACIOPHY_TOP_BIST_READ_CTRL 0x90 +#define ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE BIT(2) + +#define ACIOPHY_TOP_PHY_STAT 0x9c +#define ACIOPHY_TOP_PHY_STAT_LN0_UNK0 BIT(0) +#define ACIOPHY_TOP_PHY_STAT_LN0_UNK23 BIT(23) + +#define ACIOPHY_TOP_BIST_PHY_CFG0 0xa8 +#define ACIOPHY_TOP_BIST_PHY_CFG0_LN0_RESET_N BIT(0) + +#define ACIOPHY_TOP_BIST_PHY_CFG1 0xac +#define ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN GENMASK(13, 10) + +#define ACIOPHY_SLEEP_CTRL 0x1b0 +#define ACIOPHY_SLEEP_CTRL_TX_BIG_OV GENMASK(3, 2) +#define ACIOPHY_SLEEP_CTRL_TX_SMALL_OV GENMASK(7, 6) +#define ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV GENMASK(11, 10) + +#define ACIOPHY_PLL_PCTL_FSM_CTRL1 0x1014 +#define ACIOPHY_PLL_APB_REQ_OV_SEL GENMASK(21, 13) +#define ACIOPHY_PLL_COMMON_CTRL 0x1028 +#define ACIOPHY_PLL_WAIT_FOR_CMN_READY_BEFORE_RESET_EXIT BIT(24) + +#define ATCPHY_POWER_CTRL 0x20000 +#define ATCPHY_POWER_STAT 0x20004 +#define ATCPHY_POWER_SLEEP_SMALL BIT(0) +#define ATCPHY_POWER_SLEEP_BIG BIT(1) +#define ATCPHY_POWER_CLAMP_EN BIT(2) +#define ATCPHY_POWER_APB_RESET_N BIT(3) +#define ATCPHY_POWER_PHY_RESET_N BIT(4) + +#define ATCPHY_MISC 0x20008 +#define ATCPHY_MISC_RESET_N BIT(0) +#define ATCPHY_MISC_LANE_SWAP BIT(2) + +#define ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0 0x7000 +#define DP_PMA_BYTECLK_RESET BIT(0) +#define DP_MAC_DIV20_CLK_SEL BIT(1) +#define DPTXPHY_PMA_LANE_RESET_N BIT(2) +#define DPTXPHY_PMA_LANE_RESET_N_OV BIT(3) +#define DPTX_PCLK1_SELECT GENMASK(6, 4) +#define DPTX_PCLK2_SELECT GENMASK(9, 7) +#define DPRX_PCLK_SELECT GENMASK(12, 10) +#define DPTX_PCLK1_ENABLE BIT(13) +#define DPTX_PCLK2_ENABLE BIT(14) +#define DPRX_PCLK_ENABLE BIT(15) + +#define ACIOPHY_DP_PCLK_STAT 0x7044 +#define ACIOPHY_AUSPLL_LOCK BIT(3) + +#define LN0_AUSPMA_RX_TOP 0x9000 +#define LN0_AUSPMA_RX_EQ 0xA000 +#define LN0_AUSPMA_RX_SHM 0xB000 +#define LN0_AUSPMA_TX_TOP 0xC000 +#define LN0_AUSPMA_TX_SHM 0xD000 + +#define LN1_AUSPMA_RX_TOP 0x10000 +#define LN1_AUSPMA_RX_EQ 0x11000 +#define LN1_AUSPMA_RX_SHM 0x12000 +#define LN1_AUSPMA_TX_TOP 0x13000 +#define LN1_AUSPMA_TX_SHM 0x14000 + +#define LN_AUSPMA_RX_TOP_PMAFSM 0x0010 +#define LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV BIT(0) +#define LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ BIT(9) + +#define LN_AUSPMA_RX_TOP_TJ_CFG_RX_TXMODE 0x00F0 +#define LN_RX_TXMODE BIT(0) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0 0x00 +#define LN_TX_CLK_EN BIT(20) +#define LN_TX_CLK_EN_OV BIT(21) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1 0x04 +#define LN_RX_DIV20_RESET_N_OV BIT(29) +#define LN_RX_DIV20_RESET_N BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL2 0x08 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL3 0x0C +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL4 0x10 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL5 0x14 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL6 0x18 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL7 0x1C +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL8 0x20 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL9 0x24 +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10 0x28 +#define LN_DTVREG_ADJUST GENMASK(31, 27) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11 0x2C +#define LN_DTVREG_BIG_EN BIT(23) +#define LN_DTVREG_BIG_EN_OV BIT(24) +#define LN_DTVREG_SML_EN BIT(25) +#define LN_DTVREG_SML_EN_OV BIT(26) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12 0x30 +#define LN_TX_BYTECLK_RESET_SYNC_CLR BIT(22) +#define LN_TX_BYTECLK_RESET_SYNC_CLR_OV BIT(23) +#define LN_TX_BYTECLK_RESET_SYNC_EN BIT(24) +#define LN_TX_BYTECLK_RESET_SYNC_EN_OV BIT(25) +#define LN_TX_HRCLK_SEL BIT(28) +#define LN_TX_HRCLK_SEL_OV BIT(29) +#define LN_TX_PBIAS_EN BIT(30) +#define LN_TX_PBIAS_EN_OV BIT(31) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13 0x34 +#define LN_TX_PRE_EN BIT(0) +#define LN_TX_PRE_EN_OV BIT(1) +#define LN_TX_PST1_EN BIT(2) +#define LN_TX_PST1_EN_OV BIT(3) +#define LN_DTVREG_ADJUST_OV BIT(15) + +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL14A 0x38 +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL14B 0x3C +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL15A 0x40 +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL15B 0x44 +#define LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16 0x48 +#define LN_RXTERM_EN BIT(21) +#define LN_RXTERM_EN_OV BIT(22) +#define LN_RXTERM_PULLUP_LEAK_EN BIT(23) +#define LN_RXTERM_PULLUP_LEAK_EN_OV BIT(24) +#define LN_TX_CAL_CODE GENMASK(29, 25) +#define LN_TX_CAL_CODE_OV BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17 0x4C +#define LN_TX_MARGIN GENMASK(19, 15) +#define LN_TX_MARGIN_OV BIT(20) +#define LN_TX_MARGIN_LSB BIT(21) +#define LN_TX_MARGIN_LSB_OV BIT(22) +#define LN_TX_MARGIN_P1 GENMASK(26, 23) +#define LN_TX_MARGIN_P1_OV BIT(27) +#define LN_TX_MARGIN_P1_LSB GENMASK(29, 28) +#define LN_TX_MARGIN_P1_LSB_OV BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18 0x50 +#define LN_TX_P1_CODE GENMASK(3, 0) +#define LN_TX_P1_CODE_OV BIT(4) +#define LN_TX_P1_LSB_CODE GENMASK(6, 5) +#define LN_TX_P1_LSB_CODE_OV BIT(7) +#define LN_TX_MARGIN_PRE GENMASK(10, 8) +#define LN_TX_MARGIN_PRE_OV BIT(11) +#define LN_TX_MARGIN_PRE_LSB GENMASK(13, 12) +#define LN_TX_MARGIN_PRE_LSB_OV BIT(14) +#define LN_TX_PRE_LSB_CODE GENMASK(16, 15) +#define LN_TX_PRE_LSB_CODE_OV BIT(17) +#define LN_TX_PRE_CODE GENMASK(21, 18) +#define LN_TX_PRE_CODE_OV BIT(22) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19 0x54 +#define LN_TX_TEST_EN BIT(21) +#define LN_TX_TEST_EN_OV BIT(22) +#define LN_TX_EN BIT(23) +#define LN_TX_EN_OV BIT(24) +#define LN_TX_CLK_DLY_CTRL_TAPGEN GENMASK(27, 25) +#define LN_TX_CLK_DIV2_EN BIT(28) +#define LN_TX_CLK_DIV2_EN_OV BIT(29) +#define LN_TX_CLK_DIV2_RST BIT(30) +#define LN_TX_CLK_DIV2_RST_OV BIT(31) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL20 0x58 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL21 0x5C +#define LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22 0x60 +#define LN_VREF_ADJUST_GRAY GENMASK(11, 7) +#define LN_VREF_ADJUST_GRAY_OV BIT(12) +#define LN_VREF_BIAS_SEL GENMASK(14, 13) +#define LN_VREF_BIAS_SEL_OV BIT(15) +#define LN_VREF_BOOST_EN BIT(16) +#define LN_VREF_BOOST_EN_OV BIT(17) +#define LN_VREF_EN BIT(18) +#define LN_VREF_EN_OV BIT(19) +#define LN_VREF_LPBKIN_DATA GENMASK(29, 28) +#define LN_VREF_TEST_RXLPBKDT_EN BIT(30) +#define LN_VREF_TEST_RXLPBKDT_EN_OV BIT(31) + +#define LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0 0x00 +#define LN_BYTECLK_RESET_SYNC_EN_OV BIT(2) +#define LN_BYTECLK_RESET_SYNC_EN BIT(3) +#define LN_BYTECLK_RESET_SYNC_CLR_OV BIT(4) +#define LN_BYTECLK_RESET_SYNC_CLR BIT(5) +#define LN_BYTECLK_RESET_SYNC_SEL_OV BIT(6) + +#define LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1 0x04 +#define LN_TXA_DIV2_EN_OV BIT(8) +#define LN_TXA_DIV2_EN BIT(9) +#define LN_TXA_DIV2_RESET_OV BIT(10) +#define LN_TXA_DIV2_RESET BIT(11) +#define LN_TXA_CLK_EN_OV BIT(22) +#define LN_TXA_CLK_EN BIT(23) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG0 0x08 +#define LN_TXA_CAL_CTRL_OV BIT(0) +#define LN_TXA_CAL_CTRL GENMASK(18, 1) +#define LN_TXA_CAL_CTRL_BASE_OV BIT(19) +#define LN_TXA_CAL_CTRL_BASE GENMASK(23, 20) +#define LN_TXA_HIZ_OV BIT(29) +#define LN_TXA_HIZ BIT(30) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG1 0x0C +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG2 0x10 +#define LN_TXA_MARGIN_OV BIT(0) +#define LN_TXA_MARGIN GENMASK(18, 1) +#define LN_TXA_MARGIN_2R_OV BIT(19) +#define LN_TXA_MARGIN_2R BIT(20) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG3 0x14 +#define LN_TXA_MARGIN_POST_OV BIT(0) +#define LN_TXA_MARGIN_POST GENMASK(10, 1) +#define LN_TXA_MARGIN_POST_2R_OV BIT(11) +#define LN_TXA_MARGIN_POST_2R BIT(12) +#define LN_TXA_MARGIN_POST_4R_OV BIT(13) +#define LN_TXA_MARGIN_POST_4R BIT(14) +#define LN_TXA_MARGIN_PRE_OV BIT(15) +#define LN_TXA_MARGIN_PRE GENMASK(21, 16) +#define LN_TXA_MARGIN_PRE_2R_OV BIT(22) +#define LN_TXA_MARGIN_PRE_2R BIT(23) +#define LN_TXA_MARGIN_PRE_4R_OV BIT(24) +#define LN_TXA_MARGIN_PRE_4R BIT(25) + +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG0 0x18 +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG1 0x1C +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG2 0x20 + +#define LN_AUSPMA_TX_SHM_TXA_LDOCLK 0x24 +#define LN_LDOCLK_BYPASS_SML_OV BIT(8) +#define LN_LDOCLK_BYPASS_SML BIT(9) +#define LN_LDOCLK_BYPASS_BIG_OV BIT(10) +#define LN_LDOCLK_BYPASS_BIG BIT(11) +#define LN_LDOCLK_EN_SML_OV BIT(12) +#define LN_LDOCLK_EN_SML BIT(13) +#define LN_LDOCLK_EN_BIG_OV BIT(14) +#define LN_LDOCLK_EN_BIG BIT(15) + +/* LPDPTX registers */ +#define LPDPTX_AUX_CFG_BLK_AUX_CTRL 0x0000 +#define LPDPTX_BLK_AUX_CTRL_PWRDN BIT(4) +#define LPDPTX_BLK_AUX_RXOFFSET GENMASK(25, 22) + +#define LPDPTX_AUX_CFG_BLK_AUX_LDO_CTRL 0x0008 + +#define LPDPTX_AUX_CFG_BLK_AUX_MARGIN 0x000c +#define LPDPTX_MARGIN_RCAL_RXOFFSET_EN BIT(5) +#define LPDPTX_AUX_MARGIN_RCAL_TXSWING GENMASK(10, 6) + +#define LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG0 0x0204 +#define LPDPTX_CFG_PMA_AUX_SEL_LF_DATA BIT(15) + +#define LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1 0x0208 +#define LPDPTX_CFG_PMA_PHYS_ADJ GENMASK(22, 20) +#define LPDPTX_CFG_PMA_PHYS_ADJ_OV BIT(19) + +#define LPDPTX_AUX_CONTROL 0x4000 +#define LPDPTX_AUX_PWN_DOWN 0x10 +#define LPDPTX_AUX_CLAMP_EN 0x04 +#define LPDPTX_SLEEP_B_BIG_IN 0x02 +#define LPDPTX_SLEEP_B_SML_IN 0x01 +#define LPDPTX_TXTERM_CODEMSB 0x400 +#define LPDPTX_TXTERM_CODE GENMASK(9, 5) + +/* pipehandler registers */ +#define PIPEHANDLER_OVERRIDE 0x00 +#define PIPEHANDLER_OVERRIDE_RXVALID BIT(0) +#define PIPEHANDLER_OVERRIDE_RXDETECT BIT(2) + +#define PIPEHANDLER_OVERRIDE_VALUES 0x04 +#define PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 BIT(1) +#define PIPEHANDLER_OVERRIDE_VAL_RXDETECT1 BIT(2) +#define PIPEHANDLER_OVERRIDE_VAL_PHY_STATUS BIT(4) + +#define PIPEHANDLER_MUX_CTRL 0x0c +#define PIPEHANDLED_MUX_CTRL_CLK GENMASK(5, 3) +#define PIPEHANDLED_MUX_CTRL_DATA GENMASK(2, 0) +#define PIPEHANDLED_MUX_CTRL_CLK_OFF 0 +#define PIPEHANDLED_MUX_CTRL_CLK_USB3 1 +#define PIPEHANDLED_MUX_CTRL_CLK_USB4 2 +#define PIPEHANDLED_MUX_CTRL_CLK_DUMMY 4 + +#define PIPEHANDLED_MUX_CTRL_DATA_USB3 0 +#define PIPEHANDLED_MUX_CTRL_DATA_USB4 1 +#define PIPEHANDLED_MUX_CTRL_DATA_DUMMY 2 + +#define PIPEHANDLER_LOCK_REQ 0x10 +#define PIPEHANDLER_LOCK_ACK 0x14 +#define PIPEHANDLER_LOCK_EN BIT(0) + +#define PIPEHANDLER_AON_GEN 0x1C +#define PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN BIT(4) +#define PIPEHANDLER_AON_GEN_DWC3_RESET_N BIT(0) + +#define PIPEHANDLER_NONSELECTED_OVERRIDE 0x20 +#define PIPEHANDLER_NATIVE_RESET BIT(12) +#define PIPEHANDLER_DUMMY_PHY_EN BIT(15) +#define PIPEHANDLER_NATIVE_POWER_DOWN GENMASK(3, 0) + +#define PIPEHANDLER_LOCK_ACK_TIMEOUT_US 1000 + +/* USB2 PHY regs */ +#define USB2PHY_USBCTL 0x00 +#define USB2PHY_USBCTL_RUN 2 +#define USB2PHY_USBCTL_ISOLATION 4 + +#define USB2PHY_CTL 0x04 +#define USB2PHY_CTL_RESET BIT(0) +#define USB2PHY_CTL_PORT_RESET BIT(1) +#define USB2PHY_CTL_APB_RESET_N BIT(2) +#define USB2PHY_CTL_SIDDQ BIT(3) + +#define USB2PHY_SIG 0x08 +#define USB2PHY_SIG_VBUSDET_FORCE_VAL BIT(0) +#define USB2PHY_SIG_VBUSDET_FORCE_EN BIT(1) +#define USB2PHY_SIG_VBUSVLDEXT_FORCE_VAL BIT(2) +#define USB2PHY_SIG_VBUSVLDEXT_FORCE_EN BIT(3) +#define USB2PHY_SIG_HOST (7 << 12) + +#define USB2PHY_MISCTUNE 0x1c +#define USB2PHY_MISCTUNE_APBCLK_GATE_OFF BIT(29) +#define USB2PHY_MISCTUNE_REFCLK_GATE_OFF BIT(30) + +enum atcphy_dp_link_rate { + ATCPHY_DP_LINK_RATE_RBR, + ATCPHY_DP_LINK_RATE_HBR, + ATCPHY_DP_LINK_RATE_HBR2, + ATCPHY_DP_LINK_RATE_HBR3, +}; + +enum atcphy_pipehandler_state { + ATCPHY_PIPEHANDLER_STATE_INVALID, + ATCPHY_PIPEHANDLER_STATE_DUMMY, + ATCPHY_PIPEHANDLER_STATE_USB3, + ATCPHY_PIPEHANDLER_STATE_USB4, +}; + +enum atcphy_mode { + APPLE_ATCPHY_MODE_OFF, + APPLE_ATCPHY_MODE_USB2, + APPLE_ATCPHY_MODE_USB3, + APPLE_ATCPHY_MODE_USB3_DP, + APPLE_ATCPHY_MODE_TBT, + APPLE_ATCPHY_MODE_USB4, + APPLE_ATCPHY_MODE_DP, +}; + +enum atcphy_lane { + APPLE_ATCPHY_LANE_0, + APPLE_ATCPHY_LANE_1, +}; + +struct atcphy_dp_link_rate_configuration { + u16 freqinit_count_target; + u16 fbdivn_frac_den; + u16 fbdivn_frac_num; + u16 pclk_div_sel; + u8 lfclk_ctrl; + u8 vclk_op_divn; + bool plla_clkout_vreg_bypass; + bool txa_ldoclk_bypass; + bool txa_div2_en; +}; + +struct atcphy_mode_configuration { + u32 crossbar; + u32 crossbar_dp_single_pma; + bool crossbar_dp_both_pma; + u32 lane_mode[2]; + bool dp_lane[2]; + bool set_swap; +}; + +struct apple_atcphy { + struct device_node *np; + struct device *dev; + + /* tunables provided by firmware through the device tree */ + struct { + struct apple_tunable *fuses; + struct apple_tunable *axi2af; + struct apple_tunable *common; + struct apple_tunable *lane_usb3[2]; + struct apple_tunable *lane_displayport[2]; + struct apple_tunable *lane_usb4[2]; + } tunables; + + enum atcphy_mode mode; + enum atcphy_mode target_mode; + enum atcphy_pipehandler_state pipehandler_state; + bool swap_lanes; + int dp_link_rate; + bool pipehandler_up; + bool dwc3_running; + + struct { + void __iomem *core; + void __iomem *axi2af; + void __iomem *usb2phy; + void __iomem *pipehandler; + void __iomem *lpdptx; + } regs; + + struct phy *phy_usb2; + struct phy *phy_usb3; + struct phy *phy_dp; + struct phy_provider *phy_provider; + struct reset_controller_dev rcdev; + struct typec_switch *sw; + struct typec_mux *mux; + + struct mutex lock; +}; + +static const struct { + const struct atcphy_mode_configuration normal; + const struct atcphy_mode_configuration swapped; + bool enable_dp_aux; + enum atcphy_pipehandler_state pipehandler_state; +} atcphy_modes[] =3D { + [APPLE_ATCPHY_MODE_OFF] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* doesn't matter since the SS lanes are off */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB2] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* doesn't matter since the SS lanes are off */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB3] =3D { + /* + * Setting up the lanes as DP/USB3 is intentional here, USB3/USB3 does n= ot work + * and isn't required since this PHY does not support 20GBps mode anyway. + * The only difference to APPLE_ATCPHY_MODE_USB3_DP is that DP Aux is no= t enabled. + */ + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB3, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {false, true}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_USB3}, + .dp_lane =3D {true, false}, + .set_swap =3D true, + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB3, + }, + [APPLE_ATCPHY_MODE_USB3_DP] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB3, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {false, true}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_USB3}, + .dp_lane =3D {true, false}, + .set_swap =3D true, + }, + .enable_dp_aux =3D true, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB3, + }, + [APPLE_ATCPHY_MODE_TBT] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB4] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB4, + }, + [APPLE_ATCPHY_MODE_DP] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK100, + .crossbar_dp_both_pma =3D true, + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {true, true}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, /* intentionally false */ + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {true, true}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D true, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, +}; + +static const struct atcphy_dp_link_rate_configuration dp_lr_config[] =3D { + [ATCPHY_DP_LINK_RATE_RBR] =3D { + .freqinit_count_target =3D 0x21c, + .fbdivn_frac_den =3D 0x0, + .fbdivn_frac_num =3D 0x0, + .pclk_div_sel =3D 0x13, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x2, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D true, + }, + [ATCPHY_DP_LINK_RATE_HBR] =3D { + .freqinit_count_target =3D 0x1c2, + .fbdivn_frac_den =3D 0x3ffe, + .fbdivn_frac_num =3D 0x1fff, + .pclk_div_sel =3D 0x9, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x2, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D false, + }, + [ATCPHY_DP_LINK_RATE_HBR2] =3D { + .freqinit_count_target =3D 0x1c2, + .fbdivn_frac_den =3D 0x3ffe, + .fbdivn_frac_num =3D 0x1fff, + .pclk_div_sel =3D 0x4, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x0, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D false, + }, + [ATCPHY_DP_LINK_RATE_HBR3] =3D { + .freqinit_count_target =3D 0x2a3, + .fbdivn_frac_den =3D 0x3ffc, + .fbdivn_frac_num =3D 0x2ffd, + .pclk_div_sel =3D 0x4, + .lfclk_ctrl =3D 0x6, + .vclk_op_divn =3D 0x0, + .plla_clkout_vreg_bypass =3D false, + .txa_ldoclk_bypass =3D false, + .txa_div2_en =3D false, + }, +}; + +static inline void mask32(void __iomem *reg, u32 mask, u32 set) +{ + u32 value =3D readl(reg); + + value &=3D ~mask; + value |=3D set; + writel(value, reg); +} + +static inline void core_mask32(struct apple_atcphy *atcphy, u32 reg, u32 m= ask, u32 set) +{ + mask32(atcphy->regs.core + reg, mask, set); +} + +static inline void set32(void __iomem *reg, u32 set) +{ + mask32(reg, 0, set); +} + +static inline void core_set32(struct apple_atcphy *atcphy, u32 reg, u32 se= t) +{ + core_mask32(atcphy, reg, 0, set); +} + +static inline void clear32(void __iomem *reg, u32 clear) +{ + mask32(reg, clear, 0); +} + +static inline void core_clear32(struct apple_atcphy *atcphy, u32 reg, u32 = clear) +{ + core_mask32(atcphy, reg, clear, 0); +} + +static void atcphy_apply_tunables(struct apple_atcphy *atcphy, enum atcphy= _mode mode) +{ + const int lane0 =3D atcphy->swap_lanes ? 1 : 0; + const int lane1 =3D atcphy->swap_lanes ? 0 : 1; + + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.fuses); + apple_tunable_apply(atcphy->regs.axi2af, atcphy->tunables.axi2af); + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.common); + + switch (mode) { + case APPLE_ATCPHY_MODE_USB3: + case APPLE_ATCPHY_MODE_USB3_DP: + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_usb3[lane0]= ); + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_displayport= [lane1]); + break; + + case APPLE_ATCPHY_MODE_DP: + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_displayport= [lane0]); + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_displayport= [lane1]); + break; + + case APPLE_ATCPHY_MODE_TBT: + case APPLE_ATCPHY_MODE_USB4: + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_usb4[lane0]= ); + apple_tunable_apply(atcphy->regs.core, atcphy->tunables.lane_usb4[lane1]= ); + break; + + case APPLE_ATCPHY_MODE_OFF: + case APPLE_ATCPHY_MODE_USB2: + break; + } +} + +static int atcphy_pipehandler_lock(struct apple_atcphy *atcphy) +{ + int ret; + u32 reg; + + if (readl(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ) & PIPEHANDLER_= LOCK_EN) { + dev_warn(atcphy->dev, "Pipehandler already locked\n"); + return 0; + } + + set32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, PIPEHANDLER_LOCK_E= N); + + ret =3D readl_poll_timeout(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_AC= K, reg, + reg & PIPEHANDLER_LOCK_EN, 10, PIPEHANDLER_LOCK_ACK_TIMEOUT_US); + if (ret) { + clear32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, 1); + dev_warn(atcphy->dev, "Pipehandler lock not acked.\n"); + } + + return ret; +} + +static int atcphy_pipehandler_unlock(struct apple_atcphy *atcphy) +{ + int ret; + u32 reg; + + clear32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, PIPEHANDLER_LOCK= _EN); + ret =3D readl_poll_timeout(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_AC= K, reg, + !(reg & PIPEHANDLER_LOCK_EN), 10, PIPEHANDLER_LOCK_ACK_TIMEOUT_US); + if (ret) + dev_warn(atcphy->dev, "Pipehandler lock release not acked.\n"); + + return ret; +} + +static int atcphy_pipehandler_check(struct apple_atcphy *atcphy) +{ + int ret; + + lockdep_assert_held(&atcphy->lock); + + if (readl(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_ACK) & PIPEHANDLER_= LOCK_EN) { + dev_warn(atcphy->dev, "Pipehandler already locked\n"); + + ret =3D atcphy_pipehandler_unlock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to unlock pipehandler\n"); + return ret; + } + } + + return 0; +} + +static int atcphy_configure_pipehandler_usb3(struct apple_atcphy *atcphy, = bool host) +{ + int ret; + u32 reg; + + ret =3D atcphy_pipehandler_check(atcphy); + if (ret) + return ret; + + if (host && atcphy->dwc3_running) { + /* Force disable link detection */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE_VALUES, + PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 | PIPEHANDLER_OVERRIDE_VAL_RXDETECT1= ); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXVALID); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXDETECT); + + ret =3D atcphy_pipehandler_lock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to lock pipehandler"); + return ret; + } + + /* BIST dance */ + core_set32(atcphy, ACIOPHY_TOP_BIST_PHY_CFG0, + ACIOPHY_TOP_BIST_PHY_CFG0_LN0_RESET_N); + core_set32(atcphy, ACIOPHY_TOP_BIST_OV_CFG, ACIOPHY_TOP_BIST_OV_CFG_LN0_= RESET_N_OV); + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + !(reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK23), 10, 10000); + if (ret) + dev_warn(atcphy->dev, + "Timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK23\n"); + + core_set32(atcphy, ACIOPHY_TOP_BIST_READ_CTRL, + ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE); + core_clear32(atcphy, ACIOPHY_TOP_BIST_READ_CTRL, + ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE); + + core_mask32(atcphy, ACIOPHY_TOP_BIST_PHY_CFG1, + ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN, + FIELD_PREP(ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN, 3)); + + core_set32(atcphy, ACIOPHY_TOP_BIST_OV_CFG, + ACIOPHY_TOP_BIST_OV_CFG_LN0_PWR_DOWN_OV); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN); + writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_CIOPHY_CFG1); + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + (reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK0), 10, 10000); + if (ret) + dev_warn(atcphy->dev, + "timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK0\n"); + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + !(reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK23), 10, 10000); + if (ret) + dev_warn(atcphy->dev, + "timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK23\n"); + + /* Clear reset for non-selected USB3 PHY (?) */ + mask32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_POWER_DOWN, FIELD_PREP(PIPEHANDLER_NATIVE_POWE= R_DOWN, 3)); + clear32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_RESET); + + /* More BIST stuff (?) */ + writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_OV_CFG); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN); + } + + /* Configure PIPE mux to USB3 PHY */ + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_OFF)= ); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, PIPEHANDLED_MUX_CTRL_DATA_US= B3)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_USB3= )); + udelay(10); + + /* Remove link detection override */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, PIPEHANDLER_OVER= RIDE_RXVALID); + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, PIPEHANDLER_OVER= RIDE_RXDETECT); + + if (host && atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_unlock(atcphy); + if (ret) + dev_warn(atcphy->dev, "Failed to unlock pipehandler"); + } + + return 0; +} + +static int atcphy_configure_pipehandler_dummy(struct apple_atcphy *atcphy) +{ + int ret; + + ret =3D atcphy_pipehandler_check(atcphy); + if (ret) + return ret; + + /* Force disable link detection */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE_VALUES, + PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 | PIPEHANDLER_OVERRIDE_VAL_RXDETECT1); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, PIPEHANDLER_OVERRI= DE_RXVALID); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, PIPEHANDLER_OVERRI= DE_RXDETECT); + + if (atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_lock(atcphy); + if (ret) + dev_warn(atcphy->dev, "Failed to lock pipehandler"); + } + + /* Switch to dummy PHY */ + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_OFF)= ); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, PIPEHANDLED_MUX_CTRL_DATA_DU= MMY)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_DUMM= Y)); + udelay(10); + + if (atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_unlock(atcphy); + if (ret) + dev_warn(atcphy->dev, "Failed to unlock pipehandler"); + } + + mask32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_POWER_DOWN, FIELD_PREP(PIPEHANDLER_NATIVE_POWER= _DOWN, 2)); + set32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_RESET); + + return 0; +} + +static int atcphy_configure_pipehandler(struct apple_atcphy *atcphy, bool = host) +{ + int ret; + + lockdep_assert_held(&atcphy->lock); + + switch (atcphy_modes[atcphy->target_mode].pipehandler_state) { + case ATCPHY_PIPEHANDLER_STATE_INVALID: + /* Can only be reached if this driver is buggy; warn and fall back to US= B2 */ + WARN_ON_ONCE(1); + fallthrough; + case ATCPHY_PIPEHANDLER_STATE_DUMMY: + ret =3D atcphy_configure_pipehandler_dummy(atcphy); + break; + case ATCPHY_PIPEHANDLER_STATE_USB3: + ret =3D atcphy_configure_pipehandler_usb3(atcphy, host); + atcphy->pipehandler_up =3D true; + break; + case ATCPHY_PIPEHANDLER_STATE_USB4: + dev_warn(atcphy->dev, + "ATCPHY_PIPEHANDLER_STATE_USB4 not implemented; falling back to USB2\n= "); + ret =3D atcphy_configure_pipehandler_dummy(atcphy); + atcphy->pipehandler_up =3D true; + break; + default: + ret =3D -EINVAL; + } + + return ret; +} + +static void atcphy_setup_pipehandler(struct apple_atcphy *atcphy) +{ + lockdep_assert_held(&atcphy->lock); + WARN_ON(atcphy->pipehandler_state !=3D ATCPHY_PIPEHANDLER_STATE_INVALID); + + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_OFF)= ); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, PIPEHANDLED_MUX_CTRL_DATA_DU= MMY)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, PIPEHANDLED_MUX_C= TRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, PIPEHANDLED_MUX_CTRL_CLK_DUMM= Y)); + udelay(10); + + atcphy->pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY; +} + +static void atcphy_configure_lanes(struct apple_atcphy *atcphy, enum atcph= y_mode mode) +{ + const struct atcphy_mode_configuration *mode_cfg; + + if (atcphy->swap_lanes) + mode_cfg =3D &atcphy_modes[mode].swapped; + else + mode_cfg =3D &atcphy_modes[mode].normal; + + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_RX0, + FIELD_PREP(ACIOPHY_LANE_MODE_RX0, mode_cfg->lane_mode[0])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_TX0, + FIELD_PREP(ACIOPHY_LANE_MODE_TX0, mode_cfg->lane_mode[0])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_RX1, + FIELD_PREP(ACIOPHY_LANE_MODE_RX1, mode_cfg->lane_mode[1])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_TX1, + FIELD_PREP(ACIOPHY_LANE_MODE_TX1, mode_cfg->lane_mode[1])); + core_mask32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_PROTOCOL, + FIELD_PREP(ACIOPHY_CROSSBAR_PROTOCOL, mode_cfg->crossbar)); + + if (mode_cfg->set_swap) + core_set32(atcphy, ATCPHY_MISC, ATCPHY_MISC_LANE_SWAP); + else + core_clear32(atcphy, ATCPHY_MISC, ATCPHY_MISC_LANE_SWAP); + + core_mask32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_DP_SINGLE_PMA, + FIELD_PREP(ACIOPHY_CROSSBAR_DP_SINGLE_PMA, mode_cfg->crossbar_dp_sin= gle_pma)); + if (mode_cfg->crossbar_dp_both_pma) + core_set32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_DP_BOTH_PMA); + else + core_clear32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_DP_BOTH_PMA); + + if (mode_cfg->dp_lane[0]) { + core_set32(atcphy, LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + core_clear32(atcphy, LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ); + } else { + core_clear32(atcphy, LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + } + + if (mode_cfg->dp_lane[1]) { + core_set32(atcphy, LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + core_clear32(atcphy, LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ); + } else { + core_clear32(atcphy, LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + } +} + +static void atcphy_enable_dp_aux(struct apple_atcphy *atcphy) +{ + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTXPHY_PMA_LANE_= RESET_N); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTXPHY_PMA_LANE_= RESET_N_OV); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPRX_PCLK_SELECT, + FIELD_PREP(DPRX_PCLK_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPRX_PCLK_ENABLE); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK1_SELEC= T, + FIELD_PREP(DPTX_PCLK1_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK1_ENABLE= ); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK2_SELEC= T, + FIELD_PREP(DPTX_PCLK2_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK2_ENABLE= ); + + core_set32(atcphy, ACIOPHY_PLL_COMMON_CTRL, + ACIOPHY_PLL_WAIT_FOR_CMN_READY_BEFORE_RESET_EXIT); + + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_SML_IN); + udelay(10); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_BIG_IN); + udelay(10); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_PWN_DOWN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_TXTERM_CODEMSB); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_TXTERM_CODE, + FIELD_PREP(LPDPTX_TXTERM_CODE, 0x16)); + + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_LDO_CTRL, 0x1c00); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1, LPDPTX= _CFG_PMA_PHYS_ADJ, + FIELD_PREP(LPDPTX_CFG_PMA_PHYS_ADJ, 5)); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1, + LPDPTX_CFG_PMA_PHYS_ADJ_OV); + + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_MARGIN, + LPDPTX_MARGIN_RCAL_RXOFFSET_EN); + + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, LPDPTX_BLK_AUX= _CTRL_PWRDN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG0, + LPDPTX_CFG_PMA_AUX_SEL_LF_DATA); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, LPDPTX_BLK_AUX_= RXOFFSET, + FIELD_PREP(LPDPTX_BLK_AUX_RXOFFSET, 3)); + + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_MARGIN, LPDPTX_AUX_MA= RGIN_RCAL_TXSWING, + FIELD_PREP(LPDPTX_AUX_MARGIN_RCAL_TXSWING, 12)); + + atcphy->dp_link_rate =3D -1; +} + +static void atcphy_disable_dp_aux(struct apple_atcphy *atcphy) +{ + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_PWN_DOWN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, LPDPTX_BLK_AUX_C= TRL_PWRDN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_SML_IN); + udelay(10); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_BIG_IN); + udelay(10); + + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTXPHY_PMA_LAN= E_RESET_N); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPRX_PCLK_ENABL= E); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK1_ENAB= LE); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DPTX_PCLK2_ENAB= LE); +} + +static int atcphy_dp_configure_lane(struct apple_atcphy *atcphy, enum atcp= hy_lane lane, + const struct atcphy_dp_link_rate_configuration *cfg) +{ + void __iomem *tx_shm, *rx_shm, *rx_top; + unsigned int tx_cal_code; + + lockdep_assert_held(&atcphy->lock); + + switch (lane) { + case APPLE_ATCPHY_LANE_0: + tx_shm =3D atcphy->regs.core + LN0_AUSPMA_TX_SHM; + rx_shm =3D atcphy->regs.core + LN0_AUSPMA_RX_SHM; + rx_top =3D atcphy->regs.core + LN0_AUSPMA_RX_TOP; + break; + case APPLE_ATCPHY_LANE_1: + tx_shm =3D atcphy->regs.core + LN1_AUSPMA_TX_SHM; + rx_shm =3D atcphy->regs.core + LN1_AUSPMA_RX_SHM; + rx_top =3D atcphy->regs.core + LN1_AUSPMA_RX_TOP; + break; + default: + return -EINVAL; + } + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_SML); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_SML_OV); + udelay(10); + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_BIG); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_BIG_OV); + udelay(10); + + if (cfg->txa_ldoclk_bypass) { + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_SML); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_SML_OV); + udelay(10); + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_BIG); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_BIG_OV); + udelay(10); + } else { + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_SML); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_SML_OV); + udelay(10); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_BIG); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_BYPASS_BIG_OV); + udelay(10); + } + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, LN_BYTECLK_RESET_SYNC_= SEL_OV); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, LN_BYTECLK_RESET_SYNC_= EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, LN_BYTECLK_RESET_SYNC_= EN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, LN_BYTECLK_RESET_SYN= C_CLR); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, LN_BYTECLK_RESET_SYNC_= CLR_OV); + + if (cfg->txa_div2_en) + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_EN); + else + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_EN_OV); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_CLK_EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_CLK_EN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_RESET); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_RESET_OV); + + mask32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_BASE, + FIELD_PREP(LN_TXA_CAL_CTRL_BASE, 0xf)); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_BASE_OV); + + tx_cal_code =3D FIELD_GET(AUS_UNK_A20_TX_CAL_CODE, readl(atcphy->regs.cor= e + AUS_UNK_A20)); + mask32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL, + FIELD_PREP(LN_TXA_CAL_CTRL, (1 << tx_cal_code) - 1)); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_2R_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_HIZ); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_HIZ_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, LN_RX_DIV20_RESET_N); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, LN_RX_DIV20_RESET_N_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, LN_RX_DIV20_RESET_N); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_BYTECLK_RESET_SY= NC_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_BYTECLK_RESET_SY= NC_EN_OV); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_TX_CAL_CODE, + FIELD_PREP(LN_TX_CAL_CODE, tx_cal_code)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_TX_CAL_CODE_OV); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DLY_CTRL_T= APGEN, + FIELD_PREP(LN_TX_CLK_DLY_CTRL_TAPGEN, 3)); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10, LN_DTVREG_ADJUST); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_DTVREG_ADJUST_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_TEST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_TEST_EN_OV); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_TEST_RXLPBKDT= _EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_TEST_RXLPBKDT= _EN_OV); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_LPBKIN_DATA, + FIELD_PREP(LN_VREF_LPBKIN_DATA, 3)); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BIAS_SEL, + FIELD_PREP(LN_VREF_BIAS_SEL, 2)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BIAS_SEL_OV); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_ADJUST_GRAY, + FIELD_PREP(LN_VREF_ADJUST_GRAY, 0x18)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_ADJUST_GRAY_O= V); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_EN_OV); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN_OV); + udelay(10); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN_OV); + udelay(10); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PRE_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PRE_EN_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PST1_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PST1_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_PBIAS_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_PBIAS_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_PULLUP_L= EAK_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_PULLUP_LEA= K_EN_OV); + + set32(rx_top + LN_AUSPMA_RX_TOP_TJ_CFG_RX_TXMODE, LN_RX_TXMODE); + + if (cfg->txa_div2_en) + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DIV2_EN); + else + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DIV2_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DIV2_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DIV2_RST); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_CLK_DIV2_RST_OV= ); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_HRCLK_SEL); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_HRCLK_SEL_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_LSB_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1_LSB_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_LSB_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_LSB_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE_LSB_OV= ); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_LSB_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_LSB_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_CODE_OV); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_SML_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_SML_EN_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_BIG_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_BIG_EN_OV); + udelay(10); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10, LN_DTVREG_ADJUST, + FIELD_PREP(LN_DTVREG_ADJUST, 0xa)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_DTVREG_ADJUST_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_EN_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0, LN_TX_CLK_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0, LN_TX_CLK_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_BYTECLK_RESET_= SYNC_CLR); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_BYTECLK_RESET_SY= NC_CLR_OV); + + return 0; +} + +static int atcphy_auspll_apb_command(struct apple_atcphy *atcphy, u32 comm= and) +{ + int ret; + u32 reg; + + reg =3D readl(atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE); + reg &=3D ~AUSPLL_APB_CMD_OVERRIDE_CMD; + reg |=3D FIELD_PREP(AUSPLL_APB_CMD_OVERRIDE_CMD, command); + reg |=3D AUSPLL_APB_CMD_OVERRIDE_REQ; + reg |=3D AUSPLL_APB_CMD_OVERRIDE_UNK28; + writel(reg, atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE); + + ret =3D readl_poll_timeout(atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE, r= eg, + (reg & AUSPLL_APB_CMD_OVERRIDE_ACK), 10, 10000); + if (ret) + dev_warn(atcphy->dev, "AUSPLL APB command was not acked\n"); + + core_clear32(atcphy, AUSPLL_APB_CMD_OVERRIDE, AUSPLL_APB_CMD_OVERRIDE_REQ= ); + + return 0; +} + +static int atcphy_dp_configure(struct apple_atcphy *atcphy, enum atcphy_dp= _link_rate lr) +{ + const struct atcphy_dp_link_rate_configuration *cfg =3D &dp_lr_config[lr]; + const struct atcphy_mode_configuration *mode_cfg; + int ret; + u32 reg; + + if (atcphy->dp_link_rate =3D=3D lr) + return 0; + + if (atcphy->swap_lanes) + mode_cfg =3D &atcphy_modes[atcphy->mode].swapped; + else + mode_cfg =3D &atcphy_modes[atcphy->mode].normal; + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_CMN_SHM_STS_REG0, = reg, + (reg & ACIOPHY_CMN_SHM_STS_REG0_CMD_READY), 10, 10000); + if (ret) { + dev_err(atcphy->dev, "ACIOPHY_CMN_SHM_STS_REG0_CMD_READY not set.\n"); + return ret; + } + + core_clear32(atcphy, AUSPLL_FREQ_CFG, AUSPLL_FREQ_REFCLK); + + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_FREQ_COUNT_TARGET, + FIELD_PREP(AUSPLL_FD_FREQ_COUNT_TARGET, cfg->freqinit_count_target)); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_FBDIVN_HALF); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_REV_DIVN); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KI_MAN, FIELD_PREP(AUSP= LL_FD_KI_MAN, 8)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KI_EXP, FIELD_PREP(AUSP= LL_FD_KI_EXP, 3)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KP_MAN, FIELD_PREP(AUSP= LL_FD_KP_MAN, 8)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KP_EXP, FIELD_PREP(AUSP= LL_FD_KP_EXP, 7)); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KPKI_SCALE_HBW); + + core_mask32(atcphy, AUSPLL_FREQ_DESC_B, AUSPLL_FD_FBDIVN_FRAC_DEN, + FIELD_PREP(AUSPLL_FD_FBDIVN_FRAC_DEN, cfg->fbdivn_frac_den)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_B, AUSPLL_FD_FBDIVN_FRAC_NUM, + FIELD_PREP(AUSPLL_FD_FBDIVN_FRAC_NUM, cfg->fbdivn_frac_num)); + + core_clear32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_SDM_SSC_STEP); + core_clear32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_SDM_SSC_EN); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_PCLK_DIV_SEL, + FIELD_PREP(AUSPLL_FD_PCLK_DIV_SEL, cfg->pclk_div_sel)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_LFSDM_DIV, + FIELD_PREP(AUSPLL_FD_LFSDM_DIV, 1)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_LFCLK_CTRL, + FIELD_PREP(AUSPLL_FD_LFCLK_CTRL, cfg->lfclk_ctrl)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_VCLK_OP_DIVN, + FIELD_PREP(AUSPLL_FD_VCLK_OP_DIVN, cfg->vclk_op_divn)); + core_set32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_VCLK_PRE_DIVN); + + core_mask32(atcphy, AUSPLL_CLKOUT_DIV, AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI, + FIELD_PREP(AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI, 7)); + + if (cfg->plla_clkout_vreg_bypass) + core_set32(atcphy, AUSPLL_CLKOUT_DTC_VREG, AUSPLL_DTC_VREG_BYPASS); + else + core_clear32(atcphy, AUSPLL_CLKOUT_DTC_VREG, AUSPLL_DTC_VREG_BYPASS); + + core_set32(atcphy, AUSPLL_BGR, AUSPLL_BGR_CTRL_AVAIL); + + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, AUSPLL_CLKOUT_MASTER_PCLK_DRVR_E= N); + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, AUSPLL_CLKOUT_MASTER_PCLK2_DRVR_= EN); + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, AUSPLL_CLKOUT_MASTER_REFBUFCLK_D= RVR_EN); + + ret =3D atcphy_auspll_apb_command(atcphy, 0); + if (ret) + return ret; + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_DP_PCLK_STAT, reg, + (reg & ACIOPHY_AUSPLL_LOCK), 10, 10000); + if (ret) { + dev_err(atcphy->dev, "ACIOPHY_DP_PCLK did not lock.\n"); + return ret; + } + + ret =3D atcphy_auspll_apb_command(atcphy, 0x2800); + if (ret) + return ret; + + if (mode_cfg->dp_lane[0]) { + ret =3D atcphy_dp_configure_lane(atcphy, APPLE_ATCPHY_LANE_0, cfg); + if (ret) + return ret; + } + + if (mode_cfg->dp_lane[1]) { + ret =3D atcphy_dp_configure_lane(atcphy, APPLE_ATCPHY_LANE_1, cfg); + if (ret) + return ret; + } + + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DP_PMA_BYTECLK_= RESET); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, DP_MAC_DIV20_CL= K_SEL); + + atcphy->dp_link_rate =3D lr; + return 0; +} + +static void atcphy_usb2_power_off(struct apple_atcphy *atcphy) +{ + /* Disable the PHY, this clears USB2PHY_USBCTL_RUN */ + writel(USB2PHY_USBCTL_ISOLATION, atcphy->regs.usb2phy + USB2PHY_USBCTL); + udelay(10); + + /* Switch the PHY to low power mode */ + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_SIDDQ); + udelay(10); + + /* Enable all resets */ + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_PORT_RESET); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_RESET); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_APB_RESET_N); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, USB2PHY_MISCTUNE_APBCLK_GA= TE_OFF); + set32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, USB2PHY_MISCTUNE_REFCLK_GA= TE_OFF); +} + +static int atcphy_power_off(struct apple_atcphy *atcphy) +{ + u32 reg; + int ret; + + atcphy_disable_dp_aux(atcphy); + + /* Enable all reset lines */ + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_PHY_RESET_N); + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_CLAMP_EN); + core_clear32(atcphy, ATCPHY_MISC, ATCPHY_MISC_RESET_N | ATCPHY_MISC_LANE_= SWAP); + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_APB_RESET_N); + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_BIG); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + !(reg & ATCPHY_POWER_SLEEP_BIG), 10, 1000); + if (ret) { + dev_err(atcphy->dev, "Failed to sleep atcphy \"big\"\n"); + return ret; + } + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_SMALL); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + !(reg & ATCPHY_POWER_SLEEP_SMALL), 10, 1000); + if (ret) { + dev_err(atcphy->dev, "Failed to sleep atcphy \"small\"\n"); + return ret; + } + + return 0; +} + +static void atcphy_usb2_power_on(struct apple_atcphy *atcphy) +{ + set32(atcphy->regs.usb2phy + USB2PHY_SIG, + USB2PHY_SIG_VBUSDET_FORCE_VAL | USB2PHY_SIG_VBUSDET_FORCE_EN | + USB2PHY_SIG_VBUSVLDEXT_FORCE_VAL | USB2PHY_SIG_VBUSVLDEXT_FORCE_EN= ); + udelay(10); + + /* Take the PHY out of its low power state */ + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_SIDDQ); + udelay(10); + + /* Release reset */ + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_RESET); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_PORT_RESET); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_APB_RESET_N); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, USB2PHY_MISCTUNE_APBCLK_= GATE_OFF); + clear32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, USB2PHY_MISCTUNE_REFCLK_= GATE_OFF); + + /* Enable the PHY */ + writel(USB2PHY_USBCTL_RUN, atcphy->regs.usb2phy + USB2PHY_USBCTL); +} + +static int atcphy_power_on(struct apple_atcphy *atcphy) +{ + u32 reg; + int ret; + + atcphy_usb2_power_on(atcphy); + + core_set32(atcphy, ATCPHY_MISC, ATCPHY_MISC_RESET_N); + + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_SMALL); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + reg & ATCPHY_POWER_SLEEP_SMALL, 100, 100000); + if (ret) { + dev_err(atcphy->dev, "failed to wakeup atcphy \"small\"\n"); + return ret; + } + + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_BIG); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + reg & ATCPHY_POWER_SLEEP_BIG, 100, 100000); + if (ret) { + dev_err(atcphy->dev, "failed to wakeup atcphy \"big\"\n"); + return ret; + } + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_CLAMP_EN); + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_APB_RESET_N); + + return 0; +} + +static int atcphy_configure(struct apple_atcphy *atcphy, enum atcphy_mode = mode) +{ + int ret =3D 0; + + lockdep_assert_held(&atcphy->lock); + + if (mode =3D=3D APPLE_ATCPHY_MODE_OFF) { + ret =3D atcphy_power_off(atcphy); + atcphy->mode =3D mode; + return ret; + } + + ret =3D atcphy_power_on(atcphy); + if (ret) + return ret; + + atcphy_apply_tunables(atcphy, mode); + + core_set32(atcphy, AUSPLL_FSM_CTRL, 0x1fe000); + core_set32(atcphy, AUSPLL_APB_CMD_OVERRIDE, AUSPLL_APB_CMD_OVERRIDE_UNK28= ); + + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV); + udelay(10); + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV); + udelay(10); + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV); + udelay(10); + + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_SMAL= L_OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_SMALL_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_BIG_= OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_BIG_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_CLAM= P_OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV, 3)); + udelay(10); + + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_BIG_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_BIG_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_SMALL_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_SMALL_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_CLAMP_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_CLAMP_OV, 3)); + udelay(10); + + /* Setup AUX channel if DP altmode is requested */ + if (atcphy_modes[mode].enable_dp_aux) + atcphy_enable_dp_aux(atcphy); + + /* Enable clocks and configure lanes */ + core_set32(atcphy, CIO3PLL_CLK_CTRL, CIO3PLL_CLK_PCLK_EN); + core_set32(atcphy, CIO3PLL_CLK_CTRL, CIO3PLL_CLK_REFCLK_EN); + atcphy_configure_lanes(atcphy, mode); + + /* Take the USB3 PHY out of reset */ + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_PHY_RESET_N); + + atcphy->mode =3D mode; + + return 0; +} + +static int atcphy_usb2_set_mode(struct phy *phy, enum phy_mode mode, int s= ubmode) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + + guard(mutex)(&atcphy->lock); + + switch (mode) { + case PHY_MODE_USB_HOST: + set32(atcphy->regs.usb2phy + USB2PHY_SIG, USB2PHY_SIG_HOST); + break; + case PHY_MODE_USB_DEVICE: + clear32(atcphy->regs.usb2phy + USB2PHY_SIG, USB2PHY_SIG_HOST); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct phy_ops apple_atc_usb2_phy_ops =3D { + .owner =3D THIS_MODULE, + .set_mode =3D atcphy_usb2_set_mode, +}; + +static int atcphy_usb3_power_off(struct phy *phy) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + int ret; + + guard(mutex)(&atcphy->lock); + + ret =3D atcphy_configure_pipehandler_dummy(atcphy); + if (ret) + dev_warn(atcphy->dev, "Failed to switch pipe to dummy: %d", ret); + + atcphy->pipehandler_up =3D false; + + if (atcphy->target_mode !=3D atcphy->mode) + atcphy_configure(atcphy, atcphy->target_mode); + + return 0; +} + +static int atcphy_usb3_set_mode(struct phy *phy, enum phy_mode mode, int s= ubmode) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + + guard(mutex)(&atcphy->lock); + + if (atcphy->pipehandler_up) + return 0; + + switch (mode) { + case PHY_MODE_USB_HOST: + return atcphy_configure_pipehandler(atcphy, true); + case PHY_MODE_USB_DEVICE: + return atcphy_configure_pipehandler(atcphy, false); + default: + return -EINVAL; + } +} + +static const struct phy_ops apple_atc_usb3_phy_ops =3D { + .owner =3D THIS_MODULE, + .power_off =3D atcphy_usb3_power_off, + .set_mode =3D atcphy_usb3_set_mode, +}; + +static int atcphy_dpphy_set_mode(struct phy *phy, enum phy_mode mode, int = submode) +{ + /* Nothing to do here since the setup already happened in mux_set */ + if (mode =3D=3D PHY_MODE_DP && submode =3D=3D 0) + return 0; + return -EINVAL; +} + +static int atcphy_dpphy_validate(struct phy *phy, enum phy_mode mode, int = submode, + union phy_configure_opts *opts_) +{ + struct phy_configure_opts_dp *opts =3D &opts_->dp; + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + + if (mode !=3D PHY_MODE_DP) + return -EINVAL; + if (submode !=3D 0) + return -EINVAL; + + switch (atcphy->mode) { + case APPLE_ATCPHY_MODE_USB3_DP: + opts->lanes =3D 2; + break; + case APPLE_ATCPHY_MODE_DP: + opts->lanes =3D 4; + break; + default: + opts->lanes =3D 0; + } + + return 0; +} + +static int atcphy_dpphy_configure(struct phy *phy, union phy_configure_opt= s *opts_) +{ + struct phy_configure_opts_dp *opts =3D &opts_->dp; + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + enum atcphy_dp_link_rate link_rate; + + if (opts->set_voltages) + return -EINVAL; + if (opts->set_lanes) + return -EINVAL; + + if (opts->set_rate) { + guard(mutex)(&atcphy->lock); + + switch (opts->link_rate) { + case 1620: + link_rate =3D ATCPHY_DP_LINK_RATE_RBR; + break; + case 2700: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR; + break; + case 5400: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR2; + break; + case 8100: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR3; + break; + case 0: + return 0; + default: + dev_err(atcphy->dev, "Unsupported link rate: %d\n", opts->link_rate); + return -EINVAL; + } + + return atcphy_dp_configure(atcphy, link_rate); + } + + return 0; +} + +static const struct phy_ops apple_atc_dp_phy_ops =3D { + .owner =3D THIS_MODULE, + .configure =3D atcphy_dpphy_configure, + .validate =3D atcphy_dpphy_validate, + .set_mode =3D atcphy_dpphy_set_mode, +}; + +static struct phy *atcphy_xlate(struct device *dev, const struct of_phandl= e_args *args) +{ + struct apple_atcphy *atcphy =3D dev_get_drvdata(dev); + + switch (args->args[0]) { + case PHY_TYPE_USB2: + return atcphy->phy_usb2; + case PHY_TYPE_USB3: + return atcphy->phy_usb3; + case PHY_TYPE_DP: + return atcphy->phy_dp; + } + return ERR_PTR(-ENODEV); +} + +static int atcphy_probe_phy(struct apple_atcphy *atcphy) +{ + struct { + struct phy **phy; + const struct phy_ops *ops; + } phys[] =3D { + { &atcphy->phy_usb2, &apple_atc_usb2_phy_ops }, + { &atcphy->phy_usb3, &apple_atc_usb3_phy_ops }, + { &atcphy->phy_dp, &apple_atc_dp_phy_ops }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(phys); i++) { + *phys[i].phy =3D devm_phy_create(atcphy->dev, NULL, phys[i].ops); + if (IS_ERR(*phys[i].phy)) + return PTR_ERR(*phys[i].phy); + phy_set_drvdata(*phys[i].phy, atcphy); + } + + atcphy->phy_provider =3D devm_of_phy_provider_register(atcphy->dev, atcph= y_xlate); + if (IS_ERR(atcphy->phy_provider)) + return PTR_ERR(atcphy->phy_provider); + return 0; +} + +static void _atcphy_dwc3_reset_assert(struct apple_atcphy *atcphy) +{ + lockdep_assert_held(&atcphy->lock); + + clear32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, PIPEHANDLER_AON_G= EN_DWC3_RESET_N); + set32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN); +} + +static int atcphy_dwc3_reset_assert(struct reset_controller_dev *rcdev, un= signed long id) +{ + struct apple_atcphy *atcphy =3D container_of(rcdev, struct apple_atcphy, = rcdev); + int ret; + + guard(mutex)(&atcphy->lock); + + _atcphy_dwc3_reset_assert(atcphy); + + if (atcphy->pipehandler_up) { + ret =3D atcphy_configure_pipehandler_dummy(atcphy); + if (ret) + dev_warn(atcphy->dev, "Failed to switch PIPE to dummy: %d\n", ret); + else + atcphy->pipehandler_up =3D false; + } + + atcphy_usb2_power_off(atcphy); + + atcphy->dwc3_running =3D false; + + return 0; +} + +static int atcphy_dwc3_reset_deassert(struct reset_controller_dev *rcdev, = unsigned long id) +{ + struct apple_atcphy *atcphy =3D container_of(rcdev, struct apple_atcphy, = rcdev); + + guard(mutex)(&atcphy->lock); + + clear32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN); + set32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, PIPEHANDLER_AON_GEN= _DWC3_RESET_N); + + atcphy->dwc3_running =3D true; + + return 0; +} + +const struct reset_control_ops atcphy_dwc3_reset_ops =3D { + .assert =3D atcphy_dwc3_reset_assert, + .deassert =3D atcphy_dwc3_reset_deassert, +}; + +static int atcphy_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return 0; +} + +static int atcphy_probe_rcdev(struct apple_atcphy *atcphy) +{ + atcphy->rcdev.owner =3D THIS_MODULE; + atcphy->rcdev.nr_resets =3D 1; + atcphy->rcdev.ops =3D &atcphy_dwc3_reset_ops; + atcphy->rcdev.of_node =3D atcphy->dev->of_node; + atcphy->rcdev.of_reset_n_cells =3D 0; + atcphy->rcdev.of_xlate =3D atcphy_reset_xlate; + + return devm_reset_controller_register(atcphy->dev, &atcphy->rcdev); +} + +static int atcphy_sw_set(struct typec_switch_dev *sw, enum typec_orientati= on orientation) +{ + struct apple_atcphy *atcphy =3D typec_switch_get_drvdata(sw); + + guard(mutex)(&atcphy->lock); + + switch (orientation) { + case TYPEC_ORIENTATION_NONE: + break; + case TYPEC_ORIENTATION_NORMAL: + atcphy->swap_lanes =3D false; + break; + case TYPEC_ORIENTATION_REVERSE: + atcphy->swap_lanes =3D true; + break; + } + + return 0; +} + +static int atcphy_probe_switch(struct apple_atcphy *atcphy) +{ + struct typec_switch_desc sw_desc =3D { + .drvdata =3D atcphy, + .fwnode =3D atcphy->dev->fwnode, + .set =3D atcphy_sw_set, + }; + + return PTR_ERR_OR_ZERO(typec_switch_register(atcphy->dev, &sw_desc)); +} + +static int atcphy_mux_set(struct typec_mux_dev *mux, struct typec_mux_stat= e *state) +{ + struct apple_atcphy *atcphy =3D typec_mux_get_drvdata(mux); + + guard(mutex)(&atcphy->lock); + + if (state->mode =3D=3D TYPEC_STATE_SAFE) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } else if (state->mode =3D=3D TYPEC_STATE_USB) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3; + } else if (!state->alt && state->mode =3D=3D TYPEC_MODE_USB4) { + struct enter_usb_data *data =3D state->data; + u32 eudo_usb_mode =3D FIELD_GET(EUDO_USB_MODE_MASK, data->eudo); + + switch (eudo_usb_mode) { + case EUDO_USB_MODE_USB2: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB2; + break; + case EUDO_USB_MODE_USB3: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3; + break; + case EUDO_USB_MODE_USB4: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB4; + break; + default: + dev_warn(atcphy->dev, "Unsupported EUDO USB mode: 0x%x.\n", eudo_usb_mo= de); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + } else if (state->alt && state->alt->svid =3D=3D USB_TYPEC_TBT_SID) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_TBT; + } else if (state->alt && state->alt->svid =3D=3D USB_TYPEC_DP_SID) { + switch (state->mode) { + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_DP; + break; + case TYPEC_DP_STATE_D: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3_DP; + break; + default: + dev_err(atcphy->dev, + "Unsupported DP pin assignment: 0x%lx, your connected device will not = work.\n", + state->mode); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + } else if (state->alt) { + dev_err(atcphy->dev, + "Unknown alternate mode SVID: 0x%x, your connected device will not work= .\n", + state->alt->svid); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } else { + dev_err(atcphy->dev, "Unknown mode: 0x%lx, your connected device will no= t work.\n", + state->mode); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + + if (atcphy->mode =3D=3D atcphy->target_mode) + return 0; + + /* + * If the pipehandler is up the PHY has previously been up and we need + * to wait for dwc3 to shut down before we can reconfigure the PHY. + * Thus, defer reconfiguration to atcphy_usb3_power_off. + * The Type-C port controller will ensure this is called through a role + * switch to USB_ROLE_NONE (and then possibly to HOST/DEVICE if the + * target mode isn't off). + */ + if (!atcphy->pipehandler_up) + return atcphy_configure(atcphy, atcphy->target_mode); + return 0; +} + +static int atcphy_probe_mux(struct apple_atcphy *atcphy) +{ + struct typec_mux_desc mux_desc =3D { + .drvdata =3D atcphy, + .fwnode =3D atcphy->dev->fwnode, + .set =3D atcphy_mux_set, + }; + + return PTR_ERR_OR_ZERO(typec_mux_register(atcphy->dev, &mux_desc)); +} + +static int atcphy_load_tunables(struct apple_atcphy *atcphy) +{ + int ret; + struct { + const char *dt_name; + struct apple_tunable **tunable; + } tunables[] =3D { + { "apple,tunable-fuses", &atcphy->tunables.fuses }, + { "apple,tunable-axi2af", &atcphy->tunables.axi2af }, + { "apple,tunable-common", &atcphy->tunables.common }, + { "apple,tunable-lane0-usb", &atcphy->tunables.lane_usb3[0] }, + { "apple,tunable-lane1-usb", &atcphy->tunables.lane_usb3[1] }, + { "apple,tunable-lane0-cio", &atcphy->tunables.lane_usb4[0] }, + { "apple,tunable-lane1-cio", &atcphy->tunables.lane_usb4[1] }, + { "apple,tunable-lane0-dp", &atcphy->tunables.lane_displayport[0] }, + { "apple,tunable-lane1-dp", &atcphy->tunables.lane_displayport[1] }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(tunables); i++) { + *tunables[i].tunable =3D + devm_apple_tunable_parse(atcphy->dev, atcphy->np, tunables[i].dt_name); + if (IS_ERR(tunables[i].tunable)) { + dev_err(atcphy->dev, "Failed to read tunable %s: %ld\n", + tunables[i].dt_name, PTR_ERR(tunables[i].tunable)); + return ret; + } + } + + return 0; +} + +static int atcphy_map_resources(struct platform_device *pdev, struct apple= _atcphy *atcphy) +{ + struct { + const char *name; + void __iomem **addr; + } resources[] =3D { + { "core", &atcphy->regs.core }, + { "lpdptx", &atcphy->regs.lpdptx }, + { "axi2af", &atcphy->regs.axi2af }, + { "usb2phy", &atcphy->regs.usb2phy }, + { "pipehandler", &atcphy->regs.pipehandler }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(resources); i++) { + *resources[i].addr =3D devm_platform_ioremap_resource_byname(pdev, resou= rces[i].name); + if (IS_ERR(resources[i].addr)) + return dev_err_probe(atcphy->dev, PTR_ERR(resources[i].addr), + "Unable to map %s regs", resources[i].name); + } + + return 0; +} + +static int atcphy_probe_finalize(struct apple_atcphy *atcphy) +{ + int ret; + + guard(mutex)(&atcphy->lock); + + /* Reset dwc3 on probe, let dwc3 (consumer) deassert it */ + _atcphy_dwc3_reset_assert(atcphy); + + /* Reset atcphy to clear any state potentially left by the bootloader */ + atcphy_power_off(atcphy); + atcphy_setup_pipehandler(atcphy); + + ret =3D atcphy_probe_rcdev(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing rcdev failed"); + ret =3D atcphy_probe_mux(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing mux failed"); + ret =3D atcphy_probe_switch(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing switch failed"); + ret =3D atcphy_probe_phy(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing phy failed"); + + return 0; +} + +static int atcphy_probe(struct platform_device *pdev) +{ + struct apple_atcphy *atcphy; + struct device *dev =3D &pdev->dev; + int ret; + + atcphy =3D devm_kzalloc(&pdev->dev, sizeof(*atcphy), GFP_KERNEL); + if (!atcphy) + return -ENOMEM; + + atcphy->dev =3D dev; + atcphy->np =3D dev->of_node; + mutex_init(&atcphy->lock); + platform_set_drvdata(pdev, atcphy); + + ret =3D atcphy_map_resources(pdev, atcphy); + if (ret) + return ret; + ret =3D atcphy_load_tunables(atcphy); + if (ret) + return ret; + + atcphy->mode =3D APPLE_ATCPHY_MODE_OFF; + atcphy->pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_INVALID; + atcphy->dwc3_running =3D false; + atcphy->pipehandler_up =3D false; + + return atcphy_probe_finalize(atcphy); +} + +static const struct of_device_id atcphy_match[] =3D { + { .compatible =3D "apple,t8103-atcphy" }, + {}, +}; +MODULE_DEVICE_TABLE(of, atcphy_match); + +static struct platform_driver atcphy_driver =3D { + .driver =3D { + .name =3D "phy-apple-atc", + .of_match_table =3D atcphy_match, + }, + .probe =3D atcphy_probe, +}; +module_platform_driver(atcphy_driver); + +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple Type-C PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Sep 9 05:50:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34232F49E6; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=eAI4VmnwHzdGJxfOz/T6LC6R120KmqMcZ67Vc+MLAp7uLLOelDK3dNC5bfjeoVpQhWJdssDF+mtw4gx+bF0Z6CEBJ+zCsShh2T18d7UpoRpk21LVTnKWCL8w773XGFtyzVaOyff7ejumUHLuHMoZuTo3fpQQoVABzpO3b/VhXD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=BntybK4ghItAd51ZFEoy/6BXMrI0MX3OXUGh7tlF2wQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sJF+4p22PGAzeifYUWbK1sGCYZMtwuDElbkB7r8B+NAnt/c+8GpeRKpr+lhA/WedpzF6dbYvv48K9A1jeZ8+dfMha9/eELnlpJxe/vwFZh9JsVDuK6RFEUbSeqa0MXIFRcb0ipggfBylWtIFrrNTzVnRofc/gcFnPADTrEPFvIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nd5VJLex; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nd5VJLex" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7D3D1C4CEF7; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=BntybK4ghItAd51ZFEoy/6BXMrI0MX3OXUGh7tlF2wQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nd5VJLexn/JNO4rQ46wZHaAA2rdXQy4WRFRU83/JHb0FCIdv3m6jJ2NDxaNRost4E PCEEJqy3ZF9tH3znRQjppDMlltPH4XpTjHnzRoMmD6yeJnfzjFSfNakibLeKbXR+ag LndOYU1l2otaKyHEyN1GNBPT02XugtH8rLJgMWfE7caUVvRiT6Wezl8EaLjuccZVgu HWrZhQDbYB3RHOH+7aDKYl6/GGo7pfMICv7A+yF3sEdUAqxwUKJLQhB3HoAg7Gr3hn ltb2kUnEZr4jTpoNieECWl2dT6gxhfA6a2xmOG/tm7/FbL6pofBGiDLZIdNXhBMa8Y WQDGGNao7uQhg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61C2ECAC581; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:32 +0000 Subject: [PATCH v2 19/22] arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-19-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1274; i=sven@kernel.org; h=from:subject:message-id; bh=KlPzmlrett6VZZaPvH7/eARfg+MitLPN79oIzdJZz0w=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesKVv25TfrFpgvlCt8mzcumJ9y0ztH/ZTDEKmtq9d+ JrN7fHhjlIWBjEOBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBEijYzMlzqWq1rX7rFWLbo CqNLej/H3vy0+wfTkpMYojP4V6drTGX471lmNdN+57zemxNlS/z67s02e/uXacWdf5lZh0u388t V8QIA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Shutting these down breaks dwc3 init done by the firmware. We probably never want to do this anyway. The initialisation done in the ATC phy driver is not sufficient to bring dwc3 back up after these power-domains were shutdown for example after suspend to idle. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8103-pmgr.dtsi index c41c57d63997a59a9fe3c88de31fddb31781398e..4bfe0d2de30ad6f975b31d443b6= 2ef0e74b14324 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -1103,6 +1103,7 @@ ps_atc0_usb_aon: power-controller@88 { #power-domain-cells =3D <0>; #reset-cells =3D <0>; label =3D "atc0_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; =20 ps_atc1_usb_aon: power-controller@90 { @@ -1111,6 +1112,7 @@ ps_atc1_usb_aon: power-controller@90 { #power-domain-cells =3D <0>; #reset-cells =3D <0>; label =3D "atc1_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; =20 ps_atc0_usb: power-controller@98 { --=20 2.34.1 From nobody Tue Sep 9 05:50:28 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC7BF2F4A16; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; cv=none; b=P1j5wLst5P49ZGehMD+3C703tjR+ovMMU/TVjKqfadqIRpOvVO6DSQidEKSRtk+wLVvJbyo9fslougZXdjTAl4LTarbNuWUrn0gz+/PXcHrawC6tKIyX29VgJ42rZ6EnvRFF/9B1Cx3iOJrmH0RvzMUsz43YncO3ZJxqECz5LjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173420; c=relaxed/simple; bh=1cAbo9qjTQz9D7gtBYoRZ1si0Ch/NYth8AtFWmyYid0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SjhQARiwKjjkWravVRbFgbMVd+ePj572n1U3l1J/5tJ94grdOJoTr5wDDrqUpBzmtzt6YfiAnn1soal8YggA/RHu04lxaueYrFQs+t4nypD5Tk99wdKkThY+qSsq4ZVl2KjIF5flnVT5HyD2wC5mrq3Xljx2gx1Hrqzst09jS2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CLhdTWN7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CLhdTWN7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9322DC4CEF9; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=1cAbo9qjTQz9D7gtBYoRZ1si0Ch/NYth8AtFWmyYid0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CLhdTWN7518b2YOZowl6uCZwUxi++4k1F1qckpDAxy8CETpIqc4fiRIn+Bx1NVlAW Mv3if92PKSZvnlGyZIH5c/nZBvIEGadIsml2nw7Qr4HFnuXOlSb8bsbHdSdTx8mFfd 9uL4RkhrRUcQSi37RwbtfhjztXy9R/otvtbFlpW55u3wbLTgKMeR/ByAKIhgSFz/Ac E+TA0d3rSOczq+vaKq3QWzPiRj7xjIedG66OxxwENd79o0nix6Z3yXcmkmbHKb8OTD hnA+8lmn7p7wUwfZHDC94E/lNpqN2xGH/fp8uTmY2tUlr3yB78HlIFSUfG7OzIFaGV UXpqLD5jbLDzA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E6E6CA1012; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:33 +0000 Subject: [PATCH v2 20/22] arm64: dts: apple: t8103: Add Apple Type-C PHY and dwc3 nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-20-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10863; i=sven@kernel.org; h=from:subject:message-id; bh=1cAbo9qjTQz9D7gtBYoRZ1si0Ch/NYth8AtFWmyYid0=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesGUd8VN/rhB+X1KvfeIja8NKqZa5Qt3LlUofZdj8b ReLnSDbUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZjI0hxGhoY4D2Z+vlOprPzJ Qt6+p85FqGetYyvMKCybvuFz5LSPjAx/+P/md1wKfh367VPJrUdKwqxh6b39r4/Pn5ySeMz2PrM rNwA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add all nodes and connections required to make USB3 work on M1-based Apple machines. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j274.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j293.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j313.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j456.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j457.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 137 ++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t8103.dtsi | 105 +++++++++++++++++++++++ 7 files changed, 302 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts= /apple/t8103-j274.dts index 1c3e37f86d46d7b5d733717b47c4b57dc55e1201..968fe22163d4431fe5e70498546= 87e61e0ec50f1 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -29,6 +29,18 @@ &wifi0 { brcm,board-type =3D "apple,atlantisb"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-left"; +}; + +&typec1 { + label =3D "USB-C Back-right"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts= /apple/t8103-j293.dts index 5b3c42e9f0e6776241bf746d3458766e44e3639a..678f89c3d47fbf2d0705b46bb8f= eba3fa018ca7a 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -46,6 +46,18 @@ &wifi0 { brcm,board-type =3D "apple,honshu"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; + &i2c2 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts= /apple/t8103-j313.dts index 97a4344d8dca685708aff136af92a1b316f3c3dd..bce9b911009e2b0caa9d8b2222c= d1e8c3215f3b9 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -41,3 +41,15 @@ &wifi0 { &fpwm1 { status =3D "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts= /apple/t8103-j456.dts index 58c8e43789b4861544e20c717124ede3327be010..9983e11cacdf19d0a92ede108ce= ac21b7a02d5da 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -47,6 +47,18 @@ hpm3: usb-pd@3c { }; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-right"; +}; + +&typec1 { + label =3D "USB-C Back-right-middle"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts= /apple/t8103-j457.dts index 152f95fd49a2118093396838fbd8b6bd1b518f81..a622ff607d407519000d1526b72= 44419a59644a3 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -29,6 +29,18 @@ &wifi0 { brcm,board-type =3D "apple,santorini"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-right"; +}; + +&typec1 { + label =3D "USB-C Back-left"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8103-jxxx.dtsi index 0c8206156bfefda8a32c869787b2e0c8e67a9d17..758b2196954bc139c201d252984= 44f59c7832ea5 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -15,6 +15,8 @@ aliases { serial0 =3D &serial0; serial2 =3D &serial2; wifi0 =3D &wifi0; + atcphy0 =3D &atcphy0; + atcphy1 =3D &atcphy1; }; =20 chosen { @@ -53,6 +55,30 @@ hpm0: usb-pd@38 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec0: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec0_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec0_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; =20 hpm1: usb-pd@3f { @@ -61,6 +87,117 @@ hpm1: usb-pd@3f { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec1: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec1_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_hs>; + }; + }; + + port@1 { + reg =3D <1>; + typec1_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_hs: endpoint { + remote-endpoint =3D <&typec0_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_ss: endpoint { + remote-endpoint =3D <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_hs: endpoint { + remote-endpoint =3D <&typec1_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_ss: endpoint { + remote-endpoint =3D <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint =3D <&typec0_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint =3D <&typec1_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_ss>; + }; + }; }; }; =20 diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 589ddc0397995ecf6fc11b135164229ab1ee7cf8..f22a1feaf459ddf1601ce7374c2= aa0c216b371a1 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -972,6 +973,110 @@ nvme@27bcc0000 { resets =3D <&ps_ans2>; }; =20 + dwc3_0: usb@382280000 { + compatible =3D "apple,t8103-dwc3"; + reg =3D <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains =3D <&ps_atc0_usb>; + resets =3D <&atcphy0>; + phys =3D <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible =3D "apple,t8103-dwc3"; + reg =3D <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains =3D <&ps_atc1_usb>; + resets =3D <&atcphy1>; + phys =3D <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc1_usb>; + }; + pcie0_dart_0: iommu@681008000 { compatible =3D "apple,t8103-dart"; reg =3D <0x6 0x81008000 0x0 0x4000>; --=20 2.34.1 From nobody Tue Sep 9 05:50:28 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B1942F616D; Sat, 6 Sep 2025 15:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173421; cv=none; b=UeVmQbSGGL7NXnSVURRoFVc8i5lO9S5FQEwYWyj3D/PEXEN49DVvjmLwz/ul+/cg+z6D43QQUdUxWjv/y2k3/cU4ryx4QW3kuefNRs4jAd43TYL/SDYuGYmD/QoQO3K71q6Y1S0TlYJUL7pGtmtDokoWBosORqeG6RZydfKA9TA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173421; c=relaxed/simple; bh=NH51MzAzyh8diSauo8bR8An2mVNgzKZSYMmuxIBItwA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hJGV+cEIuzCbZV63P4PaeEtAMr9d8pEP68M4ZQ4NpLfYJuq9+SfZLEL/m/nnE0R3hmHPIhO76shdBXWWjJl5oMd48NsWrb2Ia6EIcxss/WuUoDGFYMm4egrZf8e71tS36uOI/cSAAG5Jh40KBdCGM5yq1N6568FQLiCgNlGzcbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MYgt75YT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MYgt75YT" Received: by smtp.kernel.org (Postfix) with ESMTPS id A974CC4CEFE; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=NH51MzAzyh8diSauo8bR8An2mVNgzKZSYMmuxIBItwA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MYgt75YTfnqSQHfi68s3aUzns+30M8xeTto86ogHhS9pEZSyt30BCGSksMZglEkFl xohI61lzIh9ErrsYQo0NTdnEAJv+tRz/ioblNDIsqpvJk55s5DbajHJu4p0+/Ob9VM dz80oECKGn97EqU8P8ovOBhA9RfuBdbeWgg+6qSjOIWdxRndy9HLr1zWyzQ+vooyE+ 3y4s8kUGwdF/27yw59oWAGMXtkY6/ZeX9+IqSsDzXzrDH2A5FMhyGmqGeenQv7btR0 PpH9eJztY8iZU/G+09dc8IkVWut4GtXbj/2Q1QJrfMk0pCvjGqm6h2QaQBsyuZsf+M 12VqmrYP+RRsQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F7DECAC582; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:34 +0000 Subject: [PATCH v2 21/22] arm64: dts: apple: t8112: Add Apple Type-C PHY and dwc3 nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-21-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9487; i=sven@kernel.org; h=from:subject:message-id; bh=mZodhmevK5McJtAr47bnBGjk3dlXrSRKjihXBaSMM9E=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesOXhi54LZc55Zay2PXXCqhM5/zhMHsma5E5/nLSw4 2ZEAPfljlIWBjEOBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBENCwY/meIe7jbRnm//hmS FWBTy6D31vpPULnSx55DZZxZb5eWFzH805XbvHanaGvdukWuDnOlHf3ZvgmvdLVRv3aMI205x6w 5nAA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Janne Grunau Add all nodes and connections required to make USB3 work on M2-based Apple machines. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112-j413.dts | 12 +++ arch/arm64/boot/dts/apple/t8112-j473.dts | 11 +++ arch/arm64/boot/dts/apple/t8112-j493.dts | 12 +++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 137 ++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t8112.dtsi | 105 +++++++++++++++++++++++ 5 files changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts= /apple/t8112-j413.dts index 6f69658623bf89ce73e3486bce504f1f5f8003f3..21e81a8899d8d7ff5461db085b5= 3feccc7c53f64 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -60,6 +60,18 @@ bluetooth0: bluetooth@0,1 { }; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; + &i2c0 { /* MagSafe port */ hpm5: usb-pd@3a { diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts= /apple/t8112-j473.dts index 06fe257f08be498ace6906b936012e01084da702..3fb236c7cba0ba7d02910ab0f98= f8eea92902d5a 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -21,6 +21,17 @@ aliases { }; }; =20 +/* + * Provide labels for the USB type C ports. + */ +&typec0 { + label =3D "USB-C Back-left"; +}; + +&typec1 { + label =3D "USB-C Back-right"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts= /apple/t8112-j493.dts index fb8ad7d4c65a8fe7966f5541f24f03a379143cfb..f8e442152ff23f21a46916ac111= e5f6bbc87cf83 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -108,6 +108,18 @@ bluetooth0: bluetooth@0,1 { }; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; + &i2c4 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8112-jxxx.dtsi index 6da35496a4c88dbaba125ebbe8c5a4a428c647c3..f1dd7e8f493140f5a1d12b63abd= fbe4e2419ca05 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -11,6 +11,8 @@ =20 / { aliases { + atcphy0 =3D &atcphy0; + atcphy1 =3D &atcphy1; serial0 =3D &serial0; serial2 =3D &serial2; }; @@ -53,6 +55,30 @@ hpm0: usb-pd@38 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec0: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec0_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec0_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; =20 hpm1: usb-pd@3f { @@ -61,6 +87,117 @@ hpm1: usb-pd@3f { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec1: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec1_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_hs>; + }; + }; + + port@1 { + reg =3D <1>; + typec1_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_hs: endpoint { + remote-endpoint =3D <&typec0_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_ss: endpoint { + remote-endpoint =3D <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_hs: endpoint { + remote-endpoint =3D <&typec1_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_ss: endpoint { + remote-endpoint =3D <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint =3D <&typec0_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint =3D <&typec1_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_ss>; + }; + }; }; }; =20 diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index b36b345861b6efa7104e525d6d0de9a7ba604ca9..640c817f445829dbc42f1d3e810= d24674fbf1f74 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 / { @@ -975,6 +976,110 @@ nvme@27bcc0000 { resets =3D <&ps_ans>; }; =20 + dwc3_0: usb@382280000 { + compatible =3D "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg =3D <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains =3D <&ps_atc0_usb>; + resets =3D <&atcphy0>; + phys =3D <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible =3D "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg =3D <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible =3D "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg =3D <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains =3D <&ps_atc1_usb>; + resets =3D <&atcphy1>; + phys =3D <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible =3D "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg =3D <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc1_usb>; + }; + pcie0_dart: iommu@681008000 { compatible =3D "apple,t8110-dart"; reg =3D <0x6 0x81008000 0x0 0x4000>; --=20 2.34.1 From nobody Tue Sep 9 05:50:28 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D2352F7441; Sat, 6 Sep 2025 15:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173421; cv=none; b=PSCK2uppyO7YhHLdJIFc5HMj9RxSefUVLQ4rwt72UeCiCi0W1jExXdFG/l287cMvLq8ZZs8/P5ku+Hoy1bgOhwNdiD3dcjTzaENKOgXwkqSr9qOZ7z5or+EgDIRUMBGfgmtZaF6wo0H8BslhbZ/u2UJ/c6XTijFGW1oS0O8ZSvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757173421; c=relaxed/simple; bh=KTAyeqUKBXSRXTrOzHfCOiEQdd5Glj7VWy4aaK3uSPI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K1T9vXuYd36MwGHZtf7kBRDyV1VsB5cO5Iirfp7X+3LcC39W11u63F6Da2+8W5Umy3hI7J3BzlDf+wRGVXW8m3OPbtoI+k84Yhit7rdPH8vPnSf3x5Ul2pzwzJL76UtsrYx2diU6YO0O5L8EEDU/m0mislUM+d+MhhNDFFe9QgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OGf0OvnR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OGf0OvnR" Received: by smtp.kernel.org (Postfix) with ESMTPS id B9C68C4CEFB; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757173420; bh=KTAyeqUKBXSRXTrOzHfCOiEQdd5Glj7VWy4aaK3uSPI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OGf0OvnRpnZKswhahXWJhN0m/rfuq9MM1u+MJt6rRonM2fEsuNvdj5na2wOHufv+H ReswnIBbmDc6S/yQz4YFNWQ0ykA/xDnzgGBa6N5hywwVGVm0dIvoGKPkD4TjfZAfQN mvTucRbpWmlr7tzhDlvsFHo/DDrMyeBtAPHbj8QslWlkNvNonfOzQ7onPUztmIaS0R A1NWsSFfm44G15oP11rlP6PDDR4ZGsc1ttTEffhYYwljYp22QxvNa3yEaUysrrSsc7 PMEKmCeZtlyfn59k3Ewnk5RsotFRpCIFBVDpF061xReeOcPFc3AtXjVvIym866z7LM l7Mb7AAHx5ZPA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B61CAC583; Sat, 6 Sep 2025 15:43:40 +0000 (UTC) From: Sven Peter Date: Sat, 06 Sep 2025 15:43:35 +0000 Subject: [PATCH v2 22/22] arm64: dts: apple: t600x: Add Apple Type-C PHY and dwc3 nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-atcphy-6-17-v2-22-52c348623ef6@kernel.org> References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> In-Reply-To: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , R X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=25022; i=sven@kernel.org; h=from:subject:message-id; bh=Gz8VC2GdnmHU+sqgZZgFGx+yLwOX3aB1YhMwtYgCrWg=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8aesOV8orkmE2t2HE7M8xBvEu478k182/Knem5MGhkvr 7rdbNnRUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZiIUhDDX/Fkh1sfTK6sumib eSKbJfRWxEPx2kNsjZwPZ0T5n95wxIGRYXNSbkvk+n39PX9z7v3c73swROyvxsN8xpd75Ew7xTf /YwMA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Janne Grunau Add all nodes and connections required to make USB3 work on M1 Pro, Max and Ultra based Apple machines. Co-developed-by: R Signed-off-by: R Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6001.dtsi | 1 + arch/arm64/boot/dts/apple/t6002-j375d.dts | 197 +++++++++++++++++- arch/arm64/boot/dts/apple/t6002.dtsi | 1 + arch/arm64/boot/dts/apple/t600x-dieX.dtsi | 212 +++++++++++++++++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 236 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 275 +++++++++++++++++++++= ++++ 6 files changed, 916 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/app= le/t6001.dtsi index ffbe823b71bc8d9c0975524aa04efa9bf520a89e..6dcb71a1d65a8da82a512653a34= ce6af3df8aee0 100644 --- a/arch/arm64/boot/dts/apple/t6001.dtsi +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dt= s/apple/t6002-j375d.dts index 3365429bdc8be90b63c8051822243d897854ab27..3b4715d5754c12848d418a71124= b443c034af3e7 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -15,6 +15,11 @@ / { compatible =3D "apple,j375d", "apple,t6002", "apple,arm-platform"; model =3D "Apple Mac Studio (M1 Ultra, 2022)"; + + aliases { + atcphy4 =3D &atcphy0_die1; + atcphy5 =3D &atcphy1_die1; + }; }; =20 /* USB Type C */ @@ -26,6 +31,30 @@ hpm4: usb-pd@39 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec4: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Front Right"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + typec4_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_die1_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec4_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_die1_typec_lanes>; + }; + }; + }; + }; }; =20 /* front-left */ @@ -35,16 +64,172 @@ hpm5: usb-pd@3a { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec5: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Front Left"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + typec5_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_die1_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec5_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_die1_typec_lanes>; + }; + }; + }; + }; }; }; =20 +/* USB controllers on die 1 */ +&dwc3_0_die1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_die1_hs: endpoint { + remote-endpoint =3D <&typec4_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_die1_ss: endpoint { + remote-endpoint =3D <&atcphy0_die1_usb3>; + }; + }; + }; +}; + +&dwc3_1_die1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_die1_hs: endpoint { + remote-endpoint =3D <&typec5_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_die1_ss: endpoint { + remote-endpoint =3D <&atcphy1_die1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0_die1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_die1_typec_lanes: endpoint { + remote-endpoint =3D <&typec4_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_die1_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_die1_ss>; + }; + }; + }; +}; + +&atcphy1_die1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_die1_typec_lanes: endpoint { + remote-endpoint =3D <&typec5_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_die1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_die1_ss>; + }; + }; + }; +}; + + +/* Disable unused dwc3 instandes on the second die. */ +&dwc3_2_dart_0_die1 { + status =3D "disabled"; +}; + +&dwc3_2_dart_1_die1 { + status =3D "disabled"; +}; + +&dwc3_2_die1 { + status =3D "disabled"; +}; + +&dwc3_3_dart_0_die1 { + status =3D "disabled"; +}; + +&dwc3_3_dart_1_die1 { + status =3D "disabled"; +}; + +&dwc3_3_die1 { + status =3D "disabled"; +}; + +/* Disable unused ATC phy instandes on the second die. */ +&atcphy2_die1 { + status =3D "disabled"; +}; + +&atcphy3_die1 { + status =3D "disabled"; +}; + +/* Disable unused USB power-domains on the second die. */ +&ps_atc2_usb_aon_die1 { + status =3D "disabled"; +}; + +&ps_atc2_usb_die1 { + status =3D "disabled"; +}; + +&ps_atc3_usb_aon_die1 { + status =3D "disabled"; +}; + +&ps_atc3_usb_die1 { + status =3D "disabled"; +}; + /* delete unused always-on power-domains on die 1 */ =20 -/delete-node/ &ps_atc2_usb_aon_die1; -/delete-node/ &ps_atc2_usb_die1; - -/delete-node/ &ps_atc3_usb_aon_die1; -/delete-node/ &ps_atc3_usb_die1; - /delete-node/ &ps_disp0_cpu0_die1; /delete-node/ &ps_disp0_fe_die1; diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/app= le/t6002.dtsi index 8fb648836b538bbd9efdccd6cec5d08d868a0d39..a532e5401c4ec430d8ff649a924= 59c80e9b6bb2b 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t600x-dieX.dtsi index a32ff0c9d7b0c2ec720e9d4cf8e769da6431fbba..a282029475af874db7bf760017e= 1345ca982d94e 100644 --- a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -119,3 +119,215 @@ DIE_NODE(pinctrl_ap): pinctrl@39b028000 { interrupt-controller; #interrupt-cells =3D <2>; }; + + DIE_NODE(dwc3_0_dart_0): iommu@702f00000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0x7 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_0_dart_1): iommu@702f80000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0x7 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_0): usb@702280000 { + compatible =3D "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg =3D <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&DIE_NODE(dwc3_0_dart_0) 0>, + <&DIE_NODE(dwc3_0_dart_1) 1>; + power-domains =3D <&DIE_NODE(ps_atc0_usb)>; + resets =3D <&DIE_NODE(atcphy0)>; + phys =3D <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYP= E_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(atcphy0): phy@703000000 { + compatible =3D "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg =3D <0x7 0x03000000 0x0 0x4c000>, + <0x7 0x03050000 0x0 0x8000>, + <0x7 0x00000000 0x0 0x4000>, + <0x7 0x02a90000 0x0 0x4000>, + <0x7 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&DIE_NODE(ps_atc0_usb)>; + }; + + DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0xb 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0xb 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_1): usb@b02280000 { + compatible =3D "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg =3D <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&DIE_NODE(dwc3_1_dart_0) 0>, + <&DIE_NODE(dwc3_1_dart_1) 1>; + power-domains =3D <&DIE_NODE(ps_atc1_usb)>; + resets =3D <&DIE_NODE(atcphy1)>; + phys =3D <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYP= E_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(atcphy1): phy@b03000000 { + compatible =3D "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg =3D <0xb 0x03000000 0x0 0x4c000>, + <0xb 0x03050000 0x0 0x8000>, + <0xb 0x00000000 0x0 0x4000>, + <0xb 0x02a90000 0x0 0x4000>, + <0xb 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&DIE_NODE(ps_atc1_usb)>; + }; + + DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0xf 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0xf 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_2): usb@f02280000 { + compatible =3D "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg =3D <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3c00>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&DIE_NODE(dwc3_2_dart_0) 0>, + <&DIE_NODE(dwc3_2_dart_1) 1>; + power-domains =3D <&DIE_NODE(ps_atc2_usb)>; + resets =3D <&DIE_NODE(atcphy2)>; + phys =3D <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYP= E_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(atcphy2): phy@f03000000 { + compatible =3D "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg =3D <0xf 0x03000000 0x0 0x4c000>, + <0xf 0x03050000 0x0 0x8000>, + <0xf 0x00000000 0x0 0x4000>, + <0xf 0x02a90000 0x0 0x4000>, + <0xf 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&DIE_NODE(ps_atc2_usb)>; + }; + + DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0x13 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 { + compatible =3D "apple,t6000-dart"; + reg =3D <0x13 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells =3D <1>; + }; + + DIE_NODE(dwc3_3): usb@1302280000 { + compatible =3D "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg =3D <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>; + reg-names =3D "dwc3-core", "dwc3-apple"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&DIE_NODE(dwc3_3_dart_0) 0>, + <&DIE_NODE(dwc3_3_dart_1) 1>; + power-domains =3D <&DIE_NODE(ps_atc3_usb)>; + resets =3D <&DIE_NODE(atcphy3)>; + phys =3D <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYP= E_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(atcphy3): phy@1303000000 { + compatible =3D "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg =3D <0x13 0x03000000 0x0 0x4c000>, + <0x13 0x03050000 0x0 0x8000>, + <0x13 0x00000000 0x0 0x4000>, + <0x13 0x02a90000 0x0 0x4000>, + <0x13 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&DIE_NODE(ps_atc3_usb)>; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-j314-j316.dtsi index 22ebc78e120bf8f0f71fd532e9dce4dcd117bbc6..13e654849eb3d637ac21479a3de= f8f8ddd731dd6 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -13,6 +13,10 @@ =20 / { aliases { + atcphy0 =3D &atcphy0; + atcphy1 =3D &atcphy1; + atcphy2 =3D &atcphy2; + atcphy3 =3D &atcphy3; serial0 =3D &serial0; wifi0 =3D &wifi0; }; @@ -62,6 +66,31 @@ hpm0: usb-pd@38 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec0: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Left Rear"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec0_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec0_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; =20 hpm1: usb-pd@3f { @@ -70,6 +99,31 @@ hpm1: usb-pd@3f { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec1: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Left Front"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec1_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec1_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; =20 hpm2: usb-pd@3b { @@ -78,6 +132,31 @@ hpm2: usb-pd@3b { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec2: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Right"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec2_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_2_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec2_connector_ss: endpoint { + remote-endpoint =3D <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; =20 /* MagSafe port */ @@ -90,6 +169,163 @@ hpm5: usb-pd@3a { }; }; =20 +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_hs: endpoint { + remote-endpoint =3D <&typec0_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_ss: endpoint { + remote-endpoint =3D <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_hs: endpoint { + remote-endpoint =3D <&typec1_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_ss: endpoint { + remote-endpoint =3D <&atcphy1_usb3>; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_2_hs: endpoint { + remote-endpoint =3D <&typec2_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_2_ss: endpoint { + remote-endpoint =3D <&atcphy2_usb3>; + }; + }; + }; +}; + +/* The 4th ATC Phy is connected to an internal DP to HDMI converter. */ +&dwc3_3_dart_0 { + status =3D "disabled"; +}; + +&dwc3_3_dart_1 { + status =3D "disabled"; +}; + +&dwc3_3 { + status =3D "disabled"; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint =3D <&typec0_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint =3D <&typec1_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint =3D <&typec2_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy2_usb3: endpoint { + remote-endpoint =3D <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + /* Disable atcphy3 as long as DisplayPort is not supported. */ + status =3D "disabled"; +}; + +/* + * The ps_atcN_usb_aon power-domains are always-on to avoid resetting dwc3 + * which reverts initialisation done by firmware. + * atc3 is used exclusively for the DP-to-HDMI converter so this is not + * necessary. + */ +&ps_atc3_usb_aon { + /delete-property/ apple,always-on; +}; + &nco_clkref { clock-frequency =3D <1068000000>; }; diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dt= s/apple/t600x-j375.dtsi index d5b985ad567936111ee5cccc9ca9fc23d01d9edf..ab49ad9e32f2798bd126d079491= 7c8f434f222de 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -11,6 +11,10 @@ =20 / { aliases { + atcphy0 =3D &atcphy0; + atcphy1 =3D &atcphy1; + atcphy2 =3D &atcphy2; + atcphy3 =3D &atcphy3; serial0 =3D &serial0; wifi0 =3D &wifi0; }; @@ -48,6 +52,31 @@ hpm0: usb-pd@38 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec0: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Back Left"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec0_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec0_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; =20 hpm1: usb-pd@3f { @@ -56,6 +85,31 @@ hpm1: usb-pd@3f { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec1: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Back Left Middle"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec1_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec1_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; =20 hpm2: usb-pd@3b { @@ -64,6 +118,31 @@ hpm2: usb-pd@3b { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec2: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Back Right Middle"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec2_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_2_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec2_connector_ss: endpoint { + remote-endpoint =3D <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; =20 hpm3: usb-pd@3c { @@ -72,6 +151,202 @@ hpm3: usb-pd@3c { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec3: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C Back Right"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec3_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_3_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec3_connector_ss: endpoint { + remote-endpoint =3D <&atcphy3_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_hs: endpoint { + remote-endpoint =3D <&typec0_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_ss: endpoint { + remote-endpoint =3D <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_hs: endpoint { + remote-endpoint =3D <&typec1_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_ss: endpoint { + remote-endpoint =3D <&atcphy1_usb3>; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_2_hs: endpoint { + remote-endpoint =3D <&typec2_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_2_ss: endpoint { + remote-endpoint =3D <&atcphy2_usb3>; + }; + }; + }; +}; + +&dwc3_3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_3_hs: endpoint { + remote-endpoint =3D <&typec3_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_3_ss: endpoint { + remote-endpoint =3D <&atcphy3_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint =3D <&typec0_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint =3D <&typec1_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint =3D <&typec2_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy2_usb3: endpoint { + remote-endpoint =3D <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy3_typec_lanes: endpoint { + remote-endpoint =3D <&typec3_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy3_usb3: endpoint { + remote-endpoint =3D <&dwc3_3_ss>; + }; + }; }; }; =20 --=20 2.34.1