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charset="utf-8" Introduce new bindings for the Monaco Evaluation Kit (EVK), an IoT board based on the QCS8300 SoC. Signed-off-by: Umang Chheda Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 0110be27c4f6..7d47d0c04376 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -855,6 +855,7 @@ properties: - items: - enum: + - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 -- 2.34.1 From nobody Wed Sep 10 05:21:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D211727E04F for ; Fri, 5 Sep 2025 19:24:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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On top of Monaco EVK board additional mezzanine boards can be stacked in future. Add support for the following components : - GPI (Generic Peripheral Interface) and QUPv3-0/1 controllers to facilitate DMA and peripheral communication. - TCA9534 I/O expander via I2C to provide 8 additional GPIO lines for extended I/O functionality. - USB1 controller in device mode to support USB peripheral operations. USB OTG mode will be enabled for USB1 controller once the VBUS control based on ID pin is implemented in hd3ss3220.c. - Remoteproc subsystems for supported DSPs such as Audio DSP, Compute DSP and Generic DSP, along with their corresponding firmware. - Configure nvmem-layout on the I2C EEPROM to store data for Ethernet and other consumers. - QCA8081 2.5G Ethernet PHY on port-0 and expose the Ethernet MAC address via nvmem for network configuration. It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY. - Support for the Iris video codec. Written with inputs from : Rakesh Kota - Regulators. Nirmesh Kumar Singh - GPIO expander. Viken Dadhaniya - GPI/QUP. Mohd Ayaan Anwar - Ethernet. Monish Chunara - EEPROM. Vikash Garodia - Iris Video codec. Swati Agarwal - USB. Signed-off-by: Umang Chheda Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/monaco-evk.dts | 449 ++++++++++++++++++++++++ 2 files changed, 450 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 0a7c308dec36..0e4e0e0b833b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts new file mode 100644 index 000000000000..93e9e5322a39 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "qcs8300.dtsi" +#include "qcs8300-pmics.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Monaco EVK"; + compatible =3D "qcom,monaco-evk", "qcom,qcs8300"; + + aliases { + ethernet0 =3D ðernet0; + i2c1 =3D &i2c1; + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_s5c: smps5 { + regulator-name =3D "vreg_s5c"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <512000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +ðernet0 { + phy-mode =3D "2500base-x"; + phy-handle =3D <&hsgmii_phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + nvmem-cells =3D <&mac_addr0>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible =3D "ethernet-phy-id004d.d101"; + reg =3D <0x1c>; + reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&i2c1 { + pinctrl-0 =3D <&qup_i2c1_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + eeprom0: eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr0: mac-addr@0 { + reg =3D <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 =3D <&qup_i2c15_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + expander0: gpio@38 { + compatible =3D "ti,tca9538"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander1: gpio@39 { + compatible =3D "ti,tca9538"; + reg =3D <0x39>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander2: gpio@3a { + compatible =3D "ti,tca9538"; + reg =3D <0x3a>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander3: gpio@3b { + compatible =3D "ti,tca9538"; + reg =3D <0x3b>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander4: gpio@3c { + compatible =3D "ti,tca9538"; + reg =3D <0x3c>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander5: gpio@3d { + compatible =3D "ti,tca9538"; + reg =3D <0x3d>; + #gpio-cells =3D <2>; + gpio-controller; + }; + + expander6: gpio@3e { + compatible =3D "ti,tca9538"; + reg =3D <0x3e>; + #gpio-cells =3D <2>; + gpio-controller; + }; +}; + +&iris { + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs8300/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs8300/cdsp0.mbn"; + + status =3D "okay"; +}; + +&remoteproc_gpdsp { + firmware-name =3D "qcom/qcs8300/gpdsp0.mbn"; + + status =3D "okay"; +}; + +&serdes0 { + phy-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio5"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio6"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + qup_i2c1_default: qup-i2c1-state { + pins =3D "gpio19", "gpio20"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c15_default: qup-i2c15-state { + pins =3D "gpio91", "gpio92"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l8a>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l4c>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; 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charset="utf-8" From: Mohammad Rafi Shaik Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Umang Chheda Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 5edb137d1471..8ae843567ea4 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -2427,6 +2428,45 @@ compute-cb@5 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; 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charset="utf-8" From: Mohammad Rafi Shaik Add the sound card for monaco-evk board and verified playback functionality using the max98357a I2S speaker amplifier and I2S microphones. The max98357a speaker amplifier is connected via High-Speed MI2S HS0 interface, while the microphones utilize the Secondary MI2S interface and also enable required pin controller gpios for audio. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 52 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 ++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts index 93e9e5322a39..f3c5d363921e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "qcs8300.dtsi" @@ -24,6 +25,57 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + dmic: audio-codec-0 { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + num-channels =3D <1>; + }; + + max98357a: audio-codec-1 { + compatible =3D "maxim,max98357a"; + #sound-dai-cells =3D <0>; + }; + + sound { + compatible =3D "qcom,qcs8275-sndcard"; + model =3D "MONACO-EVK"; + + pinctrl-0 =3D <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names =3D "default"; + + hs0-mi2s-playback-dai-link { + link-name =3D "HS0 MI2S Playback"; + + codec { + sound-dai =3D <&max98357a>; + }; + + cpu { + sound-dai =3D <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name =3D "Secondary MI2S Capture"; + + codec { + sound-dai =3D <&dmic>; + }; + + cpu { + sound-dai =3D <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; }; &apps_rsc { diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 8ae843567ea4..8afd77a2d737 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4804,6 +4804,43 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; + hs0_mi2s_active: hs0-mi2s-active-state { + pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; + function =3D "hs0_mi2s"; + drive-strength =3D <8>; + bias-disable; + }; + + mi2s1_active: mi2s1-active-state { + data0-pins { + pins =3D "gpio100"; + function =3D "mi2s1_data0"; + drive-strength =3D <8>; + bias-disable; + }; + + data1-pins { + pins =3D "gpio101"; + function =3D "mi2s1_data1"; + drive-strength =3D <8>; + bias-disable; + }; + + sclk-pins { + pins =3D "gpio98"; + function =3D "mi2s1_sck"; + drive-strength =3D <8>; + bias-disable; + }; + + ws-pins { + pins =3D "gpio99"; + function =3D "mi2s1_ws"; + drive-strength =3D <8>; + bias-disable; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins =3D "gpio17", "gpio18"; function =3D "qup0_se0"; -- 2.34.1