From nobody Mon Feb 9 16:33:31 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F9112701B1; Fri, 5 Sep 2025 19:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; cv=none; b=CXvi1KWyJ0HLOkSenfUij9bMPnQj80igrNhDOZs041ciDt0CYdlYL9asdGwm1+Q5aKwKnsACAT0nGc0dG+EMQn7zLDVfo3UeP0T+xRRD3rnr6/167oTyKqDP1WbhkyNqxhvVKzuZJue9/wKq9XAX54slP/hh3vA/9iLH4ztQGdc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; c=relaxed/simple; bh=AVRbNW2CgbMWrkL6q3L2671gszWlJaQsGzy3skcxO74=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o62iRYzjA6n81fRtO9PvXJza10tdWJtX/TNu13VDE48FBSxVgx1XVNd0rSoozP2ix2PuFermV2iUxRksEaTUz5rM5fL3ZAlumEy2RKquZtxlSVmJvBjZ1EMtZEacXI+rNejZS30cEf60cU86bOg0GVBBn397NKNyrZjDiBMtqOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nm7ub6uB; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nm7ub6uB" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 585J0JlP3816516; Fri, 5 Sep 2025 14:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757098819; bh=ZsBm3TsTGQcRsYf4DJFibM8wtjviwVdubah3mMXEB/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nm7ub6uB6E5rn3EvPTF+vGFGV7lYaUq9knLIN+eTuHKFJZ776doT55G+JmN3yA7zA nrxZnwMrZPyAEZstLdS+y19vbN7YSZWZVHfc4c4wvsg0J2Q3XmMOOmCjOkDLL6TN8G QnCwXcHd7DtdLhWyWXQbL8WCohlxEVeJMGPwyg78= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 585J0Jsx1113635 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 14:00:19 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 14:00:18 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 14:00:18 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 585J09kP887531; Fri, 5 Sep 2025 14:00:14 -0500 From: Santhosh Kumar K To: , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH v2 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Date: Sat, 6 Sep 2025 00:29:55 +0530 Message-ID: <20250905185958.3575037-2-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905185958.3575037-1-s-k6@ti.com> References: <20250905185958.3575037-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 9bf823348cd3..eaf9a0f522d5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -764,6 +764,7 @@ static int cqspi_indirect_read_execute(struct cqspi_fla= sh_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ =20 while (remaining > 0) { if (use_irq && @@ -1090,6 +1091,8 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ + /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of --=20 2.34.1