From nobody Wed Sep 10 05:39:07 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F9112701B1; Fri, 5 Sep 2025 19:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; cv=none; b=CXvi1KWyJ0HLOkSenfUij9bMPnQj80igrNhDOZs041ciDt0CYdlYL9asdGwm1+Q5aKwKnsACAT0nGc0dG+EMQn7zLDVfo3UeP0T+xRRD3rnr6/167oTyKqDP1WbhkyNqxhvVKzuZJue9/wKq9XAX54slP/hh3vA/9iLH4ztQGdc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; c=relaxed/simple; bh=AVRbNW2CgbMWrkL6q3L2671gszWlJaQsGzy3skcxO74=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o62iRYzjA6n81fRtO9PvXJza10tdWJtX/TNu13VDE48FBSxVgx1XVNd0rSoozP2ix2PuFermV2iUxRksEaTUz5rM5fL3ZAlumEy2RKquZtxlSVmJvBjZ1EMtZEacXI+rNejZS30cEf60cU86bOg0GVBBn397NKNyrZjDiBMtqOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nm7ub6uB; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nm7ub6uB" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 585J0JlP3816516; Fri, 5 Sep 2025 14:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757098819; bh=ZsBm3TsTGQcRsYf4DJFibM8wtjviwVdubah3mMXEB/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nm7ub6uB6E5rn3EvPTF+vGFGV7lYaUq9knLIN+eTuHKFJZ776doT55G+JmN3yA7zA nrxZnwMrZPyAEZstLdS+y19vbN7YSZWZVHfc4c4wvsg0J2Q3XmMOOmCjOkDLL6TN8G QnCwXcHd7DtdLhWyWXQbL8WCohlxEVeJMGPwyg78= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 585J0Jsx1113635 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 14:00:19 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 14:00:18 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 14:00:18 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 585J09kP887531; Fri, 5 Sep 2025 14:00:14 -0500 From: Santhosh Kumar K To: , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH v2 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Date: Sat, 6 Sep 2025 00:29:55 +0530 Message-ID: <20250905185958.3575037-2-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905185958.3575037-1-s-k6@ti.com> References: <20250905185958.3575037-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 9bf823348cd3..eaf9a0f522d5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -764,6 +764,7 @@ static int cqspi_indirect_read_execute(struct cqspi_fla= sh_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ =20 while (remaining > 0) { if (use_irq && @@ -1090,6 +1091,8 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ + /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of --=20 2.34.1 From nobody Wed Sep 10 05:39:07 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C165326FA5E; Fri, 5 Sep 2025 19:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; cv=none; b=b6rKlQGocsKU0Mu4/vb+VTxnhftBb2Mg0gnO0Qdp6NMl17CKmjnade3rFjLDEdglq7GZ+hI5x+2h5+vPoJbV2RIH+G/KQ9H/mAK+KAlqVq9jBOo4I/y2GBHnuXglYnykq3AHi9zoUoCPzigsb5Qj6kjET0DGZecJFBqIquA++Mk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; c=relaxed/simple; bh=j4VflqOu9YM6FVcu8x38R6Ar4Y2F7g3tKkfvruWPGVQ=; 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Fri, 5 Sep 2025 14:00:23 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 585J09kQ887531; Fri, 5 Sep 2025 14:00:19 -0500 From: Santhosh Kumar K To: , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH v2 2/4] spi: cadence-quadspi: Flush posted register writes before DAC access Date: Sat, 6 Sep 2025 00:29:56 +0530 Message-ID: <20250905185958.3575037-3-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905185958.3575037-1-s-k6@ti.com> References: <20250905185958.3575037-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index eaf9a0f522d5..447a32a08a93 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -719,6 +719,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f= _pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 @@ -1063,6 +1064,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata= *f_pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 --=20 2.34.1 From nobody Wed Sep 10 05:39:07 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3BF2271458; Fri, 5 Sep 2025 19:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; cv=none; b=NUaVlWQtUbw8txUsoP8/osjGjG3xslbRRoQGHjzkM3MVKZqIReRrBF68nGrt33sTOEfy1WZrGaDP6YNClRwPb9h+f5nlVO/msM+eg1zYNLoeLESictWChNKjRnYN4NcyJPla6Hf2yuvfhbSssGjNKMzysYkiQylf1aMwW+Qr1Rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098847; c=relaxed/simple; bh=aKz5RerzJ0535jV+VWO23TW+VuegWL1IAuAoQFZ3CAA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kKdR4G/o8WOfv+DVoMLu4Jxu4GAS95UmPwAt+xX4edEscsJO32kygvX6Hdtf4cCSPeeJSxog8reBW2F49+cm8hYRARF6H2+418ZYIAQDrdrlnCXZH4qW5X2QpfR7D5DhZLufOwwZMGkpEGqYlRearoPe92BZBeBBx8R07OrxrM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wauCF+lg; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wauCF+lg" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 585J0S5O3385094; Fri, 5 Sep 2025 14:00:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757098828; bh=ja+VhWgnaezlhzQbc00MksF1Bt+kqV49jtmkDfOdRXY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wauCF+lgH8ETzGv6NT3pohG628irK5Us2c9tbZjkgZVvlrUhg/8LjEmiylElAqC7P Olx34A1vAwS3514a2xPn9xILAiQSiBcqIHLnnKJ7+Tg70FvTWygUFVTBROnBIuYD6w ecBhT8vNZ8zxoJVjS6thBLP/xJdluZH8h1hKjS08= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 585J0Sc6562025 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 14:00:28 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 14:00:27 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 14:00:27 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 585J09kR887531; Fri, 5 Sep 2025 14:00:23 -0500 From: Santhosh Kumar K To: , , , , , CC: , , , , , , , , Pratyush Yadav Subject: [PATCH v2 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash() Date: Sat, 6 Sep 2025 00:29:57 +0530 Message-ID: <20250905185958.3575037-4-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905185958.3575037-1-s-k6@ti.com> References: <20250905185958.3575037-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea The 'max_cs' stores the largest chip select number. It should only be updated when the current 'cs' is greater than existing 'max_cs'. So, fix the condition accordingly. Also, return failure if there are no flash device declared. Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-sele= ct") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav Reviewed-by: Th=C3=A9o Lebrun Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 447a32a08a93..6627a3059ea3 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1722,12 +1722,10 @@ static const struct spi_controller_mem_caps cqspi_m= em_caps =3D { =20 static int cqspi_setup_flash(struct cqspi_st *cqspi) { - unsigned int max_cs =3D cqspi->num_chipselect - 1; struct platform_device *pdev =3D cqspi->pdev; struct device *dev =3D &pdev->dev; struct cqspi_flash_pdata *f_pdata; - unsigned int cs; - int ret; + int ret, cs, max_cs =3D -1; =20 /* Get flash device data */ for_each_available_child_of_node_scoped(dev->of_node, np) { @@ -1740,10 +1738,10 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) if (cs >=3D cqspi->num_chipselect) { dev_err(dev, "Chip select %d out of range.\n", cs); return -EINVAL; - } else if (cs < max_cs) { - max_cs =3D cs; } =20 + max_cs =3D max_t(int, cs, max_cs); + f_pdata =3D &cqspi->f_pdata[cs]; f_pdata->cqspi =3D cqspi; f_pdata->cs =3D cs; @@ -1753,6 +1751,11 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return ret; } =20 + if (max_cs < 0) { + dev_err(dev, "No flash device declared\n"); + return -ENODEV; + } + cqspi->num_chipselect =3D max_cs + 1; return 0; } --=20 2.34.1 From nobody Wed Sep 10 05:39:07 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85BEE2750F4; Fri, 5 Sep 2025 19:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098849; cv=none; b=n//p8Osm8GKvIHb78gREPlliwkBFuHHCYomzfGwpuJQRcoN6Zivwsnl7rk4C/qFF7eEPnuHewYF7drMMX/etQlYXsFkcWko/3uLHBzyvewKc3mY83T9J9eQAd4oGV8wwHRxmT453jmFV/ey8DABU2zFM+bWnsdAYoNTLrJN98yU= ARC-Message-Signature: i=1; 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Fri, 5 Sep 2025 14:00:31 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 585J09kS887531; Fri, 5 Sep 2025 14:00:28 -0500 From: Santhosh Kumar K To: , , , , , CC: , , , , , , Subject: [PATCH v2 4/4] spi: cadence-quadspi: Use BIT() macros where possible Date: Sat, 6 Sep 2025 00:29:58 +0530 Message-ID: <20250905185958.3575037-5-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905185958.3575037-1-s-k6@ti.com> References: <20250905185958.3575037-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra Convert few open coded bit shifts to BIT() macro for better readability. No functional changes intended. Signed-off-by: Vignesh Raghavendra Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 6627a3059ea3..af253b86f1ab 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -335,7 +335,7 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi) { u32 reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); =20 - return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); + return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB); } =20 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) @@ -571,7 +571,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata = *f_pdata, reg |=3D (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) << CQSPI_REG_CMDCTRL_DUMMY_LSB; =20 - reg |=3D (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + reg |=3D BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB); =20 /* 0 means 1 byte. */ reg |=3D (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) @@ -579,7 +579,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata = *f_pdata, =20 /* setup ADDR BIT field */ if (op->addr.nbytes) { - reg |=3D (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + reg |=3D BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); reg |=3D ((op->addr.nbytes - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; @@ -646,7 +646,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata= *f_pdata, reg =3D opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; =20 if (op->addr.nbytes) { - reg |=3D (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + reg |=3D BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); reg |=3D ((op->addr.nbytes - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; @@ -655,7 +655,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata= *f_pdata, } =20 if (n_tx) { - reg |=3D (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); + reg |=3D BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB); reg |=3D ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; data =3D 0; @@ -1191,7 +1191,7 @@ static void cqspi_chipselect(struct cqspi_flash_pdata= *f_pdata) * CS2 to 4b'1011 * CS3 to 4b'0111 */ - chip_select =3D 0xF & ~(1 << chip_select); + chip_select =3D 0xF & ~BIT(chip_select); } =20 reg &=3D ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK @@ -1277,9 +1277,9 @@ static void cqspi_readdata_capture(struct cqspi_st *c= qspi, reg =3D readl(reg_base + CQSPI_REG_READCAPTURE); =20 if (bypass) - reg |=3D (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); + reg |=3D BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); else - reg &=3D ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); + reg &=3D ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); =20 reg &=3D ~(CQSPI_REG_READCAPTURE_DELAY_MASK << CQSPI_REG_READCAPTURE_DELAY_LSB); --=20 2.34.1