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(v133-18-108-210.vir.kagoya.net. [133.18.108.210]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4cd3095df7sm19940233a12.36.2025.09.05.11.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Sep 2025 11:13:06 -0700 (PDT) From: ChenMiao To: Stafford Horne Cc: Linux Kernel , Linux OpenRISC , chenmiao Subject: [PATCH v5 1/4] openrisc: Add text patching API support Date: Fri, 5 Sep 2025 18:12:55 +0000 Message-ID: <20250905181258.9430-2-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250905181258.9430-1-chenmiao.ku@gmail.com> References: <20250905181258.9430-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao Add text patching api's to use in subsequent jump_label implementation. We= use a new fixmap FIX_TEXT_POKE0 entry to temporarily override MMU mappings to a= llow read only text pages to be written to. Previously, __set_fix was marked with __init as it was only used during the EARLYCON stage. Now that TEXT_POKE mappings require post-init usage (e.g., FIX_TEXT_POKE0), keeping __init would cause runtime bugs whenset_fix= map accesses invalid memory. Thus, we remove the __init flag to ensure __set_fix remains valid beyond initialization. A new function patch_insn_write is exposed to allow single instruction patc= hing. Link: https://lore.kernel.org/openrisc/aJIC8o1WmVHol9RY@antec/T/#t Signed-off-by: chenmiao --- Changes in V4: - Fixed incorrect macro definitions and malformed comments. Changes in V3: - Removed the unimplemented and unsupported is_exit_text, added comments for the set_fixmap modification explaining why __init was removed, and added new comments for patch_insn_write. Changes in V2: - We modify the patch_insn_write(void *addr, const void *insn) API to patch_insn_write(void *addr, u32 insn), derectly support a single u32 instruction write to map memory. - Create a new file named insn-def.h to define the or1k insn macro size and more define in the future. Signed-off-by: chenmiao --- arch/openrisc/include/asm/Kbuild | 1 - arch/openrisc/include/asm/fixmap.h | 1 + arch/openrisc/include/asm/insn-def.h | 12 ++++ arch/openrisc/include/asm/text-patching.h | 13 ++++ arch/openrisc/kernel/Makefile | 1 + arch/openrisc/kernel/patching.c | 79 +++++++++++++++++++++++ arch/openrisc/mm/init.c | 6 +- 7 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 arch/openrisc/include/asm/insn-def.h create mode 100644 arch/openrisc/include/asm/text-patching.h create mode 100644 arch/openrisc/kernel/patching.c diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/K= build index 2b1a6b00cdac..cef49d60d74c 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -9,4 +9,3 @@ generic-y +=3D spinlock.h generic-y +=3D qrwlock_types.h generic-y +=3D qrwlock.h generic-y +=3D user.h -generic-y +=3D text-patching.h diff --git a/arch/openrisc/include/asm/fixmap.h b/arch/openrisc/include/asm= /fixmap.h index aaa6a26a3e92..74000215064d 100644 --- a/arch/openrisc/include/asm/fixmap.h +++ b/arch/openrisc/include/asm/fixmap.h @@ -28,6 +28,7 @@ =20 enum fixed_addresses { FIX_EARLYCON_MEM_BASE, + FIX_TEXT_POKE0, __end_of_fixed_addresses }; =20 diff --git a/arch/openrisc/include/asm/insn-def.h b/arch/openrisc/include/a= sm/insn-def.h new file mode 100644 index 000000000000..e28a9a9604fc --- /dev/null +++ b/arch/openrisc/include/asm/insn-def.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + */ + +#ifndef __ASM_OPENRISC_INSN_DEF_H +#define __ASM_OPENRISC_INSN_DEF_H + +/* or1k instructions are always 32 bits. */ +#define OPENRISC_INSN_SIZE 4 + +#endif /* __ASM_OPENRISC_INSN_DEF_H */ diff --git a/arch/openrisc/include/asm/text-patching.h b/arch/openrisc/incl= ude/asm/text-patching.h new file mode 100644 index 000000000000..d19098dac0cc --- /dev/null +++ b/arch/openrisc/include/asm/text-patching.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + */ + +#ifndef _ASM_OPENRISC_PATCHING_H +#define _ASM_OPENRISC_PATCHING_H + +#include + +int patch_insn_write(void *addr, u32 insn); + +#endif /* _ASM_OPENRISC_PATCHING_H */ diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index 58e6a1b525b7..f0957ce16d6b 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -13,5 +13,6 @@ obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o obj-$(CONFIG_MODULES) +=3D module.o obj-$(CONFIG_OF) +=3D prom.o +obj-y +=3D patching.o =20 clean: diff --git a/arch/openrisc/kernel/patching.c b/arch/openrisc/kernel/patchin= g.c new file mode 100644 index 000000000000..d186172beb33 --- /dev/null +++ b/arch/openrisc/kernel/patching.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2020 SiFive + * Copyright (C) 2025 Chen Miao + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static DEFINE_RAW_SPINLOCK(patch_lock); + +static __always_inline void *patch_map(void *addr, int fixmap) +{ + uintptr_t uaddr =3D (uintptr_t) addr; + phys_addr_t phys; + + if (core_kernel_text(uaddr)) { + phys =3D __pa_symbol(addr); + } else { + struct page *page =3D vmalloc_to_page(addr); + BUG_ON(!page); + phys =3D page_to_phys(page) + offset_in_page(addr); + } + + return (void *)set_fixmap_offset(fixmap, phys); +} + +static void patch_unmap(int fixmap) +{ + clear_fixmap(fixmap); +} + +static int __patch_insn_write(void *addr, u32 insn) +{ + void *waddr =3D addr; + unsigned long flags =3D 0; + int ret; + + raw_spin_lock_irqsave(&patch_lock, flags); + + waddr =3D patch_map(addr, FIX_TEXT_POKE0); + + ret =3D copy_to_kernel_nofault(waddr, &insn, OPENRISC_INSN_SIZE); + local_icache_range_inv((unsigned long)waddr, + (unsigned long)waddr + OPENRISC_INSN_SIZE); + + patch_unmap(FIX_TEXT_POKE0); + + raw_spin_unlock_irqrestore(&patch_lock, flags); + + return ret; +} + +/* + * patch_insn_write - Write a single instruction to a specified memory loc= ation + * This API provides a single-instruction patching, primarily used for run= time + * code modification. + * By the way, the insn size must be 4 bytes. + */ +int patch_insn_write(void *addr, u32 insn) +{ + u32 *tp =3D addr; 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[133.18.108.210]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4cd3095df7sm19940233a12.36.2025.09.05.11.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Sep 2025 11:13:09 -0700 (PDT) From: ChenMiao To: Stafford Horne Cc: Linux Kernel , Linux OpenRISC , chenmiao Subject: [PATCH v5 2/4] openrisc: Add R_OR1K_32_PCREL relocation type module support Date: Fri, 5 Sep 2025 18:12:56 +0000 Message-ID: <20250905181258.9430-3-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250905181258.9430-1-chenmiao.ku@gmail.com> References: <20250905181258.9430-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao To ensure the proper functioning of the jump_label test module, this patch adds support for the R_OR1K_32_PCREL relocation type for any modules. The implementation calculates the PC-relative offset by subtracting the instruction location from the target value and stores the result at the specified location. Signed-off-by: chenmiao --- arch/openrisc/kernel/module.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/openrisc/kernel/module.c b/arch/openrisc/kernel/module.c index c9ff4c4a0b29..4ac4fbaa827c 100644 --- a/arch/openrisc/kernel/module.c +++ b/arch/openrisc/kernel/module.c @@ -55,6 +55,10 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, value |=3D *location & 0xfc000000; *location =3D value; break; + case R_OR1K_32_PCREL: + value -=3D (uint32_t)location; + *location =3D value; + break; case R_OR1K_AHI16: /* Adjust the operand to match with a signed LO16. */ value +=3D 0x8000; --=20 2.45.2 From nobody Sun Feb 8 00:59:58 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1127A305948; Fri, 5 Sep 2025 18:13:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757095994; cv=none; b=coakvlPWsHap2yMWwwhnGuAyerl1s2ct14zGHEKxkcY+kzHFGWsxhvTSXXPHnr/+4oRxU4l/oe8n5Op3fwybt+KveoUald9LpoEYYWiuWTOZJnlZ5Aho5U128IFqGgy/NWYtQOLkT9xEG19wE12MLvvq469F1dt5qkN/pX3ikmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757095994; c=relaxed/simple; bh=AIZqPgluwqpePOPT3MvDMxrsH2xlD8v9qId4APJeL3o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eu6SOnGGPjhjWh7TV66F4KiCaVsHszo7iKPyzFs9JKKD48nxeMIdpdMXmLeQhFwK3VjUPuC+UXp9+KqdGbr9h1IhvX7ITfXmEsVtfDReywyuwt7xTKa3SVUHR87wtkxMF+8KxEnXZaYkeJ/MeF3faVTWvnt7iEteTtaIsdIx0zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=N5bQNIkM; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N5bQNIkM" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-24b1622788dso17765115ad.2; Fri, 05 Sep 2025 11:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757095992; x=1757700792; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rRBZvA6tPDIGNoeLji756p9DxOWg2MHueudkSvigYAI=; b=N5bQNIkMWzxLQl6fHT88aW7XG6ZiNQO2lt4/RnQxflaUcBSGJZ6L425Tm3oT/Ya0uq G+He5iN8gqJSdWKvnpkG4NjpT3V8Ri+b6OxVvtrzoMoYpDW1CvZVYxouhlesDN34arJb D6CvS9+v8bLk8rmpcFseLIACiqkOR4Q1ERi89tbC5mUeftPO4bDBH+flvqBP3YM+3AIz /LiWfvyLrakUnYprop4QpzrcJUZU1SMKDYkgdx4D2XyHiNl/Hhsda/G2FYi0GZ0sY7mQ wQ+tDaYiXN1TnBYjPuym2bjBP2rw5PPH4KHtFj7u0UWk+kdC0nJvq9B2pXX/k0vAxTo5 QZ4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757095992; x=1757700792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rRBZvA6tPDIGNoeLji756p9DxOWg2MHueudkSvigYAI=; b=b+lQfgPV9e+jGR3G6SuT4yxS+DO9bG3pCxb+8QXCuBRiwL9iFwb2WrFPmf4Wz0XafV G8zNqD45CuRWWkT2GjCuN1WSWkLuyJNFI8cCpTx7CO1WqBUO9H0HfKmQFpm7thoxcWDL c31tf4UkSp0Nojwpt8z3XfXQvwFeInHEK4KNh3rRuSUu/cIvbnLQimkcp1BevYdbFCU7 fdJMpJZxFGk9pI9xyXySYO2NdAELVvUw4uQieytr7xWzfn1I1mIMiHK26ntt4ztqoxy+ dKSIZuRTj+EjseQPlD/KmzUgaL0PKoqUN/jraOG7YTZADGWKTiPTwnm0otecGpeflKb4 gvzQ== X-Forwarded-Encrypted: i=1; AJvYcCV581v5IoOdH+e7f0zUa9NCCE4UXWqE/Wh3WPo5O0OWfMcY69QLy1G0/j+79P8lTrC5LcY1gsL2C9xkt8dVOg==@vger.kernel.org X-Gm-Message-State: AOJu0YwzMyAY2BCU79/Jxo+lS0lLZkC/3FZkl6/0wjJv80BTyKIVQYRB wDVudYvefwXxbCFJk1tt27LoxHbAfcwk+Rh/4FxcXMQe2ouFIWPRoRxyz59KKpfGZB7wQw== X-Gm-Gg: ASbGncu/8VDg18cGoXkb8AQqnLTuSwytd+lLy/9Ceta6z/ITfjG/ptiB9rLyht7lCcB 932dXwqng+9u3SY1a/R0EHz6dLOPoCTMLG2I/54tFs451+j7eZTgh/K3strBVwJO7NU+MggWlo8 umEUoxImPqlHLdprylhVOAnw8lR9QEwtPg/ofMRSmoJ/S8sDKa/cPh063IOnH5MYYv1sF2H4rKQ 2ubTlVBUTjYyPv23FidxZftVDr3v0PVsxC7NSRD6/7LiQ4hlwckuGUokI8z2Uzkr/9uwPLIkMSE +tUl9D5Dztr9/zCUBhMyl6KbJTmj6UfMrxaDjzsKmpfIxscX0zBT0C+LkSEURGV0r/PuSaG3Ox5 iBLthgz5/92mSj3Vw7W0cQ/8Gp5MkD67jRKYlvEqRQoReNycXwb4= X-Google-Smtp-Source: AGHT+IFjFH7blnOboZp2FXiEo1b7F5VKD3m4qEugDhybRU7cWg5AGM7Fx0kkNVzkZl/GIUrT+oKxYQ== X-Received: by 2002:a17:903:1d1:b0:24d:4a96:7b30 with SMTP id d9443c01a7336-24d4ab50264mr50522365ad.35.1757095992296; Fri, 05 Sep 2025 11:13:12 -0700 (PDT) Received: from nyaos.. (v133-18-108-210.vir.kagoya.net. [133.18.108.210]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4cd3095df7sm19940233a12.36.2025.09.05.11.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Sep 2025 11:13:11 -0700 (PDT) From: ChenMiao To: Stafford Horne Cc: Linux Kernel , Linux OpenRISC , chenmiao Subject: [PATCH v5 3/4] openrisc: Regenerate defconfigs. Date: Fri, 5 Sep 2025 18:12:57 +0000 Message-ID: <20250905181258.9430-4-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250905181258.9430-1-chenmiao.ku@gmail.com> References: <20250905181258.9430-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao Regenerating defconfigs allows subsequent changes to the configs to be related only to the corresponding modifications, without mixing changes from other configs. Signed-off-by: chenmiao --- arch/openrisc/configs/or1ksim_defconfig | 18 ++++++------------ arch/openrisc/configs/virt_defconfig | 1 - 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/openrisc/configs/or1ksim_defconfig b/arch/openrisc/config= s/or1ksim_defconfig index 59fe33cefba2..58e27d8fdb4e 100644 --- a/arch/openrisc/configs/or1ksim_defconfig +++ b/arch/openrisc/configs/or1ksim_defconfig @@ -3,26 +3,22 @@ CONFIG_LOG_BUF_SHIFT=3D14 CONFIG_BLK_DEV_INITRD=3Dy # CONFIG_RD_GZIP is not set CONFIG_EXPERT=3Dy -# CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLUB=3Dy -CONFIG_SLUB_TINY=3Dy -CONFIG_MODULES=3Dy -# CONFIG_BLOCK is not set +# CONFIG_KALLSYMS is not set CONFIG_BUILTIN_DTB_NAME=3D"or1ksim" CONFIG_HZ_100=3Dy +CONFIG_MODULES=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set CONFIG_NET=3Dy CONFIG_PACKET=3Dy CONFIG_UNIX=3Dy CONFIG_INET=3Dy -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set CONFIG_TCP_CONG_ADVANCED=3Dy # CONFIG_TCP_CONG_BIC is not set @@ -35,7 +31,6 @@ CONFIG_DEVTMPFS=3Dy CONFIG_DEVTMPFS_MOUNT=3Dy # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set -CONFIG_PROC_DEVICETREE=3Dy CONFIG_NETDEVICES=3Dy CONFIG_ETHOC=3Dy CONFIG_MICREL_PHY=3Dy @@ -53,4 +48,3 @@ CONFIG_SERIAL_OF_PLATFORM=3Dy # CONFIG_DNOTIFY is not set CONFIG_TMPFS=3Dy CONFIG_NFS_FS=3Dy -# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/openrisc/configs/virt_defconfig b/arch/openrisc/configs/v= irt_defconfig index c1b69166c500..8a581e932766 100644 --- a/arch/openrisc/configs/virt_defconfig +++ b/arch/openrisc/configs/virt_defconfig @@ -55,7 +55,6 @@ CONFIG_DRM=3Dy # CONFIG_DRM_FBDEV_EMULATION is not set CONFIG_DRM_VIRTIO_GPU=3Dy CONFIG_FB=3Dy -CONFIG_FIRMWARE_EDID=3Dy CONFIG_FRAMEBUFFER_CONSOLE=3Dy CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=3Dy CONFIG_LOGO=3Dy --=20 2.45.2 From nobody Sun Feb 8 00:59:58 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EC730596A; 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(v133-18-108-210.vir.kagoya.net. [133.18.108.210]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4cd3095df7sm19940233a12.36.2025.09.05.11.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Sep 2025 11:13:14 -0700 (PDT) From: ChenMiao To: Stafford Horne Cc: Linux Kernel , Linux OpenRISC , chenmiao Subject: [PATCH v5 4/4] openrisc: Add jump label support Date: Fri, 5 Sep 2025 18:12:58 +0000 Message-ID: <20250905181258.9430-5-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250905181258.9430-1-chenmiao.ku@gmail.com> References: <20250905181258.9430-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao Supported a complete jump_label implementation based on the ARM64 and RV64 version and add the CONFIG_JUMP_LABEL=3Dy to the defconfig. Testing was conducted using a dedicated test module jump-label-test, provided in the link below. For detailed steps, please refer to the README also at the provided link. Link: https://github.com/ChenMiaoi/GSoC-2025-Final-Report/tree/main/tests/j= ump-label-test Test Environment: - Hardware: QEMU emulated OR1K - Kernel Version: 6.17.0-rc3-dirty - Configs: CONFIG_MODULES=3Dy,CONFIG_MODULE_UNLOAD=3Dy - Toolchain: or1k-none-linux-musl-gcc 15.1.0 Test Results: $ insmod jump_label_test.ko [ 32.590000] Jump label performance test module loaded [ 35.250000] Normal branch time: 1241327150 ns (124 ns per iteration) [ 35.250000] Jump label (false) time: 706422700 ns (70 ns per iteration) [ 35.250000] Jump label (true) time: 708913450 ns (70 ns per iteration) $ rmmod jump_label_test.ko [ 72.210000] Jump label test module unloaded The results show approximately 43% improvement in branch performance when using jump labels compared to traditional branches. Link: https://lore.kernel.org/openrisc/aLsZ9S3X0OpKy1RM@antec/T/#u Signed-off-by: chenmiao --- Changes in V5: - Removed some unnecessary curly braces and streamlined parts of the code. Changes in V4: - Add appropriate comments. Changes in V3: - Ensure the two defconfig using the make savedefconfig. - modify the __ASSEMBLY__ to __ASSEMBLER__, modify the __ASM_JUMP_LABEL_H to __ASM_OPENRISC_JUMP_LABEL_H and remove invalid comment. Changes in V2: - using the patch_insn_write(void *addr, u32 insn) not the const void *insn. - add new macro OPENRISC_INSN_NOP in insn-def.h to use. Signed-off-by: chenmiao --- .../core/jump-labels/arch-support.txt | 2 +- arch/openrisc/Kconfig | 2 + arch/openrisc/configs/or1ksim_defconfig | 1 + arch/openrisc/configs/virt_defconfig | 1 + arch/openrisc/include/asm/insn-def.h | 3 + arch/openrisc/include/asm/jump_label.h | 72 +++++++++++++++++++ arch/openrisc/kernel/Makefile | 1 + arch/openrisc/kernel/jump_label.c | 51 +++++++++++++ arch/openrisc/kernel/setup.c | 2 + 9 files changed, 134 insertions(+), 1 deletion(-) create mode 100644 arch/openrisc/include/asm/jump_label.h create mode 100644 arch/openrisc/kernel/jump_label.c diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Doc= umentation/features/core/jump-labels/arch-support.txt index ccada815569f..683de7c15058 100644 --- a/Documentation/features/core/jump-labels/arch-support.txt +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -17,7 +17,7 @@ | microblaze: | TODO | | mips: | ok | | nios2: | TODO | - | openrisc: | TODO | + | openrisc: | ok | | parisc: | ok | | powerpc: | ok | | riscv: | ok | diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index b38fee299bc4..9156635dd264 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -24,6 +24,8 @@ config OPENRISC select GENERIC_PCI_IOMAP select GENERIC_IOREMAP select GENERIC_CPU_DEVICES + select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_PCI select HAVE_UID16 select HAVE_PAGE_SIZE_8KB diff --git a/arch/openrisc/configs/or1ksim_defconfig b/arch/openrisc/config= s/or1ksim_defconfig index 58e27d8fdb4e..769705ac24d5 100644 --- a/arch/openrisc/configs/or1ksim_defconfig +++ b/arch/openrisc/configs/or1ksim_defconfig @@ -10,6 +10,7 @@ CONFIG_EXPERT=3Dy # CONFIG_KALLSYMS is not set CONFIG_BUILTIN_DTB_NAME=3D"or1ksim" CONFIG_HZ_100=3Dy +CONFIG_JUMP_LABEL=3Dy CONFIG_MODULES=3Dy # CONFIG_BLOCK is not set CONFIG_SLUB_TINY=3Dy diff --git a/arch/openrisc/configs/virt_defconfig b/arch/openrisc/configs/v= irt_defconfig index 8a581e932766..a93a3e1e4f87 100644 --- a/arch/openrisc/configs/virt_defconfig +++ b/arch/openrisc/configs/virt_defconfig @@ -12,6 +12,7 @@ CONFIG_NR_CPUS=3D8 CONFIG_SMP=3Dy CONFIG_HZ_100=3Dy # CONFIG_OPENRISC_NO_SPR_SR_DSX is not set +CONFIG_JUMP_LABEL=3Dy # CONFIG_COMPAT_BRK is not set CONFIG_NET=3Dy CONFIG_PACKET=3Dy diff --git a/arch/openrisc/include/asm/insn-def.h b/arch/openrisc/include/a= sm/insn-def.h index e28a9a9604fc..1e0c028a5b95 100644 --- a/arch/openrisc/include/asm/insn-def.h +++ b/arch/openrisc/include/asm/insn-def.h @@ -9,4 +9,7 @@ /* or1k instructions are always 32 bits. */ #define OPENRISC_INSN_SIZE 4 =20 +/* or1k nop instruction code */ +#define OPENRISC_INSN_NOP 0x15000000U + #endif /* __ASM_OPENRISC_INSN_DEF_H */ diff --git a/arch/openrisc/include/asm/jump_label.h b/arch/openrisc/include= /asm/jump_label.h new file mode 100644 index 000000000000..3ec0f4e19f9c --- /dev/null +++ b/arch/openrisc/include/asm/jump_label.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + * + * Based on arch/arm/include/asm/jump_label.h + */ +#ifndef __ASM_OPENRISC_JUMP_LABEL_H +#define __ASM_OPENRISC_JUMP_LABEL_H + +#ifndef __ASSEMBLER__ + +#include +#include + +#define HAVE_JUMP_LABEL_BATCH + +#define JUMP_LABEL_NOP_SIZE OPENRISC_INSN_SIZE + +/** + * JUMP_TABLE_ENTRY - Create a jump table entry + * @key: Jump key identifier (typically a symbol address) + * @label: Target label address + * + * This macro creates a jump table entry in the dedicated kernel section (= __jump_table). + * Each entry contains the following information: + * Offset from current instruction to jump instruction (1b - .) + * Offset from current instruction to target label (label - .) + * Offset from current instruction to key identifier (key - .) + */ +#define JUMP_TABLE_ENTRY(key, label) \ + ".pushsection __jump_table, \"aw\" \n\t" \ + ".align 4 \n\t" \ + ".long 1b - ., " label " - . \n\t" \ + ".long " key " - . \n\t" \ + ".popsection \n\t" + +#define ARCH_STATIC_BRANCH_ASM(key, label) \ + ".align 4 \n\t" \ + "1: l.nop \n\t" \ + " l.nop \n\t" \ + JUMP_TABLE_ENTRY(key, label) + +static __always_inline bool arch_static_branch(struct static_key *const ke= y, + const bool branch) +{ + asm goto (ARCH_STATIC_BRANCH_ASM("%0", "%l[l_yes]") + ::"i"(&((char *)key)[branch])::l_yes); + + return false; +l_yes: + return true; +} + +#define ARCH_STATIC_BRANCH_JUMP_ASM(key, label) \ + ".align 4 \n\t" \ + "1: l.j " label " \n\t" \ + " l.nop \n\t" \ + JUMP_TABLE_ENTRY(key, label) + +static __always_inline bool +arch_static_branch_jump(struct static_key *const key, const bool branch) +{ + asm goto (ARCH_STATIC_BRANCH_JUMP_ASM("%0", "%l[l_yes]") + ::"i"(&((char *)key)[branch])::l_yes); + + return false; +l_yes: + return true; +} + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_OPENRISC_JUMP_LABEL_H */ diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index f0957ce16d6b..19e0eb94f2eb 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -9,6 +9,7 @@ obj-y :=3D head.o setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o unwinder.o cacheinfo.o =20 +obj-$(CONFIG_JUMP_LABEL) +=3D jump_label.o obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o obj-$(CONFIG_MODULES) +=3D module.o diff --git a/arch/openrisc/kernel/jump_label.c b/arch/openrisc/kernel/jump_= label.c new file mode 100644 index 000000000000..ab7137c23b46 --- /dev/null +++ b/arch/openrisc/kernel/jump_label.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Chen Miao + * + * Based on arch/arm/kernel/jump_label.c + */ +#include +#include +#include +#include +#include +#include + +bool arch_jump_label_transform_queue(struct jump_entry *entry, + enum jump_label_type type) +{ + void *addr =3D (void *)jump_entry_code(entry); + u32 insn; + + if (type =3D=3D JUMP_LABEL_JMP) { + long offset; + + offset =3D jump_entry_target(entry) - jump_entry_code(entry); + /* + * The actual maximum range of the l.j instruction's offset is -134,217,= 728 + * ~ 134,217,724 (sign 26-bit imm). + * For the original jump range, we need to right-shift N by 2 to obtain = the + * instruction's offset. + */ + WARN_ON_ONCE(offset < -134217728 || offset > 134217724); + + /* 26bit imm mask */ + offset =3D (offset >> 2) & 0x03ffffff; + + insn =3D offset; + } else { + insn =3D OPENRISC_INSN_NOP; + } + + if (early_boot_irqs_disabled) + copy_to_kernel_nofault(addr, &insn, sizeof(insn)); + else + patch_insn_write(addr, insn); + + return true; +} + +void arch_jump_label_transform_apply(void) +{ + kick_all_cpus_sync(); +} diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index a9fb9cc6779e..000a9cc10e6f 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -249,6 +249,8 @@ void __init setup_arch(char **cmdline_p) initrd_below_start_ok =3D 1; } #endif + /* perform jump_table sorting before paging_init locks down read only mem= ory */ + jump_label_init(); =20 /* paging_init() sets up the MMU and marks all pages as reserved */ paging_init(); --=20 2.45.2