From nobody Wed Sep 10 11:34:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 786CB30B52E for ; Fri, 5 Sep 2025 15:45:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087146; cv=none; b=qZDAxjduZDO98HeTuh1S4dkSUezCh3KTgi4K6/2NTZPKzRNVUx9Ba4WgGCmiJec+i6gbYQ14RYjIn5ZK6Cn1lxvfHjH1wS4hu8NkNNfblA57tm1r1quLn0UZqeoNJDua95Q7Fm9VObXACre/qlsAJCL1jIGA3T6Kq8eFDavSQ8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087146; c=relaxed/simple; bh=jvgC1iNP5UlHhNzZehsvvrerAc25rtsBKfpjRvRjeYk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kmIz+TQF+aRIRcFX5AYPwZ/yzdv2KT1wekjDdpk9Y52zO4kivnnKJbi3AGTCBsguwctHBGu+JtNACIkCJFj+o3RYjqi/XuQVDs/P0gxzrpfIJ7x6f5ICw8PvAxoOPE9E2u3lZwWF9SVH6wfwqPJ9a8NmITnicybUoiFWK1+VUAg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HRiUiL3N; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HRiUiL3N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757087144; x=1788623144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jvgC1iNP5UlHhNzZehsvvrerAc25rtsBKfpjRvRjeYk=; b=HRiUiL3NQwju/YHYXI0HRvyULBclfjZfH3xQfg7VEroaoKkkAjnYGOZ/ 9vZvFBKUS7WhwG/xqAUGc44/EgcFC7OTYqgjEUvfvDGUfq1hNHG5B5cZH hBq5yQLYmF9PdC+fpE0tOiDOnVvN9x//dT+/P4EZYoxIjK0QSYp+0BA0U RtdHt/34M6dAJsmrJLXrEN1ais1t++g20H9Q3mnJAfSURtZF7YNzCWpGV FdrA0Ksa/YsJ77905+0NSjwejNk5Y1VEheQFjY3zd3Bro0bLRQvECDMAN Z1Ox+NCBzmRCA0J4M/z/eXVuo5NqZkx5eaV6Ha2Jdf8YfljUZiekuDbQy w==; X-CSE-ConnectionGUID: 2i2ptNv5TVm1Mzd6Vgb0Mw== X-CSE-MsgGUID: cavRhnVGT8yT2LtqxbEY+w== X-IronPort-AV: E=McAfee;i="6800,10657,11544"; a="70144685" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144685" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:44 -0700 X-CSE-ConnectionGUID: rEmIIMD1S5OptsM49Ow9JA== X-CSE-MsgGUID: mczdDwKtTg6kgWP2jeezXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071930" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:41 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 8/9] drm/xe/xe_late_bind_fw: Introduce debug fs node to disable late binding Date: Fri, 5 Sep 2025 21:19:52 +0530 Message-Id: <20250905154953.3974335-9-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a debug filesystem node to disable late binding fw reload during the system or runtime resume. This is intended for situations where the late binding fw needs to be loaded from user mode, perticularly for validation purpose. Note that xe kmd doesn't participate in late binding flow from user space. Binary loaded from the userspace will be lost upon entering to D3 cold hence user space app need to handle this situation. v2: - s/(uval =3D=3D 1) ? true : false/!!uval/ (Daniele) v3: - Refine the commit message (Daniele) Acked-by: Rodrigo Vivi Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_debugfs.c | 41 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 3 ++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 2 ++ 3 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugf= s.c index 4b71570529a6..c68e8d73802f 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -330,6 +330,44 @@ static const struct file_operations atomic_svm_timesli= ce_ms_fops =3D { .write =3D atomic_svm_timeslice_ms_set, }; =20 +static ssize_t disable_late_binding_show(struct file *f, char __user *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + char buf[32]; + int len; + + len =3D scnprintf(buf, sizeof(buf), "%d\n", late_bind->disable); + + return simple_read_from_buffer(ubuf, size, pos, buf, len); +} + +static ssize_t disable_late_binding_set(struct file *f, const char __user = *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + u32 uval; + ssize_t ret; + + ret =3D kstrtouint_from_user(ubuf, size, sizeof(uval), &uval); + if (ret) + return ret; + + if (uval > 1) + return -EINVAL; + + late_bind->disable =3D !!uval; + return size; +} + +static const struct file_operations disable_late_binding_fops =3D { + .owner =3D THIS_MODULE, + .read =3D disable_late_binding_show, + .write =3D disable_late_binding_set, +}; + void xe_debugfs_register(struct xe_device *xe) { struct ttm_device *bdev =3D &xe->ttm; @@ -363,6 +401,9 @@ void xe_debugfs_register(struct xe_device *xe) debugfs_create_file("atomic_svm_timeslice_ms", 0600, root, xe, &atomic_svm_timeslice_ms_fops); =20 + debugfs_create_file("disable_late_binding", 0600, root, xe, + &disable_late_binding_fops); + for (mem_type =3D XE_PL_VRAM0; mem_type <=3D XE_PL_VRAM1; ++mem_type) { man =3D ttm_manager_type(bdev, mem_type); =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index d4d64677bf48..0f062008ca83 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -167,6 +167,9 @@ int xe_late_bind_fw_load(struct xe_late_bind *late_bind) if (!late_bind->component_added) return -ENODEV; =20 + if (late_bind->disable) + return 0; + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { lbfw =3D &late_bind->late_bind_fw[fw_id]; if (lbfw->payload) { diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 5c0574aff7b9..158dc1abe072 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -65,6 +65,8 @@ struct xe_late_bind { struct workqueue_struct *wq; /** @component_added: whether the component has been added */ bool component_added; + /** @disable: to block late binding reload during pm resume flow*/ + bool disable; }; =20 #endif --=20 2.34.1