From nobody Wed Sep 10 11:31:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6108E309EE7 for ; Fri, 5 Sep 2025 15:45:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087129; cv=none; b=Q54HErf5J3FY4cfoDeSbExlEPf7jfKaYTBTHxQzdtxtZA1amjGCvebhRWxID0rq6OPvBCsxZoTnIoySg/1K3p+IiTvQjx31x5RRCLflo+yUTWTrLs171nI8nSHr4uENBK8XubCNgx6VWOU1BfsoS76+wxLpQQbIuiP9pLL+r98k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087129; c=relaxed/simple; bh=8WE78F/JPlz6ComTAeBz7fTY/mwii6BcG1oApLkybEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=npXk51aZHoeIqJFZaX5LOmlJ03BVVYfXRm9Ls//TS389PuTSz8fsL84dsNLFpedYbTxqhaSDtH9Msjc0bZ8xRDLAqVqLl8qMGXFMBD7NQx8hYPM2+5mq1nleEhQ36LBX+RYcrdj/b9ruIK641L9+QMpmAwPSEwPl9UeHw7mvKu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=coFgP7jR; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="coFgP7jR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757087127; x=1788623127; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8WE78F/JPlz6ComTAeBz7fTY/mwii6BcG1oApLkybEU=; b=coFgP7jR777W/XYfHFAELWOaWCGXreVs82y47Hezu8kX3WTWw1Qr66mL n3axQP5g0DxFGyZsFvs590B1pVkbyKy8aYdMVFMAPlRKdMUn7pez8phdj DtjuhNwEQRf02h4b+vQt4qkl9fuMG8T6/f+8Kd6zexgv7jkbYztWN0xwF E7T/1SdvpNGzLtYN9BVJ9Z6tZ3Xj9wjCD/wGwt1DY1wdOXiRfQPNAAtjp 4L6v8t4HoPuwKfHRljBuohkGwscAQEs6FRCLMOwpxGXsGAm+HtQFxbvix 1GEDnEaAB+boiRXPaBlp3y8dDBM/eP8LnPlO9j7Bhv0fSBzUtH/HlzVRD Q==; X-CSE-ConnectionGUID: h0tvrDRLQGCuMy7BkHfBQA== X-CSE-MsgGUID: E3cZBxDrQRSeCJXqEiS/mA== X-IronPort-AV: E=McAfee;i="6800,10657,11544"; a="70144637" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144637" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:27 -0700 X-CSE-ConnectionGUID: hl8iSQDnTkm2TfjwqSiRWg== X-CSE-MsgGUID: RuFK0un2SGCF4Nrd863vsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071746" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:24 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 3/9] drm/xe/xe_late_bind_fw: Introduce xe_late_bind_fw Date: Fri, 5 Sep 2025 21:19:47 +0530 Message-Id: <20250905154953.3974335-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introduce xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) v4: - %s/I915_COMPONENT_LATE_BIND/INTEL_COMPONENT_LATE_BIND/ v6: - rebased v7: - rebased - In xe_late_bind_init, use drm_err when returning an error to stop the probe (Lucas) - Use imperative mode in commit message (Lucas) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 84 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 33 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 2 + drivers/gpu/drm/xe/xe_pci_types.h | 1 + 8 files changed, 147 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index d6bd139c5839..1b062005ac8d 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -84,6 +84,7 @@ xe-y +=3D xe_bb.o \ xe_hw_error.o \ xe_hw_fence.o \ xe_irq.o \ + xe_late_bind_fw.o \ xe_lrc.o \ xe_migrate.o \ xe_mmio.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 9e2952c9c06a..3fbae3e579d0 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -45,6 +45,7 @@ #include "xe_hwmon.h" #include "xe_i2c.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_mmio.h" #include "xe_module.h" #include "xe_nvm.h" @@ -901,6 +902,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 092004d14db2..0aab247075ca 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -14,6 +14,7 @@ =20 #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" +#include "xe_late_bind_fw_types.h" #include "xe_lmtt_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" @@ -282,6 +283,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -529,6 +532,9 @@ struct xe_device { /** @nvm: discrete graphics non-volatile memory */ struct intel_dg_nvm_dev *nvm; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..5f386f860728 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D NULL; +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * @late_bind: pointer to late bind structure. + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LB) || !IS_ENABLED(CONFIG_INTEL_MEI_GSC)= ) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return 0; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + INTEL_COMPONENT_LB); + if (err < 0) { + drm_err(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_P= TR(err)); + return err; + } + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..f79e5aefed94 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + struct device *mei_dev; + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @component: struct for communication with mei component */ + struct xe_late_bind_component component; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 701ba9baa9d7..77bee811a150 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -334,6 +334,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_mbx_power_limits =3D true, .has_gsc_nvm =3D 1, .has_heci_cscfi =3D 1, + .has_late_bind =3D true, .has_sriov =3D true, .max_gt_per_tile =3D 2, .needs_scratch =3D true, @@ -588,6 +589,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_late_bind =3D desc->has_late_bind; xe->info.has_llc =3D desc->has_llc; xe->info.has_pxp =3D desc->has_pxp; xe->info.has_sriov =3D desc->has_sriov; diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_= types.h index b63002fc0f67..9b9766a3baa3 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -39,6 +39,7 @@ struct xe_device_desc { u8 has_gsc_nvm:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_late_bind:1; u8 has_llc:1; u8 has_mbx_power_limits:1; u8 has_pxp:1; --=20 2.34.1