From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3460B302179 for ; Fri, 5 Sep 2025 15:45:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087122; cv=none; b=p+ckBwm/ogTWjYW1iEWPAM+OQKG6w7nioK2FT/7b1gUVLXOnC6mH8x5ILMhVkf2g4RxD+k3PWB6qIg7LMFvwI8Bd9/8ZI95UjHAJVJrLYc0j+ZZnHYbz0lDOeybOUPQuKNl04z8NV43epXTvEivCSHokJ/7ctTBJSgxHQrWQtzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757087122; c=relaxed/simple; bh=vgk1lqclsOlLszFoOqnW3JFUcsS7Usoj1a9piG+7EIQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=br86D++XuQp8HUlMEfMXwHOZy6dxT+a5kiKD0THh9U9lmf+6jcllUnAgw+KDqUqjwJxldeUpii9AXqcQzKpDzLoyDkmFg8wIhrjEaNwDSpaEsAyzzrUFNkQmMhf7CaYp4VC4sG/Ob3M5y+2Ron5QFA1MMbGdNoQ53l6LDJaiF8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ba3h1ekH; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ba3h1ekH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757087120; x=1788623120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vgk1lqclsOlLszFoOqnW3JFUcsS7Usoj1a9piG+7EIQ=; b=ba3h1ekHb+HmJcdpqNNdRS5dHiEDLfE4SrFyff+z6sIy0EPD75COj3jA mj2yFbjZnACCyyzJ+jBGJ242trSX/LMidnsgztW4ATIbFS4NhnKXm0z7N KnNr7GvHUPLc4a6QbrdXcEPl+tdbe1uw2TP+2aUc48A+quOPhufxeY3ND r7uSOdXq3K0rLJ14XNQR91nwakEAfaiMDUYQgZGWSzkvf8N+yFlM/VX18 GBnZEh7I1sPr+wGU28amdU7YTmnzARVrsGorGZl2R8gP55frnxtN70zrJ BgolqewGQ7Z/KRSnSqrH6ioXua/8RzExIFc6d1SS4xgG1lRy9l2ZEeAIk g==; X-CSE-ConnectionGUID: IFHIv3sCRAq0sL7QAIXr8Q== X-CSE-MsgGUID: aSL77rkTQB2l/ZtwOhxIjQ== X-IronPort-AV: E=McAfee;i="6800,10657,11544"; a="70144627" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144627" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:20 -0700 X-CSE-ConnectionGUID: odg4evxLQj6xyoAPm5P5wA== X-CSE-MsgGUID: cEmgysSeTEGVR9bETP0cGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071715" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:17 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 1/9] mei: bus: add mei_cldev_mtu interface Date: Fri, 5 Sep 2025 21:19:45 +0530 Message-Id: <20250905154953.3974335-2-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Add a new helper function that allows MEI client drivers to query the maximum transmission unit (MTU) for a connected MEI client. This is useful for clients that need to transmit large payloads, such as firmware blobs, allowing them to determine the maximum message size that can be safely sent before starting transmission and size of the buffer to allocate when receiving data. Reviewed-by: Mika Westerberg Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Rodrigo Vivi --- drivers/misc/mei/bus.c | 13 +++++++++++++ include/linux/mei_cl_bus.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 5cc3ad07d5be..09aae8f9d225 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -614,6 +614,19 @@ u8 mei_cldev_ver(const struct mei_cl_device *cldev) } EXPORT_SYMBOL_GPL(mei_cldev_ver); =20 +/** + * mei_cldev_mtu - max message that client can send and receive + * + * @cldev: mei client device + * + * Return: mtu or 0 if client is not connected + */ +size_t mei_cldev_mtu(const struct mei_cl_device *cldev) +{ + return mei_cl_mtu(cldev->cl); +} +EXPORT_SYMBOL_GPL(mei_cldev_mtu); + /** * mei_cldev_enabled - check whether the device is enabled * diff --git a/include/linux/mei_cl_bus.h b/include/linux/mei_cl_bus.h index 725fd7727422..a82755e1fc40 100644 --- a/include/linux/mei_cl_bus.h +++ b/include/linux/mei_cl_bus.h @@ -113,6 +113,7 @@ int mei_cldev_register_notif_cb(struct mei_cl_device *c= ldev, mei_cldev_cb_t notif_cb); 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d="scan'208";a="172071732" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:20 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 2/9] mei: late_bind: add late binding component driver Date: Fri, 5 Sep 2025 21:19:46 +0530 Message-Id: <20250905154953.3974335-3-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Introduce a new MEI client driver to support Late Binding firmware upload/update for Intel discrete graphics platforms. Late Binding is a runtime firmware upload/update mechanism that allows payloads, such as fan control and voltage regulator, to be securely delivered and applied without requiring SPI flash updates or system reboots. This driver enables the Xe graphics driver and other user-space tools to push such firmware blobs to the authentication firmware via the MEI interface. The driver handles authentication, versioning, and communication with the authentication firmware, which in turn coordinates with the PUnit/PCODE to apply the payload. This is a foundational component for enabling dynamic, secure, and re-entrant configuration updates on platforms like Battlemage. Cc: Badal Nilawar Reviewed-by: Mika Westerberg Signed-off-by: Badal Nilawar Reviewed-by: Anshuman Gupta Signed-off-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/misc/mei/Kconfig | 13 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/mei_lb.c | 312 +++++++++++++++++++++ include/drm/intel/i915_component.h | 1 + include/drm/intel/intel_lb_mei_interface.h | 70 +++++ 5 files changed, 397 insertions(+) create mode 100644 drivers/misc/mei/mei_lb.c create mode 100644 include/drm/intel/intel_lb_mei_interface.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 7575fee96cc6..f8b04e49e4ba 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -81,6 +81,19 @@ config INTEL_MEI_VSC This driver can also be built as a module. If so, the module will be called mei-vsc. =20 +config INTEL_MEI_LB + tristate "Intel Late Binding (LB) support on ME Interface" + depends on INTEL_MEI_ME + depends on DRM_XE + help + Enable support for Intel Late Binding (LB) via the MEI interface. + + Late Binding is a method for applying firmware updates at runtime, + allowing the Intel Xe driver to load firmware payloads such as + fan controller or voltage regulator. These firmware updates are + authenticated and versioned, and do not require firmware flashing + or system reboot. + source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" source "drivers/misc/mei/gsc_proxy/Kconfig" diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index 6f9fdbf1a495..a203ed766b33 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -31,6 +31,7 @@ CFLAGS_mei-trace.o =3D -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) +=3D hdcp/ obj-$(CONFIG_INTEL_MEI_PXP) +=3D pxp/ obj-$(CONFIG_INTEL_MEI_GSC_PROXY) +=3D gsc_proxy/ +obj-$(CONFIG_INTEL_MEI_LB) +=3D mei_lb.o =20 obj-$(CONFIG_INTEL_MEI_VSC_HW) +=3D mei-vsc-hw.o mei-vsc-hw-y :=3D vsc-tp.o diff --git a/drivers/misc/mei/mei_lb.c b/drivers/misc/mei/mei_lb.c new file mode 100644 index 000000000000..77686b108d3c --- /dev/null +++ b/drivers/misc/mei/mei_lb.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mkhi.h" + +/** + * DOC: Late Binding Firmware Update/Upload + * + * Late Binding is a firmware update/upload mechanism that allows configur= ation + * payloads to be securely delivered and applied at runtime, rather than + * being embedded in the system firmware image (e.g., IFWI or SPI flash). + * + * This mechanism is used to update device-level configuration such as: + * - Fan controller + * - Voltage regulator (VR) + * + * Key Characteristics: + * --------------------- + * - Runtime Delivery: + * Firmware blobs are loaded by the host driver (e.g., Xe KMD) + * after the GPU or SoC has booted. + * + * - Secure and Authenticated: + * All payloads are signed and verified by the authentication firmware. + * + * - No Firmware Flashing Required: + * Updates are applied in volatile memory and do not require SPI flash + * modification or system reboot. + * + * - Re-entrant: + * Multiple updates of the same or different types can be applied + * sequentially within a single boot session. + * + * - Version Controlled: + * Each payload includes version and security version number (SVN) + * metadata to support anti-rollback enforcement. + * + * Upload Flow: + * ------------ + * 1. Host driver (KMD or user-space tool) loads the late binding firmware. + * 2. Firmware is passed to the MEI interface and forwarded to + * authentication firmware. + * 3. Authentication firmware authenticates the payload and extracts + * command and data arrays. + * 4. Authentication firmware delivers the configuration to PUnit/PCODE. + * 5. Status is returned back to the host via MEI. + */ + +#define INTEL_LB_CMD 0x12 +#define INTEL_LB_RSP (INTEL_LB_CMD | 0x80) + +#define INTEL_LB_SEND_TIMEOUT_MSEC 3000 +#define INTEL_LB_RECV_TIMEOUT_MSEC 3000 + +/** + * struct mei_lb_req - Late Binding request structure + * @header: MKHI message header (see struct mkhi_msg_hdr) + * @type: Type of the Late Binding payload + * @flags: Flags to be passed to the authentication firmware (e.g. %INTEL_= LB_FLAGS_IS_PERSISTENT) + * @reserved: Reserved for future use by authentication firmware, must be = set to 0 + * @payload_size: Size of the payload data in bytes + * @payload: Payload data to be sent to the authentication firmware + */ +struct mei_lb_req { + struct mkhi_msg_hdr header; + __le32 type; + __le32 flags; + __le32 reserved[2]; + __le32 payload_size; + u8 payload[] __counted_by(payload_size); +} __packed; + +/** + * struct mei_lb_rsp - Late Binding response structure + * @header: MKHI message header (see struct mkhi_msg_hdr) + * @type: Type of the Late Binding payload + * @reserved: Reserved for future use by authentication firmware, must be = set to 0 + * @status: Status returned by authentication firmware (see &enum intel_lb= _status) + */ +struct mei_lb_rsp { + struct mkhi_msg_hdr header; + __le32 type; + __le32 reserved[2]; + __le32 status; +} __packed; + +static bool mei_lb_check_response(const struct device *dev, ssize_t bytes, + struct mei_lb_rsp *rsp) +{ + /* + * Received message size may be smaller than the full message size when + * reply contains only MKHI header with result field set to the error cod= e. + * Check the header size and content first to output exact error, if need= ed, + * and then process to the whole message. + */ + if (bytes < sizeof(rsp->header)) { + dev_err(dev, "Received less than header size from the firmware: %zd < %z= u\n", + bytes, sizeof(rsp->header)); + return false; + } + if (rsp->header.group_id !=3D MKHI_GROUP_ID_GFX) { + dev_err(dev, "Mismatch group id: 0x%x instead of 0x%x\n", + rsp->header.group_id, MKHI_GROUP_ID_GFX); + return false; + } + if (rsp->header.command !=3D INTEL_LB_RSP) { + dev_err(dev, "Mismatch command: 0x%x instead of 0x%x\n", + rsp->header.command, INTEL_LB_RSP); + return false; + } + if (rsp->header.result) { + dev_err(dev, "Error in result: 0x%x\n", rsp->header.result); + return false; + } + if (bytes < sizeof(*rsp)) { + dev_err(dev, "Received less than message size from the firmware: %zd < %= zu\n", + bytes, sizeof(*rsp)); + return false; + } + + return true; +} + +static int mei_lb_push_payload(struct device *dev, + enum intel_lb_type type, u32 flags, + const void *payload, size_t payload_size) +{ + struct mei_cl_device *cldev; + struct mei_lb_req *req =3D NULL; + struct mei_lb_rsp rsp; + size_t req_size; + ssize_t bytes; + int ret; + + cldev =3D to_mei_cl_device(dev); + + ret =3D mei_cldev_enable(cldev); + if (ret) { + dev_dbg(dev, "Failed to enable firmware client. %d\n", ret); + return ret; + } + + req_size =3D struct_size(req, payload, payload_size); + if (req_size > mei_cldev_mtu(cldev)) { + dev_err(dev, "Payload is too big: %zu\n", payload_size); + ret =3D -EMSGSIZE; + goto end; + } + + req =3D kmalloc(req_size, GFP_KERNEL); + if (!req) { + ret =3D -ENOMEM; + goto end; + } + + req->header.group_id =3D MKHI_GROUP_ID_GFX; + req->header.command =3D INTEL_LB_CMD; + req->type =3D cpu_to_le32(type); + req->flags =3D cpu_to_le32(flags); + req->reserved[0] =3D 0; + req->reserved[1] =3D 0; + req->payload_size =3D cpu_to_le32(payload_size); + memcpy(req->payload, payload, payload_size); + + bytes =3D mei_cldev_send_timeout(cldev, (u8 *)req, req_size, + INTEL_LB_SEND_TIMEOUT_MSEC); + if (bytes < 0) { + dev_err(dev, "Failed to send late binding request to firmware. %zd\n", b= ytes); + ret =3D bytes; + goto end; + } + + bytes =3D mei_cldev_recv_timeout(cldev, (u8 *)&rsp, sizeof(rsp), + INTEL_LB_RECV_TIMEOUT_MSEC); + if (bytes < 0) { + dev_err(dev, "Failed to receive late binding reply from MEI firmware. %z= d\n", + bytes); + ret =3D bytes; + goto end; + } + if (!mei_lb_check_response(dev, bytes, &rsp)) { + dev_err(dev, "Bad response from the firmware. header: %02x %02x %02x %02= x\n", + rsp.header.group_id, rsp.header.command, + rsp.header.reserved, rsp.header.result); + ret =3D -EPROTO; + goto end; + } + + dev_dbg(dev, "status =3D %u\n", le32_to_cpu(rsp.status)); + ret =3D (int)le32_to_cpu(rsp.status); +end: + mei_cldev_disable(cldev); + kfree(req); + return ret; +} + +static const struct intel_lb_component_ops mei_lb_ops =3D { + .push_payload =3D mei_lb_push_payload, +}; + +static int mei_lb_component_master_bind(struct device *dev) +{ + return component_bind_all(dev, (void *)&mei_lb_ops); +} + +static void mei_lb_component_master_unbind(struct device *dev) +{ + component_unbind_all(dev, (void *)&mei_lb_ops); +} + +static const struct component_master_ops mei_lb_component_master_ops =3D { + .bind =3D mei_lb_component_master_bind, + .unbind =3D mei_lb_component_master_unbind, +}; + +static int mei_lb_component_match(struct device *dev, int subcomponent, + void *data) +{ + /* + * This function checks if requester is Intel %PCI_CLASS_DISPLAY_VGA or + * %PCI_CLASS_DISPLAY_OTHER device, and checks if the requester is the + * grand parent of mei_if i.e. late bind MEI device + */ + struct device *base =3D data; + struct pci_dev *pdev; + + if (!dev) + return 0; + + if (!dev_is_pci(dev)) + return 0; + + pdev =3D to_pci_dev(dev); + + if (pdev->vendor !=3D PCI_VENDOR_ID_INTEL) + return 0; + + if (pdev->class !=3D (PCI_CLASS_DISPLAY_VGA << 8) && + pdev->class !=3D (PCI_CLASS_DISPLAY_OTHER << 8)) + return 0; + + if (subcomponent !=3D INTEL_COMPONENT_LB) + return 0; + + base =3D base->parent; + if (!base) /* mei device */ + return 0; + + base =3D base->parent; /* pci device */ + + return !!base && dev =3D=3D base; +} + +static int mei_lb_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct component_match *master_match =3D NULL; + int ret; + + component_match_add_typed(&cldev->dev, &master_match, + mei_lb_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) + return -ENOMEM; + + ret =3D component_master_add_with_match(&cldev->dev, + &mei_lb_component_master_ops, + master_match); + if (ret < 0) + dev_err(&cldev->dev, "Failed to add late binding master component. %d\n"= , ret); + + return ret; +} + +static void mei_lb_remove(struct mei_cl_device *cldev) +{ + component_master_del(&cldev->dev, &mei_lb_component_master_ops); +} + +#define MEI_GUID_MKHI UUID_LE(0xe2c2afa2, 0x3817, 0x4d19, \ + 0x9d, 0x95, 0x6, 0xb1, 0x6b, 0x58, 0x8a, 0x5d) + +static const struct mei_cl_device_id mei_lb_tbl[] =3D { + { .uuid =3D MEI_GUID_MKHI, .version =3D MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_lb_tbl); + +static struct mei_cl_driver mei_lb_driver =3D { + .id_table =3D mei_lb_tbl, + .name =3D "mei_lb", + .probe =3D mei_lb_probe, + .remove =3D mei_lb_remove, +}; + +module_mei_cl_driver(mei_lb_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI Late Binding Firmware Update/Upload"); diff --git a/include/drm/intel/i915_component.h b/include/drm/intel/i915_co= mponent.h index 4ea3b17aa143..8082db222e00 100644 --- a/include/drm/intel/i915_component.h +++ b/include/drm/intel/i915_component.h @@ -31,6 +31,7 @@ enum i915_component_type { I915_COMPONENT_HDCP, I915_COMPONENT_PXP, I915_COMPONENT_GSC_PROXY, + INTEL_COMPONENT_LB, }; =20 /* MAX_PORT is the number of port diff --git a/include/drm/intel/intel_lb_mei_interface.h b/include/drm/intel= /intel_lb_mei_interface.h new file mode 100644 index 000000000000..d65be2cba2ab --- /dev/null +++ b/include/drm/intel/intel_lb_mei_interface.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Intel Corporation + */ + +#ifndef _INTEL_LB_MEI_INTERFACE_H_ +#define _INTEL_LB_MEI_INTERFACE_H_ + +#include + +struct device; + +/** + * define INTEL_LB_FLAG_IS_PERSISTENT - Mark the payload as persistent + * + * This flag indicates that the late binding payload should be stored + * persistently in flash across warm resets. + */ +#define INTEL_LB_FLAG_IS_PERSISTENT BIT(0) + +/** + * enum intel_lb_type - enum to determine late binding payload type + * @INTEL_LB_TYPE_FAN_CONTROL: Fan controller configuration + */ +enum intel_lb_type { + INTEL_LB_TYPE_FAN_CONTROL =3D 1, +}; + +/** + * enum intel_lb_status - Status codes returned on late binding transmissi= ons + * @INTEL_LB_STATUS_SUCCESS: Operation completed successfully + * @INTEL_LB_STATUS_4ID_MISMATCH: Mismatch in the expected 4ID (firmware i= dentity/token) + * @INTEL_LB_STATUS_ARB_FAILURE: Arbitration failure (e.g. conflicting acc= ess or state) + * @INTEL_LB_STATUS_GENERAL_ERROR: General firmware error not covered by o= ther codes + * @INTEL_LB_STATUS_INVALID_PARAMS: One or more input parameters are inval= id + * @INTEL_LB_STATUS_INVALID_SIGNATURE: Payload has an invalid or untrusted= signature + * @INTEL_LB_STATUS_INVALID_PAYLOAD: Payload contents are not accepted by = firmware + * @INTEL_LB_STATUS_TIMEOUT: Operation timed out before completion + */ +enum intel_lb_status { + INTEL_LB_STATUS_SUCCESS =3D 0, + INTEL_LB_STATUS_4ID_MISMATCH =3D 1, + INTEL_LB_STATUS_ARB_FAILURE =3D 2, + INTEL_LB_STATUS_GENERAL_ERROR =3D 3, + INTEL_LB_STATUS_INVALID_PARAMS =3D 4, + INTEL_LB_STATUS_INVALID_SIGNATURE =3D 5, + INTEL_LB_STATUS_INVALID_PAYLOAD =3D 6, + INTEL_LB_STATUS_TIMEOUT =3D 7, +}; + +/** + * struct intel_lb_component_ops - Ops for late binding services + */ +struct intel_lb_component_ops { + /** + * push_payload - Sends a payload to the authentication firmware + * @dev: Device struct corresponding to the mei device + * @type: Payload type (see &enum intel_lb_type) + * @flags: Payload flags bitmap (e.g. %INTEL_LB_FLAGS_IS_PERSISTENT) + * @payload: Pointer to payload buffer + * @payload_size: Payload buffer size in bytes + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by firmware + */ + int (*push_payload)(struct device *dev, u32 type, u32 flags, + const void *payload, size_t payload_size); +}; + +#endif /* _INTEL_LB_MEI_INTERFACE_H_ */ --=20 2.34.1 From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6108E309EE7 for ; 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a="70144637" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144637" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:27 -0700 X-CSE-ConnectionGUID: hl8iSQDnTkm2TfjwqSiRWg== X-CSE-MsgGUID: RuFK0un2SGCF4Nrd863vsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071746" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:24 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 3/9] drm/xe/xe_late_bind_fw: Introduce xe_late_bind_fw Date: Fri, 5 Sep 2025 21:19:47 +0530 Message-Id: <20250905154953.3974335-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introduce xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) v4: - %s/I915_COMPONENT_LATE_BIND/INTEL_COMPONENT_LATE_BIND/ v6: - rebased v7: - rebased - In xe_late_bind_init, use drm_err when returning an error to stop the probe (Lucas) - Use imperative mode in commit message (Lucas) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 84 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 33 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 2 + drivers/gpu/drm/xe/xe_pci_types.h | 1 + 8 files changed, 147 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index d6bd139c5839..1b062005ac8d 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -84,6 +84,7 @@ xe-y +=3D xe_bb.o \ xe_hw_error.o \ xe_hw_fence.o \ xe_irq.o \ + xe_late_bind_fw.o \ xe_lrc.o \ xe_migrate.o \ xe_mmio.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 9e2952c9c06a..3fbae3e579d0 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -45,6 +45,7 @@ #include "xe_hwmon.h" #include "xe_i2c.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_mmio.h" #include "xe_module.h" #include "xe_nvm.h" @@ -901,6 +902,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 092004d14db2..0aab247075ca 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -14,6 +14,7 @@ =20 #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" +#include "xe_late_bind_fw_types.h" #include "xe_lmtt_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" @@ -282,6 +283,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -529,6 +532,9 @@ struct xe_device { /** @nvm: discrete graphics non-volatile memory */ struct intel_dg_nvm_dev *nvm; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..5f386f860728 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D NULL; +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * @late_bind: pointer to late bind structure. + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LB) || !IS_ENABLED(CONFIG_INTEL_MEI_GSC)= ) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return 0; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + INTEL_COMPONENT_LB); + if (err < 0) { + drm_err(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_P= TR(err)); + return err; + } + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..f79e5aefed94 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + struct device *mei_dev; + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @component: struct for communication with mei component */ + struct xe_late_bind_component component; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 701ba9baa9d7..77bee811a150 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -334,6 +334,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_mbx_power_limits =3D true, .has_gsc_nvm =3D 1, .has_heci_cscfi =3D 1, + .has_late_bind =3D true, .has_sriov =3D true, .max_gt_per_tile =3D 2, .needs_scratch =3D true, @@ -588,6 +589,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_late_bind =3D desc->has_late_bind; xe->info.has_llc =3D desc->has_llc; xe->info.has_pxp =3D desc->has_pxp; xe->info.has_sriov =3D desc->has_sriov; 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d="scan'208";a="172071760" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:27 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 4/9] drm/xe/xe_late_bind_fw: Initialize late binding firmware Date: Fri, 5 Sep 2025 21:19:48 +0530 Message-Id: <20250905154953.3974335-5-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Search for late binding firmware binaries and populate the meta data of firmware structures. v2 (Daniele): - drm_err if firmware size is more than max pay load size - s/request_firmware/firmware_request_nowarn/ as firmware will not be available for all possible cards v3 (Daniele): - init firmware from within xe_late_bind_init, propagate error - switch late_bind_fw to array to handle multiple firmware types v4 (Daniele): - Alloc payload dynamically, fix nits v6 (Daniele) - %s/MAX_PAYLOAD_SIZE/XE_LB_MAX_PAYLOAD_SIZE/ Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 100 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 30 +++++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 5f386f860728..2a9255e73747 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -5,6 +5,7 @@ =20 #include #include +#include =20 #include #include @@ -13,6 +14,16 @@ =20 #include "xe_device.h" #include "xe_late_bind_fw.h" +#include "xe_pcode.h" +#include "xe_pcode_api.h" + +static const u32 fw_id_to_type[] =3D { + [XE_LB_FW_FAN_CONTROL] =3D INTEL_LB_TYPE_FAN_CONTROL, + }; + +static const char * const fw_id_to_name[] =3D { + [XE_LB_FW_FAN_CONTROL] =3D "fan_control", + }; =20 static struct xe_device * late_bind_to_xe(struct xe_late_bind *late_bind) @@ -20,6 +31,89 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_tile *root_tile =3D xe_device_get_root_tile(xe); + u32 uval; + + if (!xe_pcode_read(root_tile, + PCODE_MBOX(FAN_SPEED_CONTROL, FSC_READ_NUM_FANS, 0), &uval, NULL)) + return uval; + else + return 0; +} + +static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct xe_late_bind_fw *lb_fw; + const struct firmware *fw; + u32 num_fans; + int ret; + + if (fw_id >=3D XE_LB_FW_MAX_ID) + return -EINVAL; + + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + lb_fw->id =3D fw_id; + lb_fw->type =3D fw_id_to_type[lb_fw->id]; + lb_fw->flags &=3D ~INTEL_LB_FLAG_IS_PERSISTENT; + + if (lb_fw->type =3D=3D INTEL_LB_TYPE_FAN_CONTROL) { + num_fans =3D xe_late_bind_fw_num_fans(late_bind); + drm_dbg(&xe->drm, "Number of Fans: %d\n", num_fans); + if (!num_fans) + return 0; + } + + snprintf(lb_fw->blob_path, sizeof(lb_fw->blob_path), "xe/%s_8086_%04x_%04= x_%04x.bin", + fw_id_to_name[lb_fw->id], pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + + drm_dbg(&xe->drm, "Request late binding firmware %s\n", lb_fw->blob_path); + ret =3D firmware_request_nowarn(&fw, lb_fw->blob_path, xe->drm.dev); + if (ret) { + drm_dbg(&xe->drm, "%s late binding fw not available for current device", + fw_id_to_name[lb_fw->id]); + return 0; + } + + if (fw->size > XE_LB_MAX_PAYLOAD_SIZE) { + drm_err(&xe->drm, "Firmware %s size %zu is larger than max pay load size= %u\n", + lb_fw->blob_path, fw->size, XE_LB_MAX_PAYLOAD_SIZE); + release_firmware(fw); + return -ENODATA; + } + + lb_fw->payload_size =3D fw->size; + lb_fw->payload =3D drmm_kzalloc(&xe->drm, lb_fw->payload_size, GFP_KERNEL= ); + if (!lb_fw->payload) { + release_firmware(fw); + return -ENOMEM; + } + + memcpy((void *)lb_fw->payload, fw->data, lb_fw->payload_size); + release_firmware(fw); + + return 0; +} + +static int xe_late_bind_fw_init(struct xe_late_bind *late_bind) +{ + int ret; + int fw_id; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + ret =3D __xe_late_bind_fw_init(late_bind, fw_id); + if (ret) + return ret; + } + return 0; +} + static int xe_late_bind_component_bind(struct device *xe_kdev, struct device *mei_kdev, void *data) { @@ -80,5 +174,9 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) return err; } =20 - return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); + if (err) + return err; + + return xe_late_bind_fw_init(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index f79e5aefed94..c4a8042f2600 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,34 @@ #include #include =20 +#define XE_LB_MAX_PAYLOAD_SIZE SZ_4K + +/** + * xe_late_bind_fw_id - enum to determine late binding fw index + */ +enum xe_late_bind_fw_id { + XE_LB_FW_FAN_CONTROL =3D 0, + XE_LB_FW_MAX_ID +}; + +/** + * struct xe_late_bind_fw + */ +struct xe_late_bind_fw { + /** @id: firmware index */ + u32 id; + /** @blob_path: firmware binary path */ + char blob_path[PATH_MAX]; + /** @type: firmware type */ + u32 type; + /** @flags: firmware flags */ + u32 flags; + /** @payload: to store the late binding blob */ + const u8 *payload; + /** @payload_size: late binding blob payload_size */ + size_t payload_size; +}; + /** * struct xe_late_bind_component - Late Binding services component * @mei_dev: device that provide Late Binding service. @@ -28,6 +56,8 @@ struct xe_late_bind_component { struct xe_late_bind { /** @component: struct for communication with mei component */ struct xe_late_bind_component component; + /** @late_bind_fw: late binding firmware array */ + struct xe_late_bind_fw late_bind_fw[XE_LB_FW_MAX_ID]; }; =20 #endif --=20 2.34.1 From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2717D393DD7 for ; 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a="70144651" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144651" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:34 -0700 X-CSE-ConnectionGUID: ngbkOomARuOSCMpXeFg8tg== X-CSE-MsgGUID: 2LKG69Y/SPi8qns3Fq5nVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071780" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:31 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 5/9] drm/xe/xe_late_bind_fw: Load late binding firmware Date: Fri, 5 Sep 2025 21:19:49 +0530 Message-Id: <20250905154953.3974335-6-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Load late binding firmware v2: - s/EAGAIN/EBUSY/ - Flush worker in suspend and driver unload (Daniele) v3: - Use retry interval of 6s, in steps of 200ms, to allow other OS components release MEI CL handle (Sasha) v4: - return -ENODEV if component not added (Daniele) - parse and print status returned by csc v5: - Use payload to check firmware valid (Daniele) - Obtain the RPM reference before scheduling the worker to ensure the device remains awake until the worker completes firmware loading (Rodrigo) v6: - In case of error donot re-attempt fw download (Daniele) v7 (Rodrigo): - Rename of mei structs and callback. Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 157 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 9 +- 3 files changed, 165 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 2a9255e73747..bb161d99602e 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -16,6 +16,20 @@ #include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pcode_api.h" +#include "xe_pm.h" + +/* + * The component should load quite quickly in most cases, but it could take + * a bit. Using a very big timeout just to cover the worst case scenario + */ +#define LB_INIT_TIMEOUT_MS 20000 + +/* + * Retry interval set to 6 seconds, in steps of 200 ms, to allow time for + * other OS components to release the MEI CL handle + */ +#define LB_FW_LOAD_RETRY_MAXCOUNT 30 +#define LB_FW_LOAD_RETRY_PAUSE_MS 200 =20 static const u32 fw_id_to_type[] =3D { [XE_LB_FW_FAN_CONTROL] =3D INTEL_LB_TYPE_FAN_CONTROL, @@ -31,6 +45,30 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static const char *xe_late_bind_parse_status(uint32_t status) +{ + switch (status) { + case INTEL_LB_STATUS_SUCCESS: + return "success"; + case INTEL_LB_STATUS_4ID_MISMATCH: + return "4Id Mismatch"; + case INTEL_LB_STATUS_ARB_FAILURE: + return "ARB Failure"; + case INTEL_LB_STATUS_GENERAL_ERROR: + return "General Error"; + case INTEL_LB_STATUS_INVALID_PARAMS: + return "Invalid Params"; + case INTEL_LB_STATUS_INVALID_SIGNATURE: + return "Invalid Signature"; + case INTEL_LB_STATUS_INVALID_PAYLOAD: + return "Invalid Payload"; + case INTEL_LB_STATUS_TIMEOUT: + return "Timeout"; + default: + return "Unknown error"; + } +} + static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -44,6 +82,101 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind= *late_bind) return 0; } =20 +static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_late_bind_fw *lbfw; + int fw_id; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->payload && late_bind->wq) { + drm_dbg(&xe->drm, "Flush work: load %s firmware\n", + fw_id_to_name[lbfw->id]); + flush_work(&lbfw->work); + } + } +} + +static void xe_late_bind_work(struct work_struct *work) +{ + struct xe_late_bind_fw *lbfw =3D container_of(work, struct xe_late_bind_f= w, work); + struct xe_late_bind *late_bind =3D container_of(lbfw, struct xe_late_bind, + late_bind_fw[lbfw->id]); + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int retry =3D LB_FW_LOAD_RETRY_MAXCOUNT; + int ret; + int slept; + + xe_device_assert_mem_access(xe); + + /* we can queue this before the component is bound */ + for (slept =3D 0; slept < LB_INIT_TIMEOUT_MS; slept +=3D 100) { + if (late_bind->component.ops) + break; + msleep(100); + } + + if (!late_bind->component.ops) { + drm_err(&xe->drm, "Late bind component not bound\n"); + /* Do not re-attempt fw load */ + drmm_kfree(&xe->drm, (void *)lbfw->payload); + lbfw->payload =3D NULL; + goto out; + } + + drm_dbg(&xe->drm, "Load %s firmware\n", fw_id_to_name[lbfw->id]); + + do { + ret =3D late_bind->component.ops->push_payload(late_bind->component.mei_= dev, + lbfw->type, + lbfw->flags, + lbfw->payload, + lbfw->payload_size); + if (!ret) + break; + msleep(LB_FW_LOAD_RETRY_PAUSE_MS); + } while (--retry && ret =3D=3D -EBUSY); + + if (!ret) { + drm_dbg(&xe->drm, "Load %s firmware successful\n", + fw_id_to_name[lbfw->id]); + goto out; + } + + if (ret > 0) + drm_err(&xe->drm, "Load %s firmware failed with err %d, %s\n", + fw_id_to_name[lbfw->id], ret, xe_late_bind_parse_status(ret)); + else + drm_err(&xe->drm, "Load %s firmware failed with err %d", + fw_id_to_name[lbfw->id], ret); + /* Do not re-attempt fw load */ + drmm_kfree(&xe->drm, (void *)lbfw->payload); + lbfw->payload =3D NULL; + +out: + xe_pm_runtime_put(xe); +} + +int xe_late_bind_fw_load(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_late_bind_fw *lbfw; + int fw_id; + + if (!late_bind->component_added) + return -ENODEV; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->payload) { + xe_pm_runtime_get_noresume(xe); + queue_work(late_bind->wq, &lbfw->work); + } + } + return 0; +} + static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -97,6 +230,7 @@ static int __xe_late_bind_fw_init(struct xe_late_bind *l= ate_bind, u32 fw_id) =20 memcpy((void *)lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); + INIT_WORK(&lb_fw->work, xe_late_bind_work); =20 return 0; } @@ -106,11 +240,16 @@ static int xe_late_bind_fw_init(struct xe_late_bind *= late_bind) int ret; int fw_id; =20 + late_bind->wq =3D alloc_ordered_workqueue("late-bind-ordered-wq", 0); + if (!late_bind->wq) + return -ENOMEM; + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { ret =3D __xe_late_bind_fw_init(late_bind, fw_id); if (ret) return ret; } + return 0; } =20 @@ -132,6 +271,8 @@ static void xe_late_bind_component_unbind(struct device= *xe_kdev, struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); struct xe_late_bind *late_bind =3D &xe->late_bind; =20 + xe_late_bind_wait_for_worker_completion(late_bind); + late_bind->component.ops =3D NULL; } =20 @@ -145,7 +286,15 @@ static void xe_late_bind_remove(void *arg) struct xe_late_bind *late_bind =3D arg; struct xe_device *xe =3D late_bind_to_xe(late_bind); =20 + xe_late_bind_wait_for_worker_completion(late_bind); + + late_bind->component_added =3D false; + component_del(xe->drm.dev, &xe_late_bind_component_ops); + if (late_bind->wq) { + destroy_workqueue(late_bind->wq); + late_bind->wq =3D NULL; + } } =20 /** @@ -174,9 +323,15 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) return err; } =20 + late_bind->component_added =3D true; + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); if (err) return err; =20 - return xe_late_bind_fw_init(late_bind); + err =3D xe_late_bind_fw_init(late_bind); + if (err) + return err; + + return xe_late_bind_fw_load(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 4c73571c3e62..28d56ed2bfdc 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -11,5 +11,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); +int xe_late_bind_fw_load(struct xe_late_bind *late_bind); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index c4a8042f2600..5c0574aff7b9 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define XE_LB_MAX_PAYLOAD_SIZE SZ_4K =20 @@ -36,6 +37,8 @@ struct xe_late_bind_fw { const u8 *payload; /** @payload_size: late binding blob payload_size */ size_t payload_size; + /** @work: worker to upload latebind blob */ + struct work_struct work; }; =20 /** @@ -47,7 +50,7 @@ struct xe_late_bind_fw { */ struct xe_late_bind_component { struct device *mei_dev; - const struct late_bind_component_ops *ops; + const struct intel_lb_component_ops *ops; }; =20 /** @@ -58,6 +61,10 @@ struct xe_late_bind { struct xe_late_bind_component component; /** @late_bind_fw: late binding firmware array */ struct xe_late_bind_fw late_bind_fw[XE_LB_FW_MAX_ID]; + /** @wq: workqueue to submit request to download late bind blob */ + struct workqueue_struct *wq; + /** @component_added: whether the component has been added */ + bool component_added; }; =20 #endif --=20 2.34.1 From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FAAC393DF9 for ; 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charset="utf-8" Reload late binding fw during runtime resume. Signed-off-by: Badal Nilawar Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_pm.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index bb161d99602e..d4d64677bf48 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -82,7 +82,7 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind *= late_bind) return 0; } =20 -static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); struct xe_late_bind_fw *lbfw; diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 28d56ed2bfdc..07e437390539 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -12,5 +12,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); int xe_late_bind_fw_load(struct xe_late_bind *late_bind); +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index a2e85030b7f4..b7c05508f67a 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -21,6 +21,7 @@ #include "xe_gt_idle.h" #include "xe_i2c.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_sriov_vf_ccs.h" @@ -575,6 +576,9 @@ int xe_pm_runtime_resume(struct xe_device *xe) if (IS_SRIOV_VF(xe)) xe_sriov_vf_ccs_register_context(xe); =20 + if (xe->d3cold.allowed) + xe_late_bind_fw_load(&xe->late_bind); + out: xe_rpm_lockmap_release(xe); xe_pm_write_callback_task(xe, NULL); --=20 2.34.1 From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7FB730B513 for ; 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a="70144674" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144674" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:41 -0700 X-CSE-ConnectionGUID: qkcynP9zTVeLLZQAcNh9Vw== X-CSE-MsgGUID: 6Iz5Cq0oRFun93vq8kLrdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071826" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:37 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 7/9] drm/xe/xe_late_bind_fw: Reload late binding fw during system resume Date: Fri, 5 Sep 2025 21:19:51 +0530 Message-Id: <20250905154953.3974335-8-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reload late binding fw during resume from system suspend v2: - Unconditionally reload late binding fw (Rodrigo) - Flush worker during system suspend Cc: Rodrigo Vivi Signed-off-by: Badal Nilawar Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_pm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index b7c05508f67a..6a170c8581e5 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -129,6 +129,8 @@ int xe_pm_suspend(struct xe_device *xe) if (err) goto err; =20 + xe_late_bind_wait_for_worker_completion(&xe->late_bind); + for_each_gt(gt, xe, id) xe_gt_suspend_prepare(gt); =20 @@ -216,6 +218,8 @@ int xe_pm_resume(struct xe_device *xe) if (IS_SRIOV_VF(xe)) xe_sriov_vf_ccs_register_context(xe); =20 + xe_late_bind_fw_load(&xe->late_bind); + drm_dbg(&xe->drm, "Device resumed\n"); return 0; err: --=20 2.34.1 From nobody Wed Sep 10 05:43:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 786CB30B52E for ; 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a="70144685" X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="70144685" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:44 -0700 X-CSE-ConnectionGUID: rEmIIMD1S5OptsM49Ow9JA== X-CSE-MsgGUID: mczdDwKtTg6kgWP2jeezXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,241,1751266800"; d="scan'208";a="172071930" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 08:45:41 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 8/9] drm/xe/xe_late_bind_fw: Introduce debug fs node to disable late binding Date: Fri, 5 Sep 2025 21:19:52 +0530 Message-Id: <20250905154953.3974335-9-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a debug filesystem node to disable late binding fw reload during the system or runtime resume. This is intended for situations where the late binding fw needs to be loaded from user mode, perticularly for validation purpose. Note that xe kmd doesn't participate in late binding flow from user space. Binary loaded from the userspace will be lost upon entering to D3 cold hence user space app need to handle this situation. v2: - s/(uval =3D=3D 1) ? true : false/!!uval/ (Daniele) v3: - Refine the commit message (Daniele) Acked-by: Rodrigo Vivi Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_debugfs.c | 41 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 3 ++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 2 ++ 3 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugf= s.c index 4b71570529a6..c68e8d73802f 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -330,6 +330,44 @@ static const struct file_operations atomic_svm_timesli= ce_ms_fops =3D { .write =3D atomic_svm_timeslice_ms_set, }; =20 +static ssize_t disable_late_binding_show(struct file *f, char __user *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + char buf[32]; + int len; + + len =3D scnprintf(buf, sizeof(buf), "%d\n", late_bind->disable); + + return simple_read_from_buffer(ubuf, size, pos, buf, len); +} + +static ssize_t disable_late_binding_set(struct file *f, const char __user = *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + u32 uval; + ssize_t ret; + + ret =3D kstrtouint_from_user(ubuf, size, sizeof(uval), &uval); + if (ret) + return ret; + + if (uval > 1) + return -EINVAL; + + late_bind->disable =3D !!uval; + return size; +} + +static const struct file_operations disable_late_binding_fops =3D { + .owner =3D THIS_MODULE, + .read =3D disable_late_binding_show, + .write =3D disable_late_binding_set, +}; + void xe_debugfs_register(struct xe_device *xe) { struct ttm_device *bdev =3D &xe->ttm; @@ -363,6 +401,9 @@ void xe_debugfs_register(struct xe_device *xe) debugfs_create_file("atomic_svm_timeslice_ms", 0600, root, xe, &atomic_svm_timeslice_ms_fops); =20 + debugfs_create_file("disable_late_binding", 0600, root, xe, + &disable_late_binding_fops); + for (mem_type =3D XE_PL_VRAM0; mem_type <=3D XE_PL_VRAM1; ++mem_type) { man =3D ttm_manager_type(bdev, mem_type); =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index d4d64677bf48..0f062008ca83 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -167,6 +167,9 @@ int xe_late_bind_fw_load(struct xe_late_bind *late_bind) if (!late_bind->component_added) return -ENODEV; =20 + if (late_bind->disable) + return 0; + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { lbfw =3D &late_bind->late_bind_fw[fw_id]; if (lbfw->payload) { diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 5c0574aff7b9..158dc1abe072 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -65,6 +65,8 @@ struct xe_late_bind { struct workqueue_struct *wq; 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05 Sep 2025 08:45:44 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, mika.westerberg@linux.intel.com, lucas.demarchi@intel.com, karthik.poosa@intel.com Subject: [PATCH v9 9/9] drm/xe/xe_late_bind_fw: Extract and print version info Date: Fri, 5 Sep 2025 21:19:53 +0530 Message-Id: <20250905154953.3974335-10-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905154953.3974335-1-badal.nilawar@intel.com> References: <20250905154953.3974335-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract and print version info of the late binding binary. v2: Some refinements (Daniele) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 124 +++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 + drivers/gpu/drm/xe/xe_uc_fw_abi.h | 66 +++++++++++ 3 files changed, 193 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 0f062008ca83..38f3feb2aecd 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -45,6 +45,121 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static struct xe_device * +late_bind_fw_to_xe(struct xe_late_bind_fw *lb_fw) +{ + return container_of(lb_fw, struct xe_device, late_bind.late_bind_fw[lb_fw= ->id]); +} + +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_cpd_header(struct xe_late_bind_fw *lb_fw, + const void *data, size_t size, const char *manifest_entry) +{ + struct xe_device *xe =3D late_bind_fw_to_xe(lb_fw); + const struct gsc_cpd_header_v2 *header =3D data; + const struct gsc_manifest_header *manifest; + const struct gsc_cpd_entry *entry; + size_t min_size =3D sizeof(*header); + u32 offset; + int i; + + /* manifest_entry is mandatory */ + xe_assert(xe, manifest_entry); + + if (size < min_size || header->header_marker !=3D GSC_CPD_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct gsc_cpd_header_v2)) { + drm_err(&xe->drm, "%s late binding fw: Invalid CPD header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct gsc_cpd_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the manifest first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, manifest_entry) =3D=3D 0) + offset =3D entry->offset & GSC_CPD_ENTRY_OFFSET_MASK; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find manifest_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_manifest_header); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + manifest =3D data + offset; + + lb_fw->version =3D manifest->fw_version; + + return 0; +} + +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_lb_layout(struct xe_late_bind_fw *lb_fw, + const void *data, size_t size, const char *fpt_entry) +{ + struct xe_device *xe =3D late_bind_fw_to_xe(lb_fw); + const struct csc_fpt_header *header =3D data; + const struct csc_fpt_entry *entry; + size_t min_size =3D sizeof(*header); + u32 offset; + int i; + + /* fpt_entry is mandatory */ + xe_assert(xe, fpt_entry); + + if (size < min_size || header->header_marker !=3D CSC_FPT_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct csc_fpt_header)) { + drm_err(&xe->drm, "%s late binding fw: Invalid FPT header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct csc_fpt_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the cpd header first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, fpt_entry) =3D=3D 0) + offset =3D entry->offset; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find fpt_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_cpd_header_v2); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + return parse_cpd_header(lb_fw, data + offset, size - offset, "LTES.man"); +} + static const char *xe_late_bind_parse_status(uint32_t status) { switch (status) { @@ -224,6 +339,10 @@ static int __xe_late_bind_fw_init(struct xe_late_bind = *late_bind, u32 fw_id) return -ENODATA; } =20 + ret =3D parse_lb_layout(lb_fw, fw->data, fw->size, "LTES"); + if (ret) + return ret; + lb_fw->payload_size =3D fw->size; lb_fw->payload =3D drmm_kzalloc(&xe->drm, lb_fw->payload_size, GFP_KERNEL= ); if (!lb_fw->payload) { @@ -231,6 +350,11 @@ static int __xe_late_bind_fw_init(struct xe_late_bind = *late_bind, u32 fw_id) return -ENOMEM; } =20 + drm_info(&xe->drm, "Using %s firmware from %s version %u.%u.%u.%u\n", + fw_id_to_name[lb_fw->id], lb_fw->blob_path, + lb_fw->version.major, lb_fw->version.minor, + lb_fw->version.hotfix, lb_fw->version.build); + memcpy((void *)lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); INIT_WORK(&lb_fw->work, xe_late_bind_work); diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 158dc1abe072..0f5da89ce98b 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,7 @@ #include #include #include +#include "xe_uc_fw_abi.h" =20 #define XE_LB_MAX_PAYLOAD_SIZE SZ_4K =20 @@ -39,6 +40,8 @@ struct xe_late_bind_fw { size_t payload_size; /** @work: worker to upload latebind blob */ struct work_struct work; + /** @version: late binding blob manifest version */ + struct gsc_version version; }; =20 /** diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_f= w_abi.h index 87ade41209d0..78782d105fa9 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h +++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h @@ -318,4 +318,70 @@ struct gsc_manifest_header { u32 exponent_size; /* in dwords */ } __packed; =20 +/** + * DOC: Late binding Firmware Layout + * + * The Late binding binary starts with FPT header, which contains locations + * of various partitions of the binary. Here we're interested in finding o= ut + * manifest version. To the manifest version, we need to locate CPD header + * one of the entry in CPD header points to manifest header. Manifest head= er + * contains the version. + * + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT Header | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES" | + * | ... | + * | offset >-----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | CPD Header |<-----o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | CPD entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES.man" | + * | ... | + * | offset >----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | Manifest Header |<-----o + * | ... | + * | FW version | + * | ... | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + */ + +/* FPT Headers */ +struct csc_fpt_header { + u32 header_marker; +#define CSC_FPT_HEADER_MARKER 0x54504624 + u32 num_of_entries; + u8 header_version; + u8 entry_version; + u8 header_length; /* in bytes */ + u8 flags; + u16 ticks_to_add; + u16 tokens_to_add; + u32 uma_size; + u32 crc32; + struct gsc_version fitc_version; +} __packed; + +struct csc_fpt_entry { + u8 name[4]; /* partition name */ + u32 reserved1; + u32 offset; /* offset from beginning of CSE region */ + u32 length; /* partition length in bytes */ + u32 reserved2[3]; + u32 partition_flags; +} __packed; + #endif --=20 2.34.1