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Miller" CC: Kamlesh Gurudasani , Manorit Chawdhry , Vignesh Raghavendra , Praneeth Bajjuri , Vishal Mahaveer , Kavitha Malarvizhi , , Subject: [PATCH 2/4] crypto: ti: Add support for AES-CTR in DTHEv2 driver Date: Fri, 5 Sep 2025 18:57:17 +0530 Message-ID: <20250905133504.2348972-6-t-pratham@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250905133504.2348972-4-t-pratham@ti.com> References: <20250905133504.2348972-4-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add support for CTR mode of operation for AES algorithm in the AES Engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-aes.c | 80 +++++++++++++++++++++++++++++-- drivers/crypto/ti/dthev2-common.c | 19 ++++++++ drivers/crypto/ti/dthev2-common.h | 15 ++++++ 4 files changed, 110 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index bdb7f652e093..b36733a8c734 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -6,6 +6,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SKCIPHER select CRYPTO_ECB select CRYPTO_CBC + select CRYPTO_CTR select CRYPTO_XTS help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-aes.c b/drivers/crypto/ti/dthev2-aes.c index 21e7e5b8d6da..07787f0ae4fd 100644 --- a/drivers/crypto/ti/dthev2-aes.c +++ b/drivers/crypto/ti/dthev2-aes.c @@ -63,6 +63,7 @@ enum aes_ctrl_mode_masks { AES_CTRL_ECB_MASK =3D 0x00, AES_CTRL_CBC_MASK =3D BIT(5), + AES_CTRL_CTR_MASK =3D BIT(6), AES_CTRL_XTS_MASK =3D BIT(12) | BIT(11), }; =20 @@ -74,6 +75,8 @@ enum aes_ctrl_mode_masks { #define DTHE_AES_CTRL_KEYSIZE_24B BIT(4) #define DTHE_AES_CTRL_KEYSIZE_32B (BIT(3) | BIT(4)) =20 +#define DTHE_AES_CTRL_CTR_WIDTH_128B (BIT(7) | BIT(8)) + #define DTHE_AES_CTRL_SAVE_CTX_SET BIT(29) =20 #define DTHE_AES_CTRL_OUTPUT_READY BIT_MASK(0) @@ -131,6 +134,15 @@ static int dthe_aes_cbc_setkey(struct crypto_skcipher = *tfm, const u8 *key, unsig return dthe_aes_setkey(tfm, key, keylen); } =20 +static int dthe_aes_ctr_setkey(struct crypto_skcipher *tfm, const u8 *key,= unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); + + ctx->aes_mode =3D DTHE_AES_CTR; + + return dthe_aes_setkey(tfm, key, keylen); +} + static int dthe_aes_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,= unsigned int keylen) { struct dthe_tfm_ctx *ctx =3D crypto_skcipher_ctx(tfm); @@ -206,6 +218,10 @@ static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx = *ctx, case DTHE_AES_CBC: ctrl_val |=3D AES_CTRL_CBC_MASK; break; + case DTHE_AES_CTR: + ctrl_val |=3D AES_CTRL_CTR_MASK; + ctrl_val |=3D DTHE_AES_CTRL_CTR_WIDTH_128B; + break; case DTHE_AES_XTS: ctrl_val |=3D AES_CTRL_XTS_MASK; break; @@ -246,6 +262,9 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) int src_mapped_nents; int dst_mapped_nents; =20 + u8 pad_buf[AES_BLOCK_SIZE] =3D {0}; + int pad_len =3D 0; + bool diff_dst; enum dma_data_direction src_dir, dst_dir; =20 @@ -265,6 +284,29 @@ static int dthe_aes_run(struct crypto_engine *engine, = void *areq) aes_irqenable_val |=3D DTHE_AES_IRQENABLE_EN_ALL; writel_relaxed(aes_irqenable_val, aes_base_reg + DTHE_P_AES_IRQENABLE); =20 + if (ctx->aes_mode =3D=3D DTHE_AES_CTR) { + /* + * CTR mode can operate on any input length, but the hardware + * requires input length to be a multiple of the block size. + * We need to handle the padding in the driver. + */ + if (req->cryptlen % AES_BLOCK_SIZE) { + /* Need to create a new SG list with padding */ + pad_len =3D ALIGN(req->cryptlen, AES_BLOCK_SIZE) - req->cryptlen; + struct scatterlist *sg; + + src =3D kmalloc_array((src_nents + 1), sizeof(*src), GFP_KERNEL); + if (!src) { + ret =3D -ENOMEM; + goto aes_alloc_err; + } + sg_init_table(src, src_nents + 1); + sg =3D dthe_copy_sg(src, req->src, req->cryptlen); + sg_set_buf(sg, pad_buf, pad_len); + src_nents++; + } + } + if (src =3D=3D dst) { diff_dst =3D false; src_dir =3D DMA_BIDIRECTIONAL; @@ -281,7 +323,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) src_mapped_nents =3D dma_map_sg(tx_dev, src, src_nents, src_dir); if (src_mapped_nents =3D=3D 0) { ret =3D -EINVAL; - goto aes_err; + goto aes_map_src_err; } =20 if (!diff_dst) { @@ -293,7 +335,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) if (dst_mapped_nents =3D=3D 0) { dma_unmap_sg(tx_dev, src, src_nents, src_dir); ret =3D -EINVAL; - goto aes_err; + goto aes_map_dst_err; } } =20 @@ -356,11 +398,16 @@ static int dthe_aes_run(struct crypto_engine *engine,= void *areq) } =20 aes_prep_err: - dma_unmap_sg(tx_dev, src, src_nents, src_dir); if (dst_dir !=3D DMA_BIDIRECTIONAL) dma_unmap_sg(rx_dev, dst, dst_nents, dst_dir); +aes_map_dst_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); =20 -aes_err: +aes_map_src_err: + if (ctx->aes_mode =3D=3D DTHE_AES_CTR && req->cryptlen % AES_BLOCK_SIZE) + kfree(src); + +aes_alloc_err: local_bh_disable(); crypto_finalize_skcipher_request(dev_data->engine, req, ret); local_bh_enable(); @@ -375,9 +422,10 @@ static int dthe_aes_crypt(struct skcipher_request *req) =20 /* * If data is not a multiple of AES_BLOCK_SIZE, need to return -EINVAL + * except in CTR mode, where any length is supported. * If data length input is zero, no need to do any operation. */ - if (req->cryptlen % AES_BLOCK_SIZE) + if (req->cryptlen % AES_BLOCK_SIZE && ctx->aes_mode !=3D DTHE_AES_CTR) return -EINVAL; =20 if (req->cryptlen =3D=3D 0) @@ -447,6 +495,28 @@ static struct skcipher_engine_alg cipher_algs[] =3D { }, .op.do_one_request =3D dthe_aes_run, }, /* CBC AES */ + { + .base.init =3D dthe_cipher_init_tfm, + .base.setkey =3D dthe_aes_ctr_setkey, + .base.encrypt =3D dthe_aes_encrypt, + .base.decrypt =3D dthe_aes_decrypt, + .base.min_keysize =3D AES_MIN_KEY_SIZE, + .base.max_keysize =3D AES_MAX_KEY_SIZE, + .base.ivsize =3D AES_IV_SIZE, + .base.base =3D { + .cra_name =3D "ctr(aes)", + .cra_driver_name =3D "ctr-aes-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_alignmask =3D AES_BLOCK_SIZE - 1, + .cra_blocksize =3D 1, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_aes_req_ctx), + .cra_module =3D THIS_MODULE, + }, + .op.do_one_request =3D dthe_aes_run, + }, /* CTR AES */ { .base.init =3D dthe_cipher_init_tfm, .base.setkey =3D dthe_aes_xts_setkey, diff --git a/drivers/crypto/ti/dthev2-common.c b/drivers/crypto/ti/dthev2-c= ommon.c index c39d37933b9e..a2ad79bec105 100644 --- a/drivers/crypto/ti/dthev2-common.c +++ b/drivers/crypto/ti/dthev2-common.c @@ -48,6 +48,25 @@ struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx) return dev_data; } =20 +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen) +{ + struct scatterlist *from_sg, *to_sg; + int sglen; + + for (to_sg =3D dst, from_sg =3D src; buflen && from_sg; buflen -=3D sglen= ) { + sglen =3D from_sg->length; + if (sglen > buflen) + sglen =3D buflen; + sg_set_buf(to_sg, sg_virt(from_sg), sglen); + from_sg =3D sg_next(from_sg); + to_sg =3D sg_next(to_sg); + } + + return to_sg; +} + static int dthe_dma_init(struct dthe_data *dev_data) { int ret; diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index e2d901e70fcc..629f45a3ab33 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -36,6 +36,7 @@ enum dthe_aes_mode { DTHE_AES_ECB =3D 0, DTHE_AES_CBC, + DTHE_AES_CTR, DTHE_AES_XTS, }; =20 @@ -101,6 +102,20 @@ struct dthe_aes_req_ctx { =20 struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); =20 +/** + * dthe_copy_sg - Copy sg entries from src to dst + * @dst: Destination sg to be filled + * @src: Source sg to be copied from + * @buflen: Number of bytes to be copied + * + * Description: + * Copy buflen bytes of data from src to dst. + * + **/ +struct scatterlist *dthe_copy_sg(struct scatterlist *dst, + struct scatterlist *src, + int buflen); + int dthe_register_aes_algs(void); void dthe_unregister_aes_algs(void); =20 --=20 2.43.0