From nobody Tue Sep 9 21:33:51 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7693843147; Fri, 5 Sep 2025 09:43:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757065419; cv=none; b=SlV2aCuWWVztRiQBbX07aHmlSrQdokyQXUCBWqzTfwC6lMktmHgC2rCT/2e6PNTOcECiw3sbaw1DhrFuONEXGQ+5S84mi4RI7vhR5r7xKc8VAAb7q0YA3q+rqAGTzDOc6qiBhGwFGjJmgI0ZMteonGOsMyhaunKt6GeOOPiL4uA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757065419; c=relaxed/simple; bh=epw92aAivcVG/fLMSftApO4Bty3VwOYBRAiQNLwF/5E=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=IlQm5I5SvwO9U0LPjoAjuCO3dgvVwlQxR1pJmw7zuUxqno1VJucQbIk1V4Nc6idLBK6Z6wmQre26MvyxHbp96mwtHaK2ocNuGRDFkY8JceoLhc9dHKp3mEZh/JjSsJnpNfMf3g/PEeu98hylnRfrRcAC6yYVaOWPblrCRDsaRoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uILt6dO8; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uILt6dO8" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5859hUtQ3294675; Fri, 5 Sep 2025 04:43:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757065410; bh=DQJXt0l7muCwR4Tu6CvAWfQ5w6Raa65UZ8uc6i3ChiE=; h=From:To:Subject:Date; b=uILt6dO8aO/+Eyuu4wil43M6t8OPrdvMKnsx4zqDsnboH8FyGLW5TWmvHfVn2HUaF USuswK75eu10yaCwT+81aDhrldmKj0amSRQN6xyH2CcHVH4HjPhH3K0rY3UKM4MgaG XgCMNFIJVY/Sjh9G0/F+0Ffw83H4MarxJNndk7/4= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5859hULX834246 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 04:43:30 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 04:43:29 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 04:43:29 -0500 Received: from hkshenoy.dhcp.ti.com (hkshenoy.dhcp.ti.com [172.24.235.208]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5859hPaT251827; Fri, 5 Sep 2025 04:43:26 -0500 From: Harikrishna Shenoy To: , , , , , , , , , , , Subject: [PATCH v3] arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX Date: Fri, 5 Sep 2025 15:13:25 +0530 Message-ID: <20250905094325.472473-1-h-shenoy@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Rahul T R TI's J721E SoC supports a DPI to DSI video signal conversion bridge on it's platform bus. The IP is from Cadence, and it has a custom TI wrapper around it to facilitate integration. This IP takes the DPI video signals from DSS and alongwith the DPHY IP, it transmits DSI video signals out of the SoC. Add support for DSI bridge and the DPHY-TX. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary Signed-off-by: Harikrishna Shenoy --- Changelog v2 -> v3: -Add dsi ports. -Revert to phy lablels used in v1. Link to v1- https://lore.kernel.org/all/20250822124622.1424473-1-h-shenoy@t= i.com/ Link to v2- https://lore.kernel.org/all/20250904105915.3043773-1-h-shenoy@t= i.com/ =20 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index ab3666ff4297..78fde982aff0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1887,6 +1887,45 @@ port@4 { }; }; =20 + dphy2: phy@4480000 { + compatible =3D "ti,j721e-dphy"; + reg =3D <0x00 0x04480000 0x00 0x1000>; + clocks =3D <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names =3D "psm", "pll_ref"; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 296 3>; + assigned-clock-parents =3D <&k3_clks 296 4>; + assigned-clock-rates =3D <19200000>; + status =3D "disabled"; + }; + + dsi0: dsi@4800000 { + compatible =3D "ti,j721e-dsi"; + reg =3D <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>; + clocks =3D <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names =3D "dsi_p_clk", "dsi_sys_clk"; + power-domains =3D <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + phys =3D <&dphy2>; + phy-names =3D "dphy"; + status =3D "disabled"; + + dsi0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + dss: dss@4a00000 { compatible =3D "ti,j721e-dss"; reg =3D --=20 2.34.1