From nobody Wed Sep 10 05:43:52 2025 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED58335E4CB for ; Fri, 5 Sep 2025 13:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757080745; cv=none; b=nSyIa5uv5IR6rkehXt+wGNaBC1AYWDnJff9VVG0nHkpu/tyoRiaKAftu9rQSL+U0OEds2q7q/RVyRCTB7JBc1Icx8p2U48XWPkZlWESVs6C8LCKETP8WLsx4KuVfKR1XAdC/s2eXxk9hUbySUu1Shlfx1Rc2j4sQiJjURo7ik+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757080745; c=relaxed/simple; bh=Q6Wf1vTZSaIlKJqbaA1DqzvL+IqhH2Z176IYQMLiPD4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FRurejXyq4X+7qgjFK1M0yLOqu+eBE6YUx+hrNLZtmaSjud1G9hBWesrZ0Ih8062JfmoSrBMKXeQSHT5GdmgwVFK5FgygNpUUCmRKCFBjFa3LAAS+FxHfem4I6HIO+ToxZHYJH0C35WyeqITrf7n187cSMAUx5LoWyCh4pm+R3A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=P+auLbKc; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="P+auLbKc" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 551BF1121; Fri, 5 Sep 2025 15:57:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1757080669; bh=Q6Wf1vTZSaIlKJqbaA1DqzvL+IqhH2Z176IYQMLiPD4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P+auLbKcOvvDHIT23THo9Tnpfag9ob2f5r+RzND93z+9MB3O1i01vbSWPF1DRvyhl wt9JhRgFZddytSYPUAO4D9l/49dcH/6h6QVpWtR88TIX68TZFohRzFUsSdVtfvG+RU bd2gplQ/032RheRQI0T0TcFj1Fwn+VnTTNMNqZcg= From: Tomi Valkeinen Date: Fri, 05 Sep 2025 16:58:06 +0300 Subject: [PATCH 1/2] drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com> References: <20250905-tidss-fix-timestamp-v1-0-c2aedf31e2c9@ideasonboard.com> In-Reply-To: <20250905-tidss-fix-timestamp-v1-0-c2aedf31e2c9@ideasonboard.com> To: Jyri Sarha , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Pekka Paalanen , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Laurent Pinchart , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4459; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=Q6Wf1vTZSaIlKJqbaA1DqzvL+IqhH2Z176IYQMLiPD4=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBouuyhQcJxaaJ7DbOUzaH2W8v0RIwP4qbKrh0dO RkDCB+xNjWJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCaLrsoQAKCRD6PaqMvJYe 9SRLEACwnIDQboTmlgeQ0zMAOvHmlaz2nZ3kQ6K9Hw8mhAwUfMI2tw4cQLrOTjAOcYwUrzd4Rhb pKAuY9qtUhO8aqLhOqxBPB379m2IIaO0a/sYSkqAeSVX5Zf0hNkRZAXf6JYZ6Hz63JNByLO6j42 SleOae15J/rv0B9Cgu8BbE5+4P7NMCqU5IvUG7JsPbSnnnjE4bvTkavwRD+MhvLN16tLw6sRQKY cRmjmeyZLWJEgkb2JI6JStv3uRwQxOi9aiFYOyIFc3KVY3XjRllCqPtEVrOaozBk04ikKCdssFL msRJsHnG563dx+lx5CQpykjIvqhULy/3WYxcEG5IJUjE1nRVdEznDFvYL9EBrwkXRB4pI3+Rthw ZQfFpqrVG6OEKyV4RPkabhS0WgPJ8Rv8NVM33IlvVUMQvFC3FaTnAyP8BHyg8CFrAl7I/etTQ37 giH4rTPX5jTsYBUuTQo5pPxQ+ZXeqnXA8VbblF9+pU3CX7lOSvKdw/AjSTpJDrlQvLNn8v/l9/V OxpRxJCR+X5sLeht9i8p/0jGiXWkMW79W9txAAFviNLdhy8WLBj6KipS6oLAgYlhjK2FN4Kdu1T 2o5F+6jCUr1oPCmcR95QIQb1wRKtBRl/7apw4A4ygtC5A4+gnsyVo8ELovRz/nNQ/vlTCdhjiLi N+5wxF6IJlNYxiw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that order, next to each other. dispc_vp_prepare() does preparations for enabling the crtc, by writing some registers, and dispc_vp_enable() does more preparations. As the last thing, dispc_vp_enable() enables the CRTC by writing the enable bit. There might have been a reason at some point in the history for this split, but I can't find any point to it. They also do a bit of overlapping work: both call dispc_vp_find_bus_fmt(). They could as well be a single function. But instead of combining them, this patch moves everything from dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable bit write. The reason for this is that unlike all the preparatory register writes, CRTC enable has an immediate effect, starting the timing generator and the CRTC as a whole. Thus it may be important to time the enable just right (as we do in the next patch). No functional changes. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_crtc.c | 2 +- drivers/gpu/drm/tidss/tidss_dispc.c | 22 ++++++---------------- drivers/gpu/drm/tidss/tidss_dispc.h | 3 +-- 3 files changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tid= ss_crtc.c index da89fd01c337..1b767af8e1f6 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -244,7 +244,7 @@ static void tidss_crtc_atomic_enable(struct drm_crtc *c= rtc, =20 dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state); =20 - dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport, crtc->state); + dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport); =20 spin_lock_irqsave(&ddev->event_lock, flags); =20 diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 7c8c15a5c39b..d4762410d262 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1161,6 +1161,9 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32= hw_videoport, { const struct tidss_crtc_state *tstate =3D to_tidss_crtc_state(state); const struct dispc_bus_format *fmt; + const struct drm_display_mode *mode =3D &state->adjusted_mode; + bool align, onoff, rf, ieo, ipc, ihs, ivs; + u32 hsw, hfp, hbp, vsw, vfp, vbp; =20 fmt =3D dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, tstate->bus_flags); @@ -1173,22 +1176,6 @@ void dispc_vp_prepare(struct dispc_device *dispc, u3= 2 hw_videoport, =20 dispc_enable_am65x_oldi(dispc, hw_videoport, fmt); } -} - -void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, - const struct drm_crtc_state *state) -{ - const struct drm_display_mode *mode =3D &state->adjusted_mode; - const struct tidss_crtc_state *tstate =3D to_tidss_crtc_state(state); - bool align, onoff, rf, ieo, ipc, ihs, ivs; - const struct dispc_bus_format *fmt; - u32 hsw, hfp, hbp, vsw, vfp, vbp; - - fmt =3D dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, - tstate->bus_flags); - - if (WARN_ON(!fmt)) - return; =20 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); =20 @@ -1244,7 +1231,10 @@ void dispc_vp_enable(struct dispc_device *dispc, u32= hw_videoport, mode->crtc_hdisplay - 1) | FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK, mode->crtc_vdisplay - 1)); +} =20 +void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport) +{ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, DISPC_VP_CONTROL_ENABLE_MASK); } diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index 60c1b400eb89..f38493a70122 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -119,8 +119,7 @@ void dispc_ovr_enable_layer(struct dispc_device *dispc, =20 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state); -void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, - const struct drm_crtc_state *state); +void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport); void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport); --=20 2.43.0 From nobody Wed Sep 10 05:43:52 2025 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C36E35E4EF for ; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 It was reported that Weston stops at an assert, which checks that the page flip event timestamp is the same or newer than the previous timestamp: weston_output_finish_frame: Assertion `timespec_sub_to_nsec(stamp, &output-= >frame_time) >=3D 0' failed. With manual tests, I can see that when I enable the CRTC, I get a page flip event with a timestamp of 0. Tracking this down led to drm_reset_vblank_timestamp() which does "t_vblank =3D 0" if "high-precision query" is not available. TI DSS does not have any hardware timestamping, and thus the default ktime_get() is used in the DRM framework to get the vblank timestamp, and ktime_get() is not "high precision" here. It is not quite clear why the framework behaves this way, but I assume the idea is that drm_crtc_vblank_on(), which calls drm_reset_vblank_timestamp(), can be called at any time, and thus ktime_get() wouldn't give a good timestamp. And, the idea is that the driver would wait until next vblank after the CRTC enable, and then we could get a good timestamp. This is hinted in the comment: "reinitialize delayed at next vblank interrupt and assign 0 for now". I think that makes sense. However, when we enable the CRTC in TI DSS, i.e. we write the enable bit to the hardware, that's the exact moment when the "vblank cycle" starts. It is the zero point in the cycle, and thus ktime_get() would give a good timestamp. I am not sure if this is applicable to other hardware, and if so, how should it be solved in the framework. So, let's fix this in the tidss driver at least for now. This patch updates the vblank->time manually to ktime_get() just before sending the vblank event, and we enable the crtc just before calling ktime_get(). To get even more exact timing, the dispc_vp_enable() is moved inside the event_lock spinlock. With this, we get a proper timestamp for the page flip event from enabling the CRTC, and Weston is happy. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_crtc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tid= ss_crtc.c index 1b767af8e1f6..6898f12bb364 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -244,11 +244,16 @@ static void tidss_crtc_atomic_enable(struct drm_crtc = *crtc, =20 dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state); =20 - dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport); - spin_lock_irqsave(&ddev->event_lock, flags); =20 + dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport); + if (crtc->state->event) { + unsigned int pipe =3D drm_crtc_index(crtc); + struct drm_vblank_crtc *vblank =3D &ddev->vblank[pipe]; + + vblank->time =3D ktime_get(); + drm_crtc_send_vblank_event(crtc, crtc->state->event); crtc->state->event =3D NULL; } --=20 2.43.0