From nobody Sun Feb 8 17:36:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEF632701B8; Fri, 5 Sep 2025 18:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098131; cv=none; b=ZDErWw5ISxHq2II9Ozik++JxBx1MqH5usEjgt9GmIjoVhEbGgh4P0wz8agNOMBja/VbMsYrQlqndVhT/o1HMAtkATM2yiGgE/lZZ9Jt4t59eBmyfYsO8v1okc1ULPNmtKjvhYC8wpVKh0ge4eLgy5yAT5frc0dCMXmFRupriqcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757098131; c=relaxed/simple; bh=qnf1b2zKcFkUTQHKXISqjdW6MILR4BxPUkttA+Smuto=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uXOSA2RCdV8Gl62FKF9kXVn0onjXjvD0vyjf8ulGpF3bXSMgsEQHdspnvkPO/KdxBS1bIHXvTYrafeaTT0smxNHwwS5SrneWKJa/+23f5I+yEHAgUmWo+wy88ZrvjfjYqDa6M2T6qBLP5LO5eDzjxfvq1vvd57J7zKqvQ5XJ4hU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YPCL8cjh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YPCL8cjh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8F428C4CEFA; Fri, 5 Sep 2025 18:48:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757098130; bh=qnf1b2zKcFkUTQHKXISqjdW6MILR4BxPUkttA+Smuto=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YPCL8cjhV2u0KXG1MfOuW+Vd1s1HqK1GdZh6sC+Z+dlmb/+CK9a0bl7uyrvDLWXqm mBOj0+9FyCyN27Nd1tPtgcyauGim5yNhv0VzbqxVdILkxNV2cEfYrds4bDORVcysRG vN8/gKOU1yUknk1gSQJJEAl6yZ2AmrRnhgHzjx+oUYIY+5R0TjCgcuM8Vcr1tptYpD 4xUG5sar0GfUXgb7gSrOjuU+XdF7RsAlzmoMUOWOGd36Ip7rOw7cRNkDTcbVG0QcSA 1xzKvo0+BbT/265pShS1UWcVL7U0gGX2WxyvmdjxdwWrew8FNFksSMdSNr1/ls2SU4 jn2Y/F9hl1xLQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86A13CA1017; Fri, 5 Sep 2025 18:48:50 +0000 (UTC) From: Nathan Lynch via B4 Relay Date: Fri, 05 Sep 2025 13:48:27 -0500 Subject: [PATCH RFC 04/13] dmaengine: sdxi: Add MMIO register definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-sdxi-base-v1-4-d0341a1292ba@amd.com> References: <20250905-sdxi-base-v1-0-d0341a1292ba@amd.com> In-Reply-To: <20250905-sdxi-base-v1-0-d0341a1292ba@amd.com> To: Vinod Koul Cc: Wei Huang , Mario Limonciello , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757098128; l=4036; i=nathan.lynch@amd.com; s=20241010; h=from:subject:message-id; bh=AGyFf5vWBLGgXMTQeKDi2itH4wGLo9U+txLID+JDYc8=; b=ckXC4832wmhdl4X+GtoJDyWK0pWs8vPBZBZHOHorNo+MFrwg6bZ22a0Ak7sqn1klOyKsStt2B li2rBwFyrwtCp8P9srcd/tkiA9PC/r4rA82+S0RqE0uln/bfHYYtEKj X-Developer-Key: i=nathan.lynch@amd.com; a=ed25519; pk=ZR637UTGg5YLDj56cxFeHdYoUjPMMFbcijfOkAmAnbc= X-Endpoint-Received: by B4 Relay for nathan.lynch@amd.com/20241010 with auth_id=241 X-Original-From: Nathan Lynch Reply-To: nathan.lynch@amd.com From: Nathan Lynch Add offsets and bitmasks for: * General control and status registers (MMIO_CTL0, MMIO_CTL2, MMIO_STS0) * Capability registers (MMIO_CAP0, MMIO_CAP1) * Context table pointer register (MMIO_CXT_L2) * Error logging control and status registers (MMIO_ERR_CTL, MMIO_ERR_STS, MMIO_ERR_CFG, MMIO_ERR_WRT, MMIO_ERR_RD) This is a useful subset of the MMIO registers and fields defined in the spec. The driver currently does not use MMIO_VERSION, MMIO_GRP_ENUM, or the mailbox registers. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Nathan Lynch --- drivers/dma/sdxi/mmio.h | 92 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 92 insertions(+) diff --git a/drivers/dma/sdxi/mmio.h b/drivers/dma/sdxi/mmio.h new file mode 100644 index 0000000000000000000000000000000000000000..36d174a1f8859055f7808d520de= 1ff193c49ae26 --- /dev/null +++ b/drivers/dma/sdxi/mmio.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * SDXI MMIO register offsets and layouts. + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef DMA_SDXI_MMIO_H +#define DMA_SDXI_MMIO_H + +#include +#include +#include +#include + +/* Refer to "MMIO Control Registers". */ +enum sdxi_reg { + SDXI_MMIO_CTL0 =3D 0x00000, + SDXI_MMIO_CTL2 =3D 0x00010, + SDXI_MMIO_STS0 =3D 0x00100, + SDXI_MMIO_CAP0 =3D 0x00200, + SDXI_MMIO_CAP1 =3D 0x00208, + SDXI_MMIO_VERSION =3D 0x00210, + SDXI_MMIO_CXT_L2 =3D 0x10000, + SDXI_MMIO_RKEY =3D 0x10100, + SDXI_MMIO_ERR_CTL =3D 0x20000, + SDXI_MMIO_ERR_STS =3D 0x20008, + SDXI_MMIO_ERR_CFG =3D 0x20010, + SDXI_MMIO_ERR_WRT =3D 0x20020, + SDXI_MMIO_ERR_RD =3D 0x20028, +}; + +enum { + /* SDXI_MMIO_CTL0 fields */ + SDXI_MMIO_CTL0_FN_GSR =3D GENMASK_ULL(1, 0), + SDXI_MMIO_CTL0_FN_PASID_VL =3D BIT_ULL(2), + SDXI_MMIO_CTL0_FN_ERR_INTR_EN =3D BIT_ULL(4), + SDXI_MMIO_CTL0_FN_PASID =3D GENMASK_ULL(27, 8), + SDXI_MMIO_CTL0_FN_GRP_ID =3D GENMASK_ULL(63, 32), + + /* SDXI_MMIO_CTL2 fields */ + SDXI_MMIO_CTL2_MAX_BUFFER =3D GENMASK_ULL(3, 0), + SDXI_MMIO_CTL2_MAX_AKEY_SZ =3D GENMASK_ULL(15, 12), + SDXI_MMIO_CTL2_MAX_CXT =3D GENMASK_ULL(31, 16), + SDXI_MMIO_CTL2_OPB_000_AVL =3D GENMASK_ULL(63, 32), + + /* SDXI_MMIO_STS0 bit definitions */ + SDXI_MMIO_STS0_FN_GSV =3D GENMASK_ULL(2, 0), + + /* SDXI_MMIO_CAP0 bit definitions */ + SDXI_MMIO_CAP0_SFUNC =3D GENMASK_ULL(15, 0), + SDXI_MMIO_CAP0_DB_STRIDE =3D GENMASK_ULL(22, 20), + SDXI_MMIO_CAP0_MAX_DS_RING_SZ =3D GENMASK_ULL(28, 24), + + /* SDXI_MMIO_CAP1 fields */ + SDXI_MMIO_CAP1_MAX_BUFFER =3D GENMASK_ULL(3, 0), + SDXI_MMIO_CAP1_RKEY_CAP =3D BIT_ULL(4), + SDXI_MMIO_CAP1_RM =3D BIT_ULL(5), + SDXI_MMIO_CAP1_MMIO64 =3D BIT_ULL(6), + SDXI_MMIO_CAP1_MAX_ERRLOG_SZ =3D GENMASK_ULL(11, 8), + SDXI_MMIO_CAP1_MAX_AKEY_SZ =3D GENMASK_ULL(15, 12), + SDXI_MMIO_CAP1_MAX_CXT =3D GENMASK_ULL(31, 16), + SDXI_MMIO_CAP1_OPB_000_CAP =3D GENMASK_ULL(63, 32), + + /* SDXI_MMIO_VERSION fields */ + SDXI_MMIO_VERSION_MINOR =3D GENMASK_ULL(7, 0), + SDXI_MMIO_VERSION_MAJOR =3D GENMASK_ULL(23, 16), + + /* SDXI_MMIO_CXT_L2 fields */ + SDXI_MMIO_CXT_L2_PTR =3D GENMASK_ULL(63, 12), + + /* SDXI_MMIO_ERR_CFG bit definitions */ + SDXI_MMIO_ERR_CFG_PTR =3D GENMASK_ULL(63, 12), + SDXI_MMIO_ERR_CFG_SZ =3D GENMASK_ULL(5, 1), + SDXI_MMIO_ERR_CFG_EN =3D BIT_ULL(0), + + /* SDXI_MMIO_RKEY bit definitions */ + SDXI_MMIO_RKEY_PTR =3D GENMASK_ULL(63, 12), + SDXI_MMIO_RKEY_SZ =3D GENMASK_ULL(4, 1), + SDXI_MMIO_RKEY_EN =3D BIT_ULL(0), + + /* SDXI_MMIO_ERR_CTL bit definitions */ + SDXI_MMIO_ERR_CTL_EN =3D BIT_ULL(0), + + /* SDXI_MMIO_ERR_STS bit definitions. */ + SDXI_MMIO_ERR_STS_STS_BIT =3D BIT_ULL(0), + SDXI_MMIO_ERR_STS_OVF_BIT =3D BIT_ULL(1), + SDXI_MMIO_ERR_STS_ERR_BIT =3D BIT_ULL(3), +}; + +#endif /* DMA_SDXI_MMIO_H */ --=20 2.39.5