From nobody Wed Sep 10 01:59:47 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D2E42D640A; Fri, 5 Sep 2025 10:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757067870; cv=pass; b=bR4abjVlGkI4MzhL50G6xaYfhvcKIMrzvWSXlw96wiwJqnvSv0bf+IZftJvkv5DLRi3SdBAX/uBSMw/BykHyI3KkBvznfpW7+2nJzVMpefva4KDuZuOQxP+8GD75fjUzMrIanVY7pQeHlGQ6syUQFnyr3W6n4ojlhpinjOjfbnQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757067870; c=relaxed/simple; bh=38ojihanihmK8WTQZT45+T1HhdbhtLjB3V1NJxQwLJA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sxSdyNttzVNicee+Wn9EoL+0g7zoL/Kzs9YYsFTcc5AcaP5OxL7m7UTJenIGMUK00k7jlOa26W7hZh5JjdxTe2z5TJRd7E6VFJhuOBmS1f9jrVgbnxgeNn+BVo7URhKovIYKWlBWlXYRCiQE7V8JzfS3eRQgBv9r+6vfmMslFN0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Hldl4bd6; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Hldl4bd6" ARC-Seal: i=1; a=rsa-sha256; t=1757067840; cv=none; d=zohomail.com; s=zohoarc; b=hfGlNTvaNfyjc7EUprihGHziCko/dyeAG0KhFB9+bcFFP32qZp+sZLwN/ZZu5yQ8HA+cbOYCi2fjL8tMXPZBAnZFzBsVIMlOAC7ocMa9oXC4oN5dr+2ltvkAWrMI+IHQ+If6hVFpRpmq+pet80MJdCxLXtrA0X61I9ZIUfFmJuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757067840; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=28hWbwauwaaUzRKE5Rn+QofWKCrZmo0Z+fU+KOp7vb4=; b=fRAtYjYE1HZUDBdUduTBLgTjIGgSa8d2R3AfVu1Tdrh5Vvj52313olGIBEQXj2QV+Qm63DL6XlslM9bJIfa5fU+FzHR0ll6PPUGUozWHr66U06oe7iRVFXGnsiiqTNquDyGxGMkLuISAmkaaJ4m7ZoY7RVhoUQtxKf93ct+uLI4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1757067840; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=28hWbwauwaaUzRKE5Rn+QofWKCrZmo0Z+fU+KOp7vb4=; b=Hldl4bd6STxNyqkR5U1l/1OGA2b+HBhwp9EuJ057EXjMDyFLGajTZ57A3Ponm3z5 OhZ77KKk2vMpmEEDEWEjKKgkV737SFGo3Z2WoWgamA70ZxR8g6YS9TdaKmxpNbEInSr YG5PYBoPHu3y/3LmMw4XriI3fdFB5Rgb2I+HoRi8= Received: by mx.zohomail.com with SMTPS id 1757067839865275.92172227990136; Fri, 5 Sep 2025 03:23:59 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 05 Sep 2025 12:23:00 +0200 Subject: [PATCH RFC 04/10] dt-bindings: mailbox: Add MT8196 GPUEB Mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-mt8196-gpufreq-v1-4-7b6c2d6be221@collabora.com> References: <20250905-mt8196-gpufreq-v1-0-7b6c2d6be221@collabora.com> In-Reply-To: <20250905-mt8196-gpufreq-v1-0-7b6c2d6be221@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" Cc: Chia-I Wu , Chen-Yu Tsai , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs proprietary firmware for this purpose, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Signed-off-by: Nicolas Frattaroli --- .../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpue= b-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpu= eb-mbox.yaml new file mode 100644 index 0000000000000000000000000000000000000000..506723d54ae0a429b462914f366= 6184c24c4fc5a --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.= yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics GPUEB Mailbox Controller + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - mediatek,mt8196-gpueb-mbox + + reg: + items: + - description: mailbox data registers + - description: mailbox control registers + + reg-names: + items: + - const: mbox + - const: mbox_ctl + + clocks: + items: + - description: main clock of the GPUEB MCU + + interrupts: + items: + - description: fires when a new message is received + + "#mbox-cells": + const: 1 + description: + The number of the mailbox channel. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gpueb_mbox: mailbox@4b09fd80 { + compatible =3D "mediatek,mt8196-gpueb-mbox"; + reg =3D <0x4b09fd80 0x280>, + <0x4b170000 0x7c>; + reg-names =3D "mbox", "mbox_ctl"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; --=20 2.51.0