From nobody Wed Sep 10 01:59:47 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DB292D6626; Fri, 5 Sep 2025 10:24:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757067859; cv=pass; b=E0Fh9swcmoVSo6xirzbqxOnYkAv+cqIeDO2RygqKxRaHsIz7OGuEsd5UEYG1VUNCZT8L7eSIsgj79YGohxb+j+HgfzevZCZfgkLzcJpwZDxaA2Szki4OKr/6eawrtku0BHN5PUbYp8744CCdG+4716vk1mi6XIg+2/7RQzXOSLo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757067859; c=relaxed/simple; bh=KKeJHcuyfcAZEQqhEka41a06N41CtHc4T5e3u0Iv8uY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UoFVYvKFrDof6JY2H7PKlG2+bh2xG0p9NcMqBM0TxjFOy9ZL5lnAEYKp7AfSOjWdGYdQ4b3r2q5NWGOJFBpMfh2i2TQuoLU0iQPowGORF9YNnFhTWC0BHFneb8XAdRtpI73jb/Kwa/AlGGMr37BH1uhEQoMpg6XMQBk5jz78Kz4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=g3iqPgC0; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="g3iqPgC0" ARC-Seal: i=1; a=rsa-sha256; t=1757067830; cv=none; d=zohomail.com; s=zohoarc; b=hkH1JYAHlf6zYePcwkDs61WrJEaI2U8t/sNwWsVY11sa6gvljLXFKRyq23txh7Y0Yv/uK19wlrT3e4SXgdCBDWXxCGU2f/oJATnXFjxrS1Xyh56URnRI0fPrXndq6Tjl8qjX+VBIhDeUp5bM1Ci0OK9TjEX3DZ5WB30W1mUPVlw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757067830; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=xJDFnVvMBGp0ssnHfwN1wWO5gqMs/oZsQPyIp11iV0U=; b=oHxzZdt1XRFdsUMU9mwdgeHf/jr+YHjl9c1yoeJhH+tc2SygADI4O/gLUbezcJx/4RVn3lZiQr1206srArcmv1rbc1ptKdtZPqI1aabaJNbwK+63CtNPKpYv2MW1qIdseCmoIZuA+DsbGfpOyEGX52kh7FAuB+SL7+qcKW5byHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1757067830; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=xJDFnVvMBGp0ssnHfwN1wWO5gqMs/oZsQPyIp11iV0U=; b=g3iqPgC0yF5eeVlbjETcewPUummZO+BM/mR5xuxysw/iJzhR3Nwxq4zw7SVT78kb SEqjPanpnv74k+zqvlst6WUHmNUjdT2b0kHoX29/2dt6rOSdoiFAaT9RyxU5Xo+CA/D nqSkQnfZird48/prsZJb/VBo245LgQdYiapYjiI0= Received: by mx.zohomail.com with SMTPS id 1757067828625770.7656618316871; Fri, 5 Sep 2025 03:23:48 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 05 Sep 2025 12:22:58 +0200 Subject: [PATCH RFC 02/10] dt-bindings: devfreq: add mt8196-gpufreq binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-mt8196-gpufreq-v1-2-7b6c2d6be221@collabora.com> References: <20250905-mt8196-gpufreq-v1-0-7b6c2d6be221@collabora.com> In-Reply-To: <20250905-mt8196-gpufreq-v1-0-7b6c2d6be221@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" Cc: Chia-I Wu , Chen-Yu Tsai , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On the MediaTek MT8196 SoC, the GPU has its power and frequency dynamically controlled by an embedded special-purpose MCU. This MCU is in charge of powering up the GPU silicon. It also provides us with a list of available OPPs at runtime, and is fully in control of all the regulator and clock fiddling it takes to reach a certain level of performance. It's also in charge of enforcing limits on power draw or temperature. Add a binding for this device in the devfreq subdirectory, where it seems to fit in best considering its tasks. The functions of many of the mailbox channels are unknown. This is not the fault of this binding's author; we've never received adequate documentation for this hardware, and the downstream code does not make use of them in a way that'd reveal their purpose. They are kept in the binding as the binding should be complete. Signed-off-by: Nicolas Frattaroli --- .../bindings/devfreq/mediatek,mt8196-gpufreq.yaml | 116 +++++++++++++++++= ++++ 1 file changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpuf= req.yaml b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufre= q.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1fe43c9fc94bb603b1fb77e9a97= a27e92fea1ae8 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Performance Controller + +maintainers: + - Nicolas Frattaroli + +properties: + $nodename: + pattern: '^performance-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: e2_id + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: mfgpll + - const: mfgpll_sc0 + - const: mfgpll_sc1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: gpumpu (some type of memory control, unknown) + - description: FastDVFS control + - description: Unknown + - description: Unknown + - description: Unknown, but likely controls some boosting behaviour + - description: Unknown + + mbox-names: + items: + - const: fast_dvfs_event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: gpumpu + - const: fast_dvfs + - const: ipir_c_met + - const: ipis_c_met + - const: brisket + - const: ppb + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + +additionalProperties: false + +examples: + - | + #include + + gpufreq: performance-controller@4b09fd00 { + compatible =3D "mediatek,mt8196-gpufreq"; + reg =3D <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names =3D "gpr", "rpc", "e2_id"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names =3D "eb", "mfgpll", "mfgpll_sc0", + "mfgpll_sc1"; + mboxes =3D <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 6>, <&gpueb_mbox 7>, <&gpueb_mbox 8>, + <&gpueb_mbox 9>, <&gpueb_mbox 10>, <&gpueb_mbox 11>; + mbox-names =3D "fast_dvfs_event", "gpufreq", "sleep", "timer", "fh= ctl", + "ccf", "gpumpu", "fast_dvfs", "ipir_c_met", "ipis_c_m= et", + "brisket", "ppb"; + shmem =3D <&gpufreq_shmem>; + }; --=20 2.51.0