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Reviewed-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp_format.c | 118 ++++++++++++++++++++++++------= ---- 1 file changed, 85 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/di= sp/mdp_format.c index 28cef986f2d662484afd47440a79393c48256ff5..d577b3d53fbebced63792b5c65f= 50dd45211c8ea 100644 --- a/drivers/gpu/drm/msm/disp/mdp_format.c +++ b/drivers/gpu/drm/msm/disp/mdp_format.c @@ -163,22 +163,83 @@ static struct csc_cfg csc_convert[CSC_MAX] =3D { .tile_height =3D MDP_TILE_HEIGHT_DEFAULT \ } =20 -#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \ -alpha, bp, flg) \ +#define INTERLEAVED_RGB_FMT_TILED(fmt, bp, r, g, b, e0, e1, e2) \ { \ .pixel_format =3D DRM_FORMAT_ ## fmt, \ .fetch_type =3D MDP_PLANE_INTERLEAVED, \ - .alpha_enable =3D alpha, \ + .alpha_enable =3D false, \ + .element =3D { (e0), (e1), (e2), 0 }, \ + .bpc_g_y =3D g, \ + .bpc_b_cb =3D b, \ + .bpc_r_cr =3D r, \ + .bpc_a =3D 0, \ + .chroma_sample =3D CHROMA_FULL, \ + .unpack_count =3D 3, \ + .bpp =3D bp, \ + .fetch_mode =3D MDP_FETCH_UBWC, \ + .flags =3D MSM_FORMAT_FLAG_UNPACK_TIGHT | \ + MSM_FORMAT_FLAG_COMPRESSED, \ + .num_planes =3D 2, \ + .tile_height =3D MDP_TILE_HEIGHT_UBWC, \ +} + +#define INTERLEAVED_RGBA_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \ +{ \ + .pixel_format =3D DRM_FORMAT_ ## fmt, \ + .fetch_type =3D MDP_PLANE_INTERLEAVED, \ + .alpha_enable =3D true, \ .element =3D { (e0), (e1), (e2), (e3) }, \ .bpc_g_y =3D g, \ .bpc_b_cb =3D b, \ .bpc_r_cr =3D r, \ .bpc_a =3D a, \ .chroma_sample =3D CHROMA_FULL, \ - .unpack_count =3D uc, \ + .unpack_count =3D 4, \ .bpp =3D bp, \ .fetch_mode =3D MDP_FETCH_UBWC, \ - .flags =3D MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ + .flags =3D MSM_FORMAT_FLAG_UNPACK_TIGHT | \ + MSM_FORMAT_FLAG_COMPRESSED, \ + .num_planes =3D 2, \ + .tile_height =3D MDP_TILE_HEIGHT_UBWC, \ +} + +#define INTERLEAVED_RGBX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \ +{ \ + .pixel_format =3D DRM_FORMAT_ ## fmt, \ + .fetch_type =3D MDP_PLANE_INTERLEAVED, \ + .alpha_enable =3D false, \ + .element =3D { (e0), (e1), (e2), (e3) }, \ + .bpc_g_y =3D g, \ + .bpc_b_cb =3D b, \ + .bpc_r_cr =3D r, \ + .bpc_a =3D a, \ + .chroma_sample =3D CHROMA_FULL, \ + .unpack_count =3D 4, \ + .bpp =3D bp, \ + .fetch_mode =3D MDP_FETCH_UBWC, \ + .flags =3D MSM_FORMAT_FLAG_UNPACK_TIGHT | \ + MSM_FORMAT_FLAG_COMPRESSED, \ + .num_planes =3D 2, \ + .tile_height =3D MDP_TILE_HEIGHT_UBWC, \ +} + +#define INTERLEAVED_RGBA_DX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3)= \ +{ \ + .pixel_format =3D DRM_FORMAT_ ## fmt, \ + .fetch_type =3D MDP_PLANE_INTERLEAVED, \ + .alpha_enable =3D true, \ + .element =3D { (e0), (e1), (e2), (e3) }, \ + .bpc_g_y =3D g, \ + .bpc_b_cb =3D b, \ + .bpc_r_cr =3D r, \ + .bpc_a =3D a, \ + .chroma_sample =3D CHROMA_FULL, \ + .unpack_count =3D 4, \ + .bpp =3D bp, \ + .fetch_mode =3D MDP_FETCH_UBWC, \ + .flags =3D MSM_FORMAT_FLAG_UNPACK_TIGHT | \ + MSM_FORMAT_FLAG_DX | \ + MSM_FORMAT_FLAG_COMPRESSED, \ .num_planes =3D 2, \ .tile_height =3D MDP_TILE_HEIGHT_UBWC, \ } @@ -525,58 +586,49 @@ static const struct msm_format mdp_formats[] =3D { * the data will be passed by user-space. */ static const struct msm_format mdp_formats_ubwc[] =3D { - INTERLEAVED_RGB_FMT_TILED(BGR565, - 0, BPC5, BPC6, BPC5, - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, - false, 2, MSM_FORMAT_FLAG_COMPRESSED), + INTERLEAVED_RGB_FMT_TILED(BGR565, 2, + BPC5, BPC6, BPC5, + C2_R_Cr, C0_G_Y, C1_B_Cb), =20 - INTERLEAVED_RGB_FMT_TILED(ABGR8888, + INTERLEAVED_RGBA_FMT_TILED(ABGR8888, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 /* ARGB8888 and ABGR8888 purposely have the same color * ordering. The hardware only supports ABGR8888 UBWC * natively. */ - INTERLEAVED_RGB_FMT_TILED(ARGB8888, + INTERLEAVED_RGBA_FMT_TILED(ARGB8888, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 - INTERLEAVED_RGB_FMT_TILED(XBGR8888, + INTERLEAVED_RGBX_FMT_TILED(XBGR8888, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 - INTERLEAVED_RGB_FMT_TILED(XRGB8888, + INTERLEAVED_RGBX_FMT_TILED(XRGB8888, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 - INTERLEAVED_RGB_FMT_TILED(ABGR2101010, + INTERLEAVED_RGBA_DX_FMT_TILED(ABGR2101010, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 - INTERLEAVED_RGB_FMT_TILED(XBGR2101010, + INTERLEAVED_RGBA_DX_FMT_TILED(XBGR2101010, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 - INTERLEAVED_RGB_FMT_TILED(XRGB2101010, + INTERLEAVED_RGBA_DX_FMT_TILED(XRGB2101010, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 /* XRGB2101010 and ARGB2101010 purposely have the same color * ordering. The hardware only supports ARGB2101010 UBWC * natively. */ - INTERLEAVED_RGB_FMT_TILED(ARGB2101010, + INTERLEAVED_RGBA_DX_FMT_TILED(ARGB2101010, 4, BPC8A, BPC8, BPC8, BPC8, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED), + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA), =20 PSEUDO_YUV_FMT_TILED(NV12, 0, BPC8, BPC8, BPC8, --=20 2.47.2