From nobody Tue Sep 9 21:36:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A84B283145; Fri, 5 Sep 2025 09:06:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757063206; cv=none; b=WVVLN/ld5torGo70UGT9FRsAAfFfj+G5UATKxY92fvoD+y8uxJP/LMp3Y+8iQDzz5iWEfH7Q8d3Mf6aXoAv+NKTivFGHLWXZ5FXLfAp+pn00vTxvixYpTlpXrcDygHmdJK27W8Kt7ri2b4+SABp/RWdz4f1Z6KBsNURpQAOShPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757063206; c=relaxed/simple; bh=OUSduZHpQytaAfXKSV2SoQ+CWi6AI0udx0LxSMgifvY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jpOh/wszR9TKwXee82KBx6aYyzaS2XI8ZtKZMl11iJRlA52y6Jh++t/wL+mO64lZ6EeFzc5Wq/4AQjYOfmtAudhyhMGuvmg2OdDtzw7v483IbHspF5GQg6nS0tJPfSsPSehicyb6k1qi7hErCUVDV8Qaf2JRhzpkkfFTVgUywUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XZ9VMjq/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XZ9VMjq/" Received: by smtp.kernel.org (Postfix) with ESMTPS id EC7BBC4CEF9; Fri, 5 Sep 2025 09:06:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757063206; bh=OUSduZHpQytaAfXKSV2SoQ+CWi6AI0udx0LxSMgifvY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XZ9VMjq/lujMZqIuoOmIgvJW0tFX8x3xvhSRioiEUc1OjKhKaD0OcuPI4Nvh6yrO5 DYLDPumP+deJpzAXozQZ8eQNwlpLkQ0ggzEJGGgLply3RaPXAPF0sV1I0Z9bEkHvVZ TbP7Msr6OJGu9AksOO3UBytgOdtLf02rrpxK+xhPENA92cPCmcOA0SUIW9lQv7Q1Fo aAv7zbPN1upn9+1qg1cG23BeeqeIv+ovkwVjRyMK0+e5NmNM4iWJeimcXLv1zCQcu8 3tPMvHvHrYf184b7dW5zCJ73/73KHiaaT2WK2AMEQfdzQyu0Dtjo+3/VD7CkpQD4D8 ye5JqetFtNofA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCAB6CA1015; Fri, 5 Sep 2025 09:06:45 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 05 Sep 2025 17:06:38 +0800 Subject: [PATCH v3 1/2] dt-bindings: clock: add video clock indices for Amlogic S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-add_video_clk-v3-1-8304c91b8b94@amlogic.com> References: <20250905-add_video_clk-v3-0-8304c91b8b94@amlogic.com> In-Reply-To: <20250905-add_video_clk-v3-0-8304c91b8b94@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757063204; l=1113; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=bgu6e/fPXdfrF8SBobYJP00S8M4VvuEqG6nMELJh9dQ=; b=kfwLaqWah0xsMRA97VXkD7xs9E8CRixyqUPl75F/w7L6f8CP0IXJIjp2pU9RVECX+Z+gHaSha rqClD3gmLU6Ad5rhG88yPygZWmAZ39Vwafp3PiYP6lu5NLW+6BSS9lr X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add indices for video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu Acked-by: Conor Dooley --- include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,s4-peripherals-clkc.h index 861a331963ac..b0fc549f53e3 100644 --- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h @@ -232,5 +232,16 @@ #define CLKID_HDCP22_SKPCLK_SEL 222 #define CLKID_HDCP22_SKPCLK_DIV 223 #define CLKID_HDCP22_SKPCLK 224 +#define CLKID_CTS_ENCL_SEL 225 +#define CLKID_CTS_ENCL 226 +#define CLKID_CDAC_SEL 227 +#define CLKID_CDAC_DIV 228 +#define CLKID_CDAC 229 +#define CLKID_DEMOD_CORE_SEL 230 +#define CLKID_DEMOD_CORE_DIV 231 +#define CLKID_DEMOD_CORE 232 +#define CLKID_ADC_EXTCLK_IN_SEL 233 +#define CLKID_ADC_EXTCLK_IN_DIV 234 +#define CLKID_ADC_EXTCLK_IN 235 =20 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Tue Sep 9 21:36:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A8B028A704; Fri, 5 Sep 2025 09:06:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757063206; cv=none; b=MACspXxJKhJYTtGhp0OG7adgLIZWgfYe6BHhs4nFskNscRe3q53CaoX/F54Jp5MuFU9OOcf6ucyEec9ExPEFkT5wcMkLPHbI/OueRd6QM0sv1oO/2p1IyhuTus8wOCc3s9BPNcW3CpaKrLmsV5kRM0OViID+tuMnVoxWbhj8IBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757063206; c=relaxed/simple; bh=Nf4BNlj92A6Gq2vl04S2lCAj8pMT1QldYLkShSHu178=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ofrnjJg9D/o3NwZOvGH5Aq725uyhXDrP+0v2xZdjeiEKB6Hauzhyu5d+P4VLxLP0JYH6WOlg3Csttmh11ayq/G6DhSD1g35Doibhg2SfjqLYhjaiMFVNNvuIV9pNOK6pwHUt97rXlazVbuooECcqq0bLTVk4OGVCbhz87Ucja0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JZG5blmF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JZG5blmF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 05E21C4CEFB; Fri, 5 Sep 2025 09:06:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757063206; bh=Nf4BNlj92A6Gq2vl04S2lCAj8pMT1QldYLkShSHu178=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JZG5blmFIaQPAQuViZoIXaY17JqFnqoY8c2N+iP+QeRohxocLqKH87oqTW9nbwPmD KWUwdhbFbpB0jpyfHMKwnmCG0HaAG9j33NBFA1gIB4zEcYDxLeOc5u86px77UNhxbc o8onfsUJZHn3fctc5XqZ454u3DQQhIFG0g5dIn7oITXlPcgDRKtkwc/bRT2kiL0Jrl l9jsA8kPH8lUCPtt4jdpYPJx6QpqPjDDtlzlwO+JYGHTu3jyhv158qRiLytrvTPkqR JoOvle+gBwCMbeQqEPuQ0tzalH/wHj5VW97cW5YYqqzDn1t12pVMN23zmS0/mMSkeM ocgzayxkwtTZA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC38CA0FED; Fri, 5 Sep 2025 09:06:45 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 05 Sep 2025 17:06:39 +0800 Subject: [PATCH v3 2/2] clk: amlogic: add video-related clocks for S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250905-add_video_clk-v3-2-8304c91b8b94@amlogic.com> References: <20250905-add_video_clk-v3-0-8304c91b8b94@amlogic.com> In-Reply-To: <20250905-add_video_clk-v3-0-8304c91b8b94@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757063204; l=7141; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=kLmXzk491eV2x81ro4ZED7Iyt5KXxTTTzbVBOuqxLYA=; b=QmC/l58/sloPfIy5YK9Z1FVq75GuUgALvxzAREqNgwP7JwIOzanXydlUyAE4u1or3EOQq5eVN MpGpDf+BwBiD0KSvE5uuhqf0aHUOGVezhejOxbUq2YEBTrSd1PA2etz X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 203 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 203 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 6d69b132d1e1..c0f877ce0993 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1126,6 +1127,22 @@ static struct clk_regmap s4_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap s4_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D mux_table_cts_sel, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D s4_cts_parent_hws, + .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VIID_CLK_DIV, @@ -1205,6 +1222,22 @@ static struct clk_regmap s4_cts_encp =3D { }, }; =20 +static struct clk_regmap s4_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VID_CLK_CTRL2, @@ -2735,6 +2768,165 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div5" }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap s4_cdac_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .shift =3D 0, + .width =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "fclk_div4" } + }, + .num_parents =3D 3, + }, +}; + +static struct clk_regmap s4_demod_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 8 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div4" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "gp0_pll" }, + { .fw_name =3D "hifi_pll" } + }, + .num_parents =3D 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 24 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; =20 #define S4_PCLK(_name, _reg, _bit, _flags) \ @@ -3028,6 +3220,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_sel.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, + [CLKID_CTS_ENCL_SEL] =3D &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &s4_cts_encl.hw, + [CLKID_CDAC_SEL] =3D &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] =3D &s4_cdac_div.hw, + [CLKID_CDAC] =3D &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] =3D &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] =3D &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] =3D &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] =3D &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] =3D &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] =3D &s4_adc_extclk_in.hw, }; =20 static const struct meson_clkc_data s4_peripherals_clkc_data =3D { --=20 2.42.0