From nobody Fri Oct 3 06:37:02 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909E22BEFE7; Thu, 4 Sep 2025 21:28:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757021319; cv=none; b=BXTE2k9BFNVGJZJySxWPov8GehNBJAMiizGFFJ7b3+Gtgzv4ooS+KJ0DSFdYT4LhW4CQGLyREYZJ7RYgIjHNuGu9PL+PkSa7GPPQJIA1t6ton7ktyJpwpG+IQK3Y3KLPh2WbtpLt2p8WbUE0TnVYjZvyTKN3iPPcUnv8F1JBKNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757021319; c=relaxed/simple; bh=XfGcghG19TabjT51QdOsitXxhnwZTmBxIT0FUrZXRpA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b7aB/9RlFZhYeoXZvcfL7F2/yrIWBsXY9LfEUjs8i9etfMzxGtBplKub3oh8/xnHz+7DBWIht6TJ4EyQVt9woSnNnfqFgFO82D5al4Tr45HLFo0uy73i3813X1akWI3aGQObvi44K1ZGz5fdtjWL8QFWCxSuNQ8XwneGX/r3yPE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Z0j6tRne; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Z0j6tRne" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584LSWW53169123; Thu, 4 Sep 2025 16:28:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757021312; bh=ffpMJyApy52p0uslmGd/xoHzUe/PhPzo7pID9ctc1EU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Z0j6tRneAzThXhUP/H3kXnLtgPX+Fp6BKKPv7BBSbHnrjzRPvpzgi6vBSMBFjbkK0 d66otnNwiAlxDqBNbiGOQ3bwJ9Frh3oNw/3CpuwUmz+pf0TwaxHnku1E8wYCGFBDno USYuBmITcRtx4JKSYeJbkcMgzqG8avTUevJ7+dEk= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584LSWD54090301 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 16:28:32 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 16:28:31 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 16:28:31 -0500 Received: from uda0506412.dhcp.ti.com (uda0506412.dhcp.ti.com [128.247.81.19]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584LSTnQ3903903; Thu, 4 Sep 2025 16:28:31 -0500 From: Kendall Willis To: , , , , , , , , CC: , , , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-am62p5-sk: Enable Main UART wakeup Date: Thu, 4 Sep 2025 16:28:27 -0500 Message-ID: <20250904212827.3730314-4-k-willis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904212827.3730314-1-k-willis@ti.com> References: <20250904212827.3730314-1-k-willis@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The Main UART can resume from suspend to RAM states when PIN_WKUP_EN is enabled. Add the necessary pins needed to wakeup the system. Add the system idle states that the Main UART can wakeup the system from. Signed-off-by: Kendall Willis --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563b..1857437eb9c34 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -340,14 +340,26 @@ AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX= _CTL */ bootph-all; }; =20 - main_uart0_pins_default: main-uart0-default-pins { + main_uart0_tx_pins_default: main-uart0-tx-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ >; bootph-all; }; =20 + main_uart0_rx_pins_default: main-uart0-rx-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + >; + bootph-all; + }; + + main_uart0_rx_pins_wakeup: main-uart0-rx-wakeup-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (A22) UART0_RXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins =3D < AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ @@ -738,8 +750,12 @@ &mcu_r5fss0_core0 { }; =20 &main_uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_uart0_pins_default>; + pinctrl-names =3D "default", "wakeup"; + pinctrl-0 =3D <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_default= >; + pinctrl-1 =3D <&main_uart0_tx_pins_default>, <&main_uart0_rx_pins_wakeup>; + wakeup-source =3D <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; status =3D "okay"; bootph-all; }; --=20 2.34.1