From nobody Mon Feb 9 16:33:09 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D80463043D7; Thu, 4 Sep 2025 13:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992743; cv=none; b=YnXL/4DOpkgv9y6uzl7gNAys9rC4alLbwgi99b2eYpLuzs4zWwbu5UQbS70VBXdgE4NZq/7N3rxPEcPs4LCpzuEQXHEJCPrZ0xvnrh7T7BZwMMp2bQ85VQzOwtjDLwGdXYvvSmqBFs10XC7BFXx1UYH6vEigZhwZov+kuKA9avE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992743; c=relaxed/simple; bh=lSy3vF7XFPKovwQWLto/qQcnAkkUkDHc9jfWqk1v2Bs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KogCnaNvBnmzRc5W9lB0M07FAANriLWBk0Wf+/vUcVGabGDO2eq7Vw7M2XSX2DzvOqA3uBYgNfZ0rNpyTUMUtNkqiOHHhiWUbR1+kXbqAfBMCWOWHkposKdEJcxjh/BXpxm9yDKzLhDpwnMpJyK0IrGeMYD/mqjsxgUfeqk28Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hUDDNDy8; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hUDDNDy8" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWFfI3477193; Thu, 4 Sep 2025 08:32:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992735; bh=kuhPNOfFxnvgFtt+TvhfdM3wfFKuN7Go35vbK+8gYq0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hUDDNDy8f7sIWgW5n9U/QvfHTw3ykAfxhIfWNoOAP+CDEpTOi4EmPjNvO0PvuKSq7 yGTYCb2i87/FdgS4uugVYw9SWBSHvth+lB4hQgV1ejfmm82lDyR1NO/cdNBbBnUw5w xpfHdW6W4dYmPK1Zp0n2xdfsi+uNPDTU+4MJIkSE= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWFe93839529 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:15 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:14 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:14 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DO3325799; Thu, 4 Sep 2025 08:32:10 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH 2/4] spi: cadence-quadspi: Flush posted register writes before DAC access Date: Thu, 4 Sep 2025 19:01:28 +0530 Message-ID: <20250904133130.3105736-3-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index eaf9a0f522d5..447a32a08a93 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -719,6 +719,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f= _pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 @@ -1063,6 +1064,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata= *f_pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 --=20 2.34.1