From nobody Mon Feb 9 16:33:30 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 137E42EA480; Thu, 4 Sep 2025 13:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992744; cv=none; b=Fg1nTkyIzsJV/oLkPnmCGOluXGYi3zzYGi/LpGvisX861TIOv08oSQug+yhu89yRyaOgzBr8pOFdPNDgRAVG/Ohj3EnbTiha9Ds16g3teMxJENSkdvVSQw/5zp4SB0srSVT6vA1AjzaiIdpKqFLaW7hlIjBdcoJ4fI8A4XmiPQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992744; c=relaxed/simple; bh=OJ8hHB24vr64uxwL1AzyYpobt6fq3/COEZni+VfV5Do=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QQSYjQOR6yY3njJX4WLyFl3ZpqNJf2kE9WgIbsjOFWP9VCEvhhJGXq+PeamvpFWmcehUX0rSyckPg3c+/dwdZjijTOdaT7yj7iYfM9k1JZACEAN0SSf5MzM4VoI/FI6B0qZrQDbg36EjbjISK8hQ3lhf3exJovqHeapbVWVXV6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pq9nYzB/; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pq9nYzB/" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWAcF3020779; Thu, 4 Sep 2025 08:32:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992730; bh=dg6HimCFAZDMskw9sXyOD+jBnhoT5mg+3/PSeKJxO5c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pq9nYzB/1XAoF01Obt003dCU9CtrcPMIg2FNEnVvtdY4R3mBkDas6KbXFTITQwAY2 LZACni87wkjT6uwIbUbVvSoWJIW0mv7GddE1M9P1jQvhntUvr8cvNx7T7KGzHJL2Uw XcHLGpfmBmGOhC+Vver58PJmerHI3ppGq1UF0P2s= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWAhx901106 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:10 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:09 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:10 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DN3325799; Thu, 4 Sep 2025 08:32:05 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Date: Thu, 4 Sep 2025 19:01:27 +0530 Message-ID: <20250904133130.3105736-2-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 9bf823348cd3..eaf9a0f522d5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -764,6 +764,7 @@ static int cqspi_indirect_read_execute(struct cqspi_fla= sh_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ =20 while (remaining > 0) { if (use_irq && @@ -1090,6 +1091,8 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ + /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of --=20 2.34.1