From nobody Sun Feb 8 14:04:26 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 137E42EA480; Thu, 4 Sep 2025 13:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992744; cv=none; b=Fg1nTkyIzsJV/oLkPnmCGOluXGYi3zzYGi/LpGvisX861TIOv08oSQug+yhu89yRyaOgzBr8pOFdPNDgRAVG/Ohj3EnbTiha9Ds16g3teMxJENSkdvVSQw/5zp4SB0srSVT6vA1AjzaiIdpKqFLaW7hlIjBdcoJ4fI8A4XmiPQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992744; c=relaxed/simple; bh=OJ8hHB24vr64uxwL1AzyYpobt6fq3/COEZni+VfV5Do=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QQSYjQOR6yY3njJX4WLyFl3ZpqNJf2kE9WgIbsjOFWP9VCEvhhJGXq+PeamvpFWmcehUX0rSyckPg3c+/dwdZjijTOdaT7yj7iYfM9k1JZACEAN0SSf5MzM4VoI/FI6B0qZrQDbg36EjbjISK8hQ3lhf3exJovqHeapbVWVXV6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pq9nYzB/; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pq9nYzB/" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWAcF3020779; Thu, 4 Sep 2025 08:32:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992730; bh=dg6HimCFAZDMskw9sXyOD+jBnhoT5mg+3/PSeKJxO5c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pq9nYzB/1XAoF01Obt003dCU9CtrcPMIg2FNEnVvtdY4R3mBkDas6KbXFTITQwAY2 LZACni87wkjT6uwIbUbVvSoWJIW0mv7GddE1M9P1jQvhntUvr8cvNx7T7KGzHJL2Uw XcHLGpfmBmGOhC+Vver58PJmerHI3ppGq1UF0P2s= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWAhx901106 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:10 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:09 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:10 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DN3325799; Thu, 4 Sep 2025 08:32:05 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Date: Thu, 4 Sep 2025 19:01:27 +0530 Message-ID: <20250904133130.3105736-2-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 9bf823348cd3..eaf9a0f522d5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -764,6 +764,7 @@ static int cqspi_indirect_read_execute(struct cqspi_fla= sh_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ =20 while (remaining > 0) { if (use_irq && @@ -1090,6 +1091,8 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ + /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of --=20 2.34.1 From nobody Sun Feb 8 14:04:26 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D80463043D7; Thu, 4 Sep 2025 13:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992743; cv=none; b=YnXL/4DOpkgv9y6uzl7gNAys9rC4alLbwgi99b2eYpLuzs4zWwbu5UQbS70VBXdgE4NZq/7N3rxPEcPs4LCpzuEQXHEJCPrZ0xvnrh7T7BZwMMp2bQ85VQzOwtjDLwGdXYvvSmqBFs10XC7BFXx1UYH6vEigZhwZov+kuKA9avE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992743; c=relaxed/simple; bh=lSy3vF7XFPKovwQWLto/qQcnAkkUkDHc9jfWqk1v2Bs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KogCnaNvBnmzRc5W9lB0M07FAANriLWBk0Wf+/vUcVGabGDO2eq7Vw7M2XSX2DzvOqA3uBYgNfZ0rNpyTUMUtNkqiOHHhiWUbR1+kXbqAfBMCWOWHkposKdEJcxjh/BXpxm9yDKzLhDpwnMpJyK0IrGeMYD/mqjsxgUfeqk28Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hUDDNDy8; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hUDDNDy8" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWFfI3477193; Thu, 4 Sep 2025 08:32:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992735; bh=kuhPNOfFxnvgFtt+TvhfdM3wfFKuN7Go35vbK+8gYq0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hUDDNDy8f7sIWgW5n9U/QvfHTw3ykAfxhIfWNoOAP+CDEpTOi4EmPjNvO0PvuKSq7 yGTYCb2i87/FdgS4uugVYw9SWBSHvth+lB4hQgV1ejfmm82lDyR1NO/cdNBbBnUw5w xpfHdW6W4dYmPK1Zp0n2xdfsi+uNPDTU+4MJIkSE= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWFe93839529 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:15 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:14 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:14 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DO3325799; Thu, 4 Sep 2025 08:32:10 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , , Pratyush Yadav , Subject: [PATCH 2/4] spi: cadence-quadspi: Flush posted register writes before DAC access Date: Thu, 4 Sep 2025 19:01:28 +0530 Message-ID: <20250904133130.3105736-3-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash C= ontroller") CC: stable@vger.kernel.org Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index eaf9a0f522d5..447a32a08a93 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -719,6 +719,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f= _pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 @@ -1063,6 +1064,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata= *f_pdata, reg &=3D ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |=3D (op->addr.nbytes - 1); writel(reg, reg_base + CQSPI_REG_SIZE); + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } =20 --=20 2.34.1 From nobody Sun Feb 8 14:04:26 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EC0F303C9B; Thu, 4 Sep 2025 13:32:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992757; cv=none; b=UuaLR4Y7m61t7m8iv3/jNrx7DyNdrmfUBTXPIJXsGIZIqIALOVtSBU8jLnyU1WUNNqhq1MqqbxesVDVwG1ZQc+l+nLQUM1m1WThs8AfbtOge92+VntgsvniHfc1cg/4ZNSGpb+xr5RndTEVtjA8JuOaeC+8jA+4sOgg625Rd18M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992757; c=relaxed/simple; bh=oItnaSCSDsa8nd0WoT2xiv18hJR3qNcqdqdRY0ysN6U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kvOkYPk3ius1ZLFN734x7ONmYq+nD5mO/B+N6dZ3Ts4cgmgYBh/glOr/+zhJF0tcW/MJ8psCgIhWJpWhSAzknkvNg49xtZheX5Xa92++JlWhB++z+kNghzipjed8oep/rArBO/ft7TKK/uK4L7Q95N9En5gsxERD0cKA3RnG+Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tlhYCI2R; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tlhYCI2R" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWJfL3518013; Thu, 4 Sep 2025 08:32:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992739; bh=Tw6vls1StU4RNUesLDoJ8Bhc3qDiBuENJydPRRnQskE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tlhYCI2RjmLEfy9mfmUqG88xoeE8pBVQKiPWbwRvwYdlFvqt01trak7WwFK2lA56w EFaQg4xXSDDHsorcin6mIyk7w9A/cJLm3xh1kv53F42pLjxq8IsWOUcYxLTV9clIgZ MZilYlALWCFD882UWje3g31tEt1t4iqckRk9Rneo= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWJa1149830 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:19 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:18 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:19 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DP3325799; Thu, 4 Sep 2025 08:32:15 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , Subject: [PATCH 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash() Date: Thu, 4 Sep 2025 19:01:29 +0530 Message-ID: <20250904133130.3105736-4-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The 'max_cs' stores the largest chip select number. It should only be updated when the current 'cs' is greater than existing 'max_cs'. So, fix the condition accordingly. Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-sele= ct") Signed-off-by: Santhosh Kumar K Reviewed-by: Pratyush Yadav Reviewed-by: Th=C3=A9o Lebrun --- drivers/spi/spi-cadence-quadspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 447a32a08a93..da3ec15abb3e 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1722,7 +1722,7 @@ static const struct spi_controller_mem_caps cqspi_mem= _caps =3D { =20 static int cqspi_setup_flash(struct cqspi_st *cqspi) { - unsigned int max_cs =3D cqspi->num_chipselect - 1; + unsigned int max_cs =3D 0; struct platform_device *pdev =3D cqspi->pdev; struct device *dev =3D &pdev->dev; struct cqspi_flash_pdata *f_pdata; @@ -1740,7 +1740,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) if (cs >=3D cqspi->num_chipselect) { dev_err(dev, "Chip select %d out of range.\n", cs); return -EINVAL; - } else if (cs < max_cs) { + } else if (cs > max_cs) { max_cs =3D cs; } =20 --=20 2.34.1 From nobody Sun Feb 8 14:04:26 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D39172EA480; Thu, 4 Sep 2025 13:32:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992756; cv=none; b=CTbXtzOMASpyH7e+2wKY7wapwjFgDMw8o21BYMq2xoidJZGQHD1GUeinjJBabm8GTA4dvSqA1uhxF+s9BtDv9pXVLYBQZt7PbleouDhy/5OLFjPbLRH7wyBizZP6ugbDYfSwHQUkecs/aJKT1JbsbimEShJV+Hk2V2ITSPGlUA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756992756; c=relaxed/simple; bh=KlqjwRyOyZ8RVuU0yCrHqiZjDdHNQSVtnaYeXWRiByk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aFKar48lcglcSCRCg4H9QuUbOqJF9bYjx02EaTP4wT0OHSn50M1XGqs5mx6jI4mK3rJmV0wuBDolzsI5Ydh2dtI7GgpgpSLetsF5K5T+2KP2FZJFfFFSZdGRRU+YtueAmIJ4MCygTblor7RWI17VGHznsl9v/uymMQSWH4UXP7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VjUYINx6; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VjUYINx6" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584DWNV23083911; Thu, 4 Sep 2025 08:32:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756992743; bh=VYuB3aj6zQtB9TojGXYO9w09Sr5XdUxpxuM9sgLqAOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VjUYINx6RV55L/P05ywSIVfrrXLSvPueS530AJDoj3tgH9Jy3hklJN8aYGRbobQZV Q+3kiArKHJkVbc3+loBfqkQ7BdlFZy2cION118Uuqol/ixiwEn1CXbJhtTU8sqlGrP wg+hWFnstVNs20py1Z8b6GCHs9dV9VcxJOgaRCS4= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584DWNTJ149849 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 08:32:23 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 08:32:23 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 08:32:23 -0500 Received: from santhoshkumark.dhcp.ti.com (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584DW0DQ3325799; Thu, 4 Sep 2025 08:32:19 -0500 From: Santhosh Kumar K To: , , , , , , CC: , , , , , , Subject: [PATCH 4/4] spi: cadence-quadspi: Use BIT() macros where possible Date: Thu, 4 Sep 2025 19:01:30 +0530 Message-ID: <20250904133130.3105736-5-s-k6@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com> References: <20250904133130.3105736-1-s-k6@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vignesh Raghavendra Convert few open coded bit shifts to BIT() macro for better readability. No functional changes intended. Signed-off-by: Vignesh Raghavendra Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index da3ec15abb3e..b18f095516f2 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -335,7 +335,7 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi) { u32 reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); =20 - return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); + return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB); } =20 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) @@ -571,7 +571,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata = *f_pdata, reg |=3D (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) << CQSPI_REG_CMDCTRL_DUMMY_LSB; =20 - reg |=3D (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + reg |=3D BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB); =20 /* 0 means 1 byte. */ reg |=3D (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) @@ -1191,7 +1191,7 @@ static void cqspi_chipselect(struct cqspi_flash_pdata= *f_pdata) * CS2 to 4b'1011 * CS3 to 4b'0111 */ - chip_select =3D 0xF & ~(1 << chip_select); + chip_select =3D 0xF & ~BIT(chip_select); } =20 reg &=3D ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK --=20 2.34.1