From nobody Fri Oct 3 06:36:43 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88D6D2FC86F; Thu, 4 Sep 2025 11:25:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985161; cv=none; b=ptWhB6FNniurP+ecyW2ZzN9XspzmEyKS+kuLs1u4cbHjjxIc5mat9ILyp4YInt/u3NpDNJLwZAIAZuKsj4NwQYH6kOh8fFBShF9mTGoC+T5kxjrbHqZ1O+A6+aeCqLENqFpa3x/ziMTpJlFBBvh8odfhgqmn1gcFdWmP5ArT8HI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985161; c=relaxed/simple; bh=jy4P8UWYGHbFspF7iugtJuJkmFtynAOIkxNyhFJU0zU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qQSl7v1QG1yi3UKNDPE3SNDn2acAw3Z8NYKUFlB5pe7E3IjZfnspAa53MRS3Uxe0GJqIgKIaohCdFTy5Fx6+XrIRoBJkoxM81JVWNjobkyDudBGEqBU/xHaIqRWbXP1VMD8AXDeX/MCLmSPKtxdymrtxTCd8AASm6gIInj1Z0Is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Lhm/52Xc; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Lhm/52Xc" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584BPtRC3000505; Thu, 4 Sep 2025 06:25:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756985155; bh=otDRlUkWg1EAiRuCq1NNN2J1DtOx7l367UeVek+CWEM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Lhm/52Xc/kyxsG6CE+RN45wHb8frZS/WKmOdQYDpG6NoP4lVYFSBCjEqQf+hMmEqv QIqAElZGAYp8DJjUcX0xNELtxP53walkhfAILu7uACfjK9tNimcTVtabU2rHQFupnh Fw6y6aCQ/NI2lpCXXlbGlB08+TXN9kPnXgt4SF/8= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584BPtIU3772666 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 06:25:55 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 06:25:54 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 06:25:54 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584BPedK3179752; Thu, 4 Sep 2025 06:25:50 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , CC: Subject: [PATCH v4 1/4] arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS Date: Thu, 4 Sep 2025 16:55:35 +0530 Message-ID: <20250904112538.529857-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904112538.529857-1-a-kaur@ti.com> References: <20250904112538.529857-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563..e8f0ac2c55e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACL= KR.UART1_TXD */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Fri Oct 3 06:36:43 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 988B22FCC06; Thu, 4 Sep 2025 11:26:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985170; cv=none; b=Zw8L8Q1SeHAWIM1TUDpfquk+fMPga/wEL6VSElpxm9kjBnfxVPmuGUlPLEK/mCRKn2c/bmkFLZk7QJ/25F/gPOn6TtJdG2Xumx70P3pu2GnY6YRi/haUhQh7aFfJqQnyK3rguuiiTNQNiJmpLTLQh/kVtkilWFn+bQWKhU/cbzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985170; c=relaxed/simple; bh=VWu4d7GqSUwIeDFUNxrTde8n+HgE4QYouRpf9d/Un3U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=P9iVw1va7nRI4yPg7BTrCNxgPISFMoZd8z8bf9hnXjbbqmW3204LGBTqvrXcNKp3/WZPOMsVTcr6PttBz4FK7Tz93eBN2ZYbhd0nJKybKdQcq8TcKNMXcVzER0yUZ1y34inMqR0w+fANzWEj61x9bosXdRZ5sxBHnKLlGnsTEc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fjH1EecB; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fjH1EecB" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584BQ4v73000569; Thu, 4 Sep 2025 06:26:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756985164; bh=cK4uQLEtwZy/fYoLqypop64Y9ZdcTJG2slYJFSfO8Zo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fjH1EecB4/76kATk/8o+Lqp8jNMOld29AsvpmwZjqe3HcVST3zbshoHjdmA4ybRmM UXUE/ldYKuH0qCuxI8IzElwlpT4ow8BQC9EKxH3T8q30zprWDlaOE4sGkZnCHeNUtd AQ0OyQLdqC653/e5A1RC52i3X8h949VSSOPpEkzI= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584BQ3m4831332 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 06:26:04 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 06:26:03 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 06:26:03 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584BPedL3179752; Thu, 4 Sep 2025 06:25:59 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , CC: Subject: [PATCH v4 2/4] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS Date: Thu, 4 Sep 2025 16:55:36 +0530 Message-ID: <20250904112538.529857-3-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904112538.529857-1-a-kaur@ti.com> References: <20250904112538.529857-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..d3bed23134ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_= TX_CTL */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Fri Oct 3 06:36:43 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77102FE579; Thu, 4 Sep 2025 11:26:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985180; cv=none; b=RFjLqlFsZ/gcCvKLgjKfQ1M6kICP57lf/bHna74MR94xPT1H11ljaZZgT0OQ1MwCdmEC/afay0JgWHfDd9uQsZzRmIE71ac6CZnW91BnzyNg1MchwMUTggn7kBoC+gMPI12HggmNJknGOZtO4JfPpv1Qe/eOripbGZM8zbo8i0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756985180; c=relaxed/simple; bh=Jo1nt6tasCtJyjGAaPaNsdaYCYDHQr3OpA1cV+TWc0E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LRoeIuIs4J5CvZBhwkMixospjF2YwPW+z3hHOWJJw7YXDA7t2lDGBD3gfKDpaQ51S5jvcCE50ZMdyk7qzUFPYvWuyclvDkHNEkxlGCQBC7OqbRC4o1GZMVQnFExB7bTXZoVTEa/U2wimTvSJcAygokL/nHj+IMRDf/KcfUXUltI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=eqXw2K6u; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eqXw2K6u" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 584BQCFa3457475; Thu, 4 Sep 2025 06:26:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756985172; bh=/J6HBMjH0Ozeryn1N7swY9fe6jx6vGCta22nNXq7D1o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eqXw2K6urSzUUhAux3Ayr4vLgZ2wNPYFdvyPBXIGMFp79MDwJ8Efww4GEcAUd0EPV rpjsVZ8+GXfVd7Td2iNE+C5jPToo6eY5oHJhQk0eeSLyyLNaHVayrK0d2s64FZ9Eis oi1qOoJtfH1HINEveDjD9ZifoPNHMsmOFONLM5NY= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 584BQCRA3772836 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 06:26:12 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 06:26:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 06:26:11 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 584BPedM3179752; Thu, 4 Sep 2025 06:26:07 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , CC: Subject: [PATCH v4 3/4] arm64: dts: ti: k3-pinctrl: Add the remaining macros Date: Thu, 4 Sep 2025 16:55:37 +0530 Message-ID: <20250904112538.529857-4-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904112538.529857-1-a-kaur@ti.com> References: <20250904112538.529857-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add the drive strength, schmitt trigger enable macros to pinctrl file. Add the missing macros for DeepSleep configuration control referenced from "Table 14-6172. Description Of The Pad Configuration Register Bits" in AM625 TRM[0]. Add some DeepSleep macros to provide combinations that can be used directly in device tree files example PIN_DS_OUTPUT_LOW that configures pin to be output and also sets its value to 0. [0] https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf Signed-off-by: Akashdeep Kaur Reviewed-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 47 ++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index c0f09be8d3f9..7c5b5783769c 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -3,15 +3,20 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti= .com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H =20 +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define ISO_OVERRIDE_EN_SHIFT (22) +#define ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) #define FORCE_DS_EN_SHIFT (15) #define DS_EN_SHIFT (24) @@ -19,6 +24,7 @@ #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) =20 /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -33,6 +39,29 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) =20 +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENAB= LE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENAB= LE) + +#define DS_STATE_EN (1 << DS_EN_SHIFT) +#define DS_STATE_DIS (0 << DS_EN_SHIFT) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +/* Configuration to enable wake-up on pin activity */ +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -53,6 +82,10 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) =20 +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) @@ -65,6 +98,18 @@ #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_Z= ERO) +#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_O= NE) +#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) + +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKU= P_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKU= P_LEVEL_HIGH) +#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) =20 /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) --=20 2.34.1 From nobody Fri Oct 3 06:36:43 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 910012FF661; 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charset="utf-8" Currently, DS_IO_OVERRIDE_EN_SHIFT macro is not defined anywhere but used for defining other macro. Replace this undefined macro with valid macro. Rename the existing macro to reflect the actual behavior. Signed-off-by: Akashdeep Kaur Reviewed-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index 7c5b5783769c..36bb403d718e 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -88,8 +88,8 @@ =20 #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) #define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) --=20 2.34.1