From nobody Fri Oct 3 06:34:56 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [4.193.249.245]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 442F32BDC09; Thu, 4 Sep 2025 09:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=4.193.249.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756976488; cv=none; b=A/7u8GF7GY9sR0QehOyWjxJf9XDhZLD+8oBzVdNi/9N+bWOWYoGVPnHANO7igW2u/cRFd9I9M9iia+f6cLiiKgEOY/w78GTiarRoW9uIiZaU4qGnRCuxRWSFXyxrL2M4wwLVfTeV9DW4C/t4NO++YqQzyYCNOjQ5WfC9dCzcBYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756976488; c=relaxed/simple; bh=/bqpS8Q6zKJe1QRdSTpgfyrRwX4Se1MPaEiV4K7DawQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qexX6WlR5NBaEc0rbt6PxYjaYoPvrJDi4jqxVSxSQ4BLww+HQyPoI7aGJcQxvigPHsqkTtAFe9qh5CyvfvlhGRsEC4bo6s5LEmxo/L5mHufiUFa4GPm/ILr0EGxop/k2SxxdXrOPJaFUgXLLrvIALynyqQCYrbP+mJ3LstjmnM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=4.193.249.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005182LT.eswin.cn (unknown [10.12.96.155]) by app1 (Coremail) with SMTP id TAJkCgAXLg9LVbloAGXIAA--.31039S2; Thu, 04 Sep 2025 17:01:01 +0800 (CST) From: weishangjuan@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, yong.liang.choong@linux.intel.com, vladimir.oltean@nxp.com, rmk+kernel@armlinux.org.uk, faizal.abdul.rahim@linux.intel.com, prabhakar.mahadev-lad.rj@bp.renesas.com, inochiama@gmail.com, jan.petrous@oss.nxp.com, jszhang@kernel.org, p.zabel@pengutronix.de, boon.khai.ng@altera.com, 0x1207@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, emil.renner.berthing@canonical.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, lizhi2@eswincomputing.com, pinkesh.vaghela@einfochips.com, Shangjuan Wei Subject: [PATCH v5 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC Date: Thu, 4 Sep 2025 17:00:55 +0800 Message-Id: <20250904090055.2546-1-weishangjuan@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250904085913.2494-1-weishangjuan@eswincomputing.com> References: <20250904085913.2494-1-weishangjuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgAXLg9LVbloAGXIAA--.31039S2 X-Coremail-Antispam: 1UD129KBjvJXoWxCr4kJF18CFWUAr43GFyDKFg_yoWrGr1kpF WkCrW5Jr4fXr1fXa1UtF10kFn3ta1DCr1Ykrn7J3Waq3s0qa90qw4ayFy5Ga43Cr47ZFy5 WFWYqayxAw12k3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Wrv_Gr1UMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRiWrW5UUUUU== X-CM-SenderInfo: pzhl2xxdqjy31dq6v25zlqu0xpsx3x1qjou0bp/ Content-Type: text/plain; charset="utf-8" From: Shangjuan Wei Add ESWIN EIC7700 Ethernet controller, supporting clock configuration, delay adjustment and speed adaptive functions. Signed-off-by: Zhi Li Signed-off-by: Shangjuan Wei Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/eswin,eic7700-eth.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/eswin,eic7700-eth= .yaml diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b= /Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml new file mode 100644 index 000000000000..9771fed9604e --- /dev/null +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SOC Eth Controller + +maintainers: + - Shuang Liang + - Zhi Li + - Shangjuan Wei + +description: + The eth controller registers are part of the syscrg block on + the EIC7700 SoC. + +select: + properties: + compatible: + contains: + enum: + - eswin,eic7700-qos-eth + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-qos-eth + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + + clocks: + items: + - description: AXI clock + - description: Configuration clock + - description: GMAC main clock + - description: Tx clock + + clock-names: + items: + - const: axi + - const: cfg + - const: stmmaceth + - const: tx + + resets: + maxItems: 1 + + reset-names: + items: + - const: stmmaceth + + rx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + tx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + eswin,hsp-sp-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: Phandle to HSP(High-Speed Peripheral) device + - description: Offset of phy control register for internal + or external clock selection + - description: Offset of AXI clock controller Low-Power request + register + - description: Offset of register controlling TX/RX clock delay + description: | + High-Speed Peripheral device needed to configure clock selection, + clock low-power mode and clock delay. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + - resets + - reset-names + - rx-internal-delay-ps + - tx-internal-delay-ps + - eswin,hsp-sp-csr + +unevaluatedProperties: false + +examples: + - | + ethernet@50400000 { + compatible =3D "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; + reg =3D <0x50400000 0x10000>; + clocks =3D <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 193>; + clock-names =3D "axi", "cfg", "stmmaceth", "tx"; + interrupt-parent =3D <&plic>; + interrupts =3D <61>; + interrupt-names =3D "macirq"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&phy0>; + resets =3D <&reset 95>; + reset-names =3D "stmmaceth"; + rx-internal-delay-ps =3D <200>; + tx-internal-delay-ps =3D <200>; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,aal; + snps,fixed-burst; + snps,tso; + stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <2>; + snps,wr_osr_lmt =3D <2>; + }; + }; --=20 2.17.1 From nobody Fri Oct 3 06:34:56 2025 Received: from zg8tmty1ljiyny4xntuumtyw.icoremail.net (zg8tmty1ljiyny4xntuumtyw.icoremail.net [165.227.155.160]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1327B1E6DC5; Thu, 4 Sep 2025 09:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005182LT.eswin.cn (unknown [10.12.96.155]) by app1 (Coremail) with SMTP id TAJkCgC32xFnVbloOGXIAA--.39044S2; Thu, 04 Sep 2025 17:01:31 +0800 (CST) From: weishangjuan@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, yong.liang.choong@linux.intel.com, vladimir.oltean@nxp.com, rmk+kernel@armlinux.org.uk, faizal.abdul.rahim@linux.intel.com, prabhakar.mahadev-lad.rj@bp.renesas.com, inochiama@gmail.com, jan.petrous@oss.nxp.com, jszhang@kernel.org, p.zabel@pengutronix.de, boon.khai.ng@altera.com, 0x1207@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, emil.renner.berthing@canonical.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, lizhi2@eswincomputing.com, pinkesh.vaghela@einfochips.com, Shangjuan Wei Subject: [PATCH v5 2/2] ethernet: eswin: Add eic7700 ethernet driver Date: Thu, 4 Sep 2025 17:01:25 +0800 Message-Id: <20250904090125.2598-1-weishangjuan@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250904085913.2494-1-weishangjuan@eswincomputing.com> References: <20250904085913.2494-1-weishangjuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgC32xFnVbloOGXIAA--.39044S2 X-Coremail-Antispam: 1UD129KBjvJXoW3tF45CrWxKr1rZr13KFyUZFb_yoWDWF45pF W8Aa4Yqrnrtr1fK398JF40vas5Ka12gF1Y9ryfJ3Z3ZFZ0yrZ8Zw4ktFyYkFykJr95uw13 Ga1UAFWxuFn0k3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Wrv_Gr1UMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRiWrW5UUUUU== X-CM-SenderInfo: pzhl2xxdqjy31dq6v25zlqu0xpsx3x1qjou0bp/ From: Shangjuan Wei Add Ethernet controller support for Eswin's eic7700 SoC. The driver provides management and control of Ethernet signals for the eiC7700 series chips. Signed-off-by: Zhi Li Signed-off-by: Shangjuan Wei --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 250 ++++++++++++++++++ 3 files changed, 262 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..a13b15ce1abd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -67,6 +67,17 @@ config DWMAC_ANARION This selects the Anarion SoC glue layer support for the stmmac driver. +config DWMAC_EIC7700 + tristate "Support for Eswin eic7700 ethernet driver" + select CRC32 + select MII + depends on OF && HAS_DMA && ARCH_ESWIN || COMPILE_TEST + help + This driver supports the Eswin EIC7700 Ethernet controller, + which integrates Synopsys DesignWare QoS features. It enables + high-speed networking with DMA acceleration and is optimized + for embedded systems. + config DWMAC_INGENIC tristate "Ingenic MAC support" default MACH_INGENIC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..f4ec5fc16571 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) +=3D stmmac_selftests.o # Ordering matters. Generic driver must be last. obj-$(CONFIG_STMMAC_PLATFORM) +=3D stmmac-platform.o obj-$(CONFIG_DWMAC_ANARION) +=3D dwmac-anarion.o +obj-$(CONFIG_DWMAC_EIC7700) +=3D dwmac-eic7700.o obj-$(CONFIG_DWMAC_INGENIC) +=3D dwmac-ingenic.o obj-$(CONFIG_DWMAC_IPQ806X) +=3D dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) +=3D dwmac-lpc18xx.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-eic7700.c new file mode 100644 index 000000000000..b6c99562ccc5 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Eswin DWC Ethernet linux driver + * + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd. + * + * Authors: + * Zhi Li + * Shuang Liang + * Shangjuan Wei + */ + +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +/* eth_phy_ctrl_offset eth0:0x100 */ +#define EIC7700_ETH_TX_CLK_SEL BIT(16) +#define EIC7700_ETH_PHY_INTF_SELI BIT(0) + +/* eth_axi_lp_ctrl_offset eth0:0x108 */ +#define EIC7700_ETH_CSYSREQ_VAL BIT(0) + +/* + * TX/RX Clock Delay Bit Masks: + * - TX Delay: bits [14:8] =E2=80=94 TX_CLK delay (unit: 0.1ns per bit) + * - RX Delay: bits [30:24] =E2=80=94 RX_CLK delay (unit: 0.1ns per bit) + */ +#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8) +#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24) + +#define EIC7700_MAX_DELAY_UNIT 0x7F + +static const char * const eic7700_clk_names[] =3D { + "tx", "axi", "cfg", +}; + +struct eic7700_qos_priv { + struct plat_stmmacenet_data *plat_dat; + struct device *dev; + struct regmap *hsp_regmap; + u32 tx_delay_ps; + u32 rx_delay_ps; +}; + +/** + * eic7700_apply_delay - Apply TX or RX delay to a register value. + * @delay_ps: Delay in picoseconds, converted to 0.1ns units. + * @reg: Pointer to register value to update in-place. + * @is_rx: True for RX delay (bits 30:24), false for TX delay (bits 14:= 8). + * + * Converts delay from ps to 0.1ns units, capped by EIC7700_MAX_DELAY_UNIT. + * Updates only the RX or TX delay field (using FIELD_PREP), leaving all + * other bits in *@reg unchanged. + */ +static void eic7700_apply_delay(u32 delay_ps, u32 *reg, bool is_rx) +{ + u32 val =3D min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + + if (is_rx) { + *reg &=3D ~EIC7700_ETH_RX_ADJ_DELAY; + *reg |=3D FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); + } else { + *reg &=3D ~EIC7700_ETH_TX_ADJ_DELAY; + *reg |=3D FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); + } +} + +static int eic7700_clks_config(void *priv, bool enabled) +{ + struct eic7700_qos_priv *dwc =3D (struct eic7700_qos_priv *)priv; + struct plat_stmmacenet_data *plat =3D dwc->plat_dat; + int ret =3D 0; + + if (enabled) + ret =3D clk_bulk_prepare_enable(plat->num_clks, plat->clks); + else + clk_bulk_disable_unprepare(plat->num_clks, plat->clks); + + return ret; +} + +static int eic7700_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct eic7700_qos_priv *dwc_priv; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_phy_ctrl_regset; + u32 eth_rxd_dly_offset; + u32 eth_dly_param =3D 0; + int i, ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat), + "dt configuration failed\n"); + + dwc_priv =3D devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL); + if (!dwc_priv) + return -ENOMEM; + + dwc_priv->dev =3D &pdev->dev; + + /* Read rx-internal-delay-ps and update rx_clk delay */ + if (!of_property_read_u32(pdev->dev.of_node, + "rx-internal-delay-ps", + &dwc_priv->rx_delay_ps)) { + eic7700_apply_delay(dwc_priv->rx_delay_ps, + ð_dly_param, true); + } else { + dev_warn(&pdev->dev, "can't get rx-internal-delay-ps\n"); + } + + /* Read tx-internal-delay-ps and update tx_clk delay */ + if (!of_property_read_u32(pdev->dev.of_node, + "tx-internal-delay-ps", + &dwc_priv->tx_delay_ps)) { + eic7700_apply_delay(dwc_priv->tx_delay_ps, + ð_dly_param, false); + } else { + dev_warn(&pdev->dev, "can't get tx-internal-delay-ps\n"); + } + + dwc_priv->hsp_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_nod= e, + "eswin,hsp-sp-csr"); + if (IS_ERR(dwc_priv->hsp_regmap)) + return dev_err_probe(&pdev->dev, + PTR_ERR(dwc_priv->hsp_regmap), + "Failed to get hsp-sp-csr regmap\n"); + + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 1, ð_phy_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_phy_ctrl_offset\n"); + + regmap_read(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, + ð_phy_ctrl_regset); + eth_phy_ctrl_regset |=3D + (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI); + regmap_write(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, + eth_phy_ctrl_regset); + + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 2, ð_axi_lp_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_axi_lp_ctrl_offset\n"); + + regmap_write(dwc_priv->hsp_regmap, eth_axi_lp_ctrl_offset, + EIC7700_ETH_CSYSREQ_VAL); + + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 3, ð_rxd_dly_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_rxd_dly_offset\n"); + + regmap_write(dwc_priv->hsp_regmap, eth_rxd_dly_offset, + eth_dly_param); + + plat_dat->num_clks =3D ARRAY_SIZE(eic7700_clk_names); + plat_dat->clks =3D devm_kcalloc(&pdev->dev, + plat_dat->num_clks, + sizeof(*plat_dat->clks), + GFP_KERNEL); + if (!plat_dat->clks) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(eic7700_clk_names); i++) + plat_dat->clks[i].id =3D eic7700_clk_names[i]; + + ret =3D devm_clk_bulk_get_optional(&pdev->dev, + plat_dat->num_clks, + plat_dat->clks); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "Failed to get clocks\n"); + + plat_dat->clk_tx_i =3D stmmac_pltfr_find_clk(plat_dat, "tx"); + plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; + plat_dat->bsp_priv =3D dwc_priv; + plat_dat->clks_config =3D eic7700_clks_config; + dwc_priv->plat_dat =3D plat_dat; + + ret =3D eic7700_clks_config(dwc_priv, true); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "error enable clock\n"); + + ret =3D stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) { + eic7700_clks_config(dwc_priv, false); + return dev_err_probe(&pdev->dev, + ret, + "Failed to driver probe\n"); + } + + return ret; +} + +static void eic7700_dwmac_remove(struct platform_device *pdev) +{ + struct eic7700_qos_priv *dwc_priv =3D get_stmmac_bsp_priv(&pdev->dev); + + stmmac_pltfr_remove(pdev); + eic7700_clks_config(dwc_priv, false); +} + +static const struct of_device_id eic7700_dwmac_match[] =3D { + { .compatible =3D "eswin,eic7700-qos-eth" }, + { } +}; +MODULE_DEVICE_TABLE(of, eic7700_dwmac_match); + +static struct platform_driver eic7700_dwmac_driver =3D { + .probe =3D eic7700_dwmac_probe, + .remove =3D eic7700_dwmac_remove, + .driver =3D { + .name =3D "eic7700-eth-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D eic7700_dwmac_match, + }, +}; +module_platform_driver(eic7700_dwmac_driver); + +MODULE_AUTHOR("Zhi Li "); +MODULE_AUTHOR("Shuang Liang "); +MODULE_AUTHOR("Shangjuan Wei "); +MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver"); +MODULE_LICENSE("GPL"); -- 2.17.1