From nobody Fri Oct 3 07:43:43 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A13DA2C1780 for ; Thu, 4 Sep 2025 08:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756974147; cv=none; b=sA15Ywmti4EzGkLCxvFm5jwBPXm3tVvGEtm2r8G5iAs5zgZ4b6f9AneBLcTYfCQVU9rMAdX5ifoAk/znwnz9Uxw0uS99Frcu0YPYU6yMTbHn/elriphq+BqVTa5KQNR2MU28BZvX7v6R659IYJviRklVEekWEWim0pXJyCN7ba4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756974147; c=relaxed/simple; bh=ldMbMsCAETYgAHNKtTSOJhI8Y1JaDR0BSRu+T7ysGwA=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gbwkK3kGybxUi73sChUJb2RhcT5vDcmaErnWNYIgoxmccCjcCYuHKPCYJYis5sxEsxh4l6Mku6L1D8tFLewnD3VQeK1wcGEUN5SchI8acjX3NalRrBiiJBalTCXC7LhYsX2pOmOXAuEqWBHR1mj/Avja1o2lWd0KaTeDlR6Pen4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=p0XJXJpU; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="p0XJXJpU" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5848M4gg3033432; Thu, 4 Sep 2025 03:22:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756974124; bh=O4dxI+zSPIUICuyhN3AeF9/dvxip1x5tnLjCqVOKHU4=; h=From:To:Subject:Date:In-Reply-To:References; b=p0XJXJpUr0oOE8obbMiAB9DZ3oiqA/C73c9o4lanuJmliUgufSJY+/w9/MWc3k728 l45X2uOH7T4PJn0HnAQnM4e/faMY7BC4aNn53Y/IgzUTOcdoOtxXRkoIabGODQUJfp A60D5dEg9rptHxsfcdR4YZ+O5Auo7z6bVeURdXj4= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5848M4fa730732 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 4 Sep 2025 03:22:04 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 03:22:04 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 03:22:03 -0500 Received: from hkshenoy.dhcp.ti.com (hkshenoy.dhcp.ti.com [172.24.235.208]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5848LpgG2963848; Thu, 4 Sep 2025 03:22:00 -0500 From: Harikrishna Shenoy To: , , , , , , , , , , , Subject: [PATCH RESEND 2/3] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine Date: Thu, 4 Sep 2025 13:51:50 +0530 Message-ID: <20250904082151.2929189-3-h-shenoy@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904082151.2929189-1-h-shenoy@ti.com> References: <20250904082151.2929189-1-h-shenoy@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar Do read-modify-write so that we re-use the characterized reset value as specified in TRM [1] to program calibration wait time which defines number of cycles to wait for after startup state machine is in bandgap enable state. This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's AM62L and J721E SoC since earlier calibration wait time was getting overwritten to zero value thus failing the PLL to lockup and causing timeout. [1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2): Link: https://www.ti.com/lit/pdf/spruj83 Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Reviewed-by: Tomi Valkeinen Signed-off-by: Devarsh Thakkar Tested-by: Harikrishna Shenoy Signed-off-by: Harikrishna Shenoy --- Rebased on top of linux-next and resend. Link to original patch- https://lore.kernel.org/all/20250704125915.1224738-= 3-devarsht@ti.com/ drivers/phy/cadence/cdns-dphy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dph= y.c index da8de0a9d086..24a25606996c 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -30,6 +30,7 @@ =20 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) =20 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) @@ -410,7 +411,8 @@ static int cdns_dphy_power_on(struct phy *phy) writel(reg, dphy->regs + DPHY_BAND_CFG); =20 /* Start TX state machine. */ - writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, + reg =3D readl(dphy->regs + DPHY_CMN_SSM); + writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX= _MODE_EN, dphy->regs + DPHY_CMN_SSM); =20 ret =3D cdns_dphy_wait_for_pll_lock(dphy); --=20 2.34.1