From nobody Fri Oct 3 07:40:20 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [13.76.142.27]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2674279918; Thu, 4 Sep 2025 06:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.76.142.27 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756967957; cv=none; b=ImluhlRRo/v3M9BhKfbyL0LYXMDRnh76V6MbEnZ96NOU3irhQErVTcci21mfvqBOvnFvPD8YAa5pxOxYLc9bzoMJd2IS+zvbMT8VXhEYiOZJ0IFdJvZ0isI8/+ANrD8TiWpDpdwL9SnRuzVfvhx19oPOTdbJo2yZIAFqBf9uSuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756967957; c=relaxed/simple; bh=su3dTLyt2rW1U5z98/OSraZOzlBbdjJC5eAsqGYFPpA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A4jx9PWfSwSEWZzTdZcZep110LW7TAi3w0NnfnUNhEWbL3U9F6MaudiKUSqkWeoSa3novo/qHpYV6vrPcCYtvkPm/9IluXQwW7NstoNWR/0giPuyEezBoj/b4Q+c2MG6JSqxRLPMTO+eHOlYQi2FECHFfhbOQiL35gWbeDJNxfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=13.76.142.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0006800LT.eswin.cn (unknown [10.12.96.77]) by app2 (Coremail) with SMTP id TQJkCgCHJpUANLlocUvIAA--.53346S2; Thu, 04 Sep 2025 14:38:59 +0800 (CST) From: Yulin Lu To: dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, linux-phy@lists.infradead.org Cc: ningyu@eswincomputing.com, zhengyu@eswincomputing.com, linmin@eswincomputing.com, huangyifeng@eswincomputing.com, fenglin@eswincomputing.com, lianghujun@eswincomputing.com, Yulin Lu Subject: [PATCH v3 3/3] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver Date: Thu, 4 Sep 2025 14:38:53 +0800 Message-Id: <20250904063853.1546-1-luyulin@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250904063427.1954-1-luyulin@eswincomputing.com> References: <20250904063427.1954-1-luyulin@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgCHJpUANLlocUvIAA--.53346S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtF43tw4rZw4rGw1fAr45Awb_yoWfAry8pF 4DCFyUWrWktF47Ka93J3WqyF13GrnFqrya9FyDKasIvFW3Jr18Za9Iqa95tFn0vrn7X3yU K3sYqFy7Ga15Aw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9C14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxK x2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRJPE-UUUUU= X-CM-SenderInfo: pox13z1lq6v25zlqu0xpsx3x1qjou0bp/ Content-Type: text/plain; charset="utf-8" Created the eswin phy driver directory and added support for the SATA phy driver on the EIC7700 SoC platform. Signed-off-by: Yulin Lu --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 205 +++++++++++++++++++++++++++ 5 files changed, 223 insertions(+) create mode 100644 drivers/phy/eswin/Kconfig create mode 100644 drivers/phy/eswin/Makefile create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d2..e82ebcfe534a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" +source "drivers/phy/eswin/Kconfig" source "drivers/phy/freescale/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/ingenic/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac468..ed7444949259 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -17,6 +17,7 @@ obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ + eswin/ \ freescale/ \ hisilicon/ \ ingenic/ \ diff --git a/drivers/phy/eswin/Kconfig b/drivers/phy/eswin/Kconfig new file mode 100644 index 000000000000..3fcd76582c3b --- /dev/null +++ b/drivers/phy/eswin/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Eswin platforms +# +config PHY_EIC7700_SATA + tristate "eic7700 Sata SerDes/PHY driver" + depends on ARCH_ESWIN || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + help + Enable this to support SerDes/Phy found on ESWIN's + EIC7700 SoC.This Phy supports SATA 1.5 Gb/s, + SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. + It supports one SATA host port to accept one SATA device. diff --git a/drivers/phy/eswin/Makefile b/drivers/phy/eswin/Makefile new file mode 100644 index 000000000000..db08c66be812 --- /dev/null +++ b/drivers/phy/eswin/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_EIC7700_SATA) +=3D phy-eic7700-sata.o diff --git a/drivers/phy/eswin/phy-eic7700-sata.c b/drivers/phy/eswin/phy-e= ic7700-sata.c new file mode 100644 index 000000000000..cf97365bf841 --- /dev/null +++ b/drivers/phy/eswin/phy-eic7700-sata.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ESWIN SATA PHY driver + * + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: Yulin Lu + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SATA_CLK_CTRL 0x0 +#define SATA_AXI_LP_CTRL 0x08 +#define SATA_MPLL_CTRL 0x20 +#define SATA_P0_PHY_STAT 0x24 +#define SATA_PHY_CTRL0 0x28 +#define SATA_PHY_CTRL1 0x2c +#define SATA_REG_CTRL 0x34 +#define SATA_REF_CTRL1 0x38 +#define SATA_LOS_IDEN 0x3c +#define SATA_RESET_CTRL 0x40 + +#define SATA_SYS_CLK_EN BIT(28) +#define SATA_PHY_RESET BIT(0) +#define SATA_PORT_RESET BIT(1) +#define SATA_CLK_RST_SOURCE_PHY BIT(0) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16) +#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0) +#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8) +#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16) +#define SATA_LOS_LEVEL_MASK GENMASK(4, 0) +#define SATA_LOS_BIAS_MASK GENMASK(18, 16) +#define SATA_M_CSYSREQ BIT(0) +#define SATA_S_CSYSREQ BIT(16) +#define SATA_REF_REPEATCLK_EN BIT(0) +#define SATA_REF_USE_PAD BIT(20) +#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16) +#define SATA_P0_PHY_READY BIT(0) + +#define PHY_READY_TIMEOUT (usecs_to_jiffies(4000)) + +struct eic7700_sata_phy { + struct phy *phy; + void __iomem *regs; +}; + +static int wait_for_phy_ready(void __iomem *base, u32 reg, u32 checkbit, + u32 status) +{ + unsigned long start =3D jiffies; + unsigned long timeout =3D start + PHY_READY_TIMEOUT; + + while (time_before(start, timeout)) { + if ((readl(base + reg) & checkbit) =3D=3D status) + return 0; + usleep_range(50, 70); + } + + return -EFAULT; +} + +static int eic7700_sata_phy_init(struct phy *phy) +{ + struct eic7700_sata_phy *sata_phy =3D phy_get_drvdata(phy); + u32 val; + int ret; + + /* + * The SATA_CLK_CTRL register offset controls the pmalive, rxoob, + * and rbc clocks gate provided by the PHY through the HSP bus, + * and it is not registered in the clock tree. + */ + val =3D readl(sata_phy->regs + SATA_CLK_CTRL); + val |=3D SATA_SYS_CLK_EN; + writel(val, sata_phy->regs + SATA_CLK_CTRL); + + writel(SATA_CLK_RST_SOURCE_PHY, sata_phy->regs + SATA_REF_CTRL1); + writel(FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK, 0x42) | + FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK, 0x46) | + FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK, 0x73), + sata_phy->regs + SATA_PHY_CTRL0); + writel(FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK, 0x5) | + FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK, 0x5) | + FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK, 0x8), + sata_phy->regs + SATA_PHY_CTRL1); + writel(FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) | + FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2), + sata_phy->regs + SATA_LOS_IDEN); + writel(SATA_M_CSYSREQ | SATA_S_CSYSREQ, + sata_phy->regs + SATA_AXI_LP_CTRL); + writel(SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD, + sata_phy->regs + SATA_REG_CTRL); + writel(FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c), + sata_phy->regs + SATA_MPLL_CTRL); + usleep_range(15, 20); + + /* + * The SATA_RESET_CTRL register offset controls reset/deassert + * for both the port and the PHY through the HSP bus, + * and it is not registered in the reset tree. + */ + val =3D readl(sata_phy->regs + SATA_RESET_CTRL); + val &=3D ~(SATA_PHY_RESET | SATA_PORT_RESET); + writel(val, sata_phy->regs + SATA_RESET_CTRL); + + ret =3D wait_for_phy_ready(sata_phy->regs, SATA_P0_PHY_STAT, + SATA_P0_PHY_READY, 1); + if (ret < 0) + dev_err(&sata_phy->phy->dev, + "PHY READY check failed\n"); + return ret; +} + +static int eic7700_sata_phy_exit(struct phy *phy) +{ + struct eic7700_sata_phy *sata_phy =3D phy_get_drvdata(phy); + u32 val; + + val =3D readl(sata_phy->regs + SATA_RESET_CTRL); + val |=3D SATA_PHY_RESET | SATA_PORT_RESET; + writel(val, sata_phy->regs + SATA_RESET_CTRL); + + val =3D readl(sata_phy->regs + SATA_CLK_CTRL); + val &=3D ~SATA_SYS_CLK_EN; + writel(val, sata_phy->regs + SATA_CLK_CTRL); + + return 0; +} + +static const struct phy_ops eic7700_sata_phy_ops =3D { + .init =3D eic7700_sata_phy_init, + .exit =3D eic7700_sata_phy_exit, + .owner =3D THIS_MODULE, +}; + +static int eic7700_sata_phy_probe(struct platform_device *pdev) +{ + struct eic7700_sata_phy *sata_phy; + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + u32 val; + int ret; + + sata_phy =3D devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL); + if (!sata_phy) + return -ENOMEM; + + sata_phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sata_phy->regs)) + return PTR_ERR(sata_phy->regs); + + dev_set_drvdata(dev, sata_phy); + + sata_phy->phy =3D devm_phy_create(dev, NULL, &eic7700_sata_phy_ops); + if (IS_ERR(sata_phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + ret =3D PTR_ERR(sata_phy->phy); + goto clk_disable; + } + + phy_set_drvdata(sata_phy->phy, sata_phy); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) { + ret =3D PTR_ERR(phy_provider); + goto clk_disable; + } + + return 0; + +clk_disable: + val =3D readl(sata_phy->regs + SATA_CLK_CTRL); + val &=3D ~SATA_SYS_CLK_EN; + writel(val, sata_phy->regs + SATA_CLK_CTRL); + + return ret; +} + +static const struct of_device_id eic7700_sata_phy_of_match[] =3D { + { .compatible =3D "eswin,eic7700-sata-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match); + +static struct platform_driver eic7700_sata_phy_driver =3D { + .probe =3D eic7700_sata_phy_probe, + .driver =3D { + .of_match_table =3D eic7700_sata_phy_of_match, + .name =3D "eic7700-sata-phy", + } +}; +module_platform_driver(eic7700_sata_phy_driver); + +MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC"); +MODULE_AUTHOR("Yulin Lu "); +MODULE_LICENSE("GPL"); --=20 2.25.1