From nobody Fri Oct 3 07:40:24 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3469584A3E; Thu, 4 Sep 2025 01:35:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756949712; cv=none; b=PhgEZOIbpQrj/Tb8szfkRRdvt3WpkZuqvUQMfZQCXTWpM+f9aE8TqzpnbIfNk+cNX1O2EIzBDhLNLwFxF27sKCZxUGYypml9WPbRFDYenD6/7NWeQ7uwRQYCB8Z+LZiVZdhO2eoG0iMPRQLuLM7iQCaAJvRL2XB4TPwqOlSHJG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756949712; c=relaxed/simple; bh=HGeMJivM5dsvsfLphCbTOUUOtUXXZkF8ad8cC9GU4hI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fXMKD8NwwpxJiGJymV3A5+ui+LiLTCtlrjfwMHAdESgAgXdrcpWkwIixSQ0fLTy+o/MZYkP7X22zWKA8heEhElC1vu/CWjs/D3BOWd0AXZgyPF5NUEmQI8w5sJ607uBc3Y9DH0gAvgzP5frx3NVhTYnnnJPL3UlLyNYkcuw+I2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=gFO/43M0; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="gFO/43M0" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id D4B1822FC2; Thu, 4 Sep 2025 03:35:08 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id qUdN7d7rQUZn; Thu, 4 Sep 2025 03:35:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1756949708; bh=HGeMJivM5dsvsfLphCbTOUUOtUXXZkF8ad8cC9GU4hI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gFO/43M0f9M3/Yy0oZvEW+6YqlswQEZWGrxIJWLDxAVt8d6XD/Z7UAq9UcIpArotv zIlSDESGX92iWRQhOVIFVFwui77TF/bflGBsJf6oHIKf6Z3b0UHhjJiXBaZ9SZIXa1 vf+ZYXo+b7yAKleFAjDtqFkML56yf10ZdO6ELlRrjwPQRA939Hs/2JrZdt3JKzfQWP zll+NCz5hkE8Y8PzF5WFIS0ULHn9z8aXu+4li3PJufnTeUVnEjcmEJ5ECmmF3EYoAw GAdAv4kIsMWi/OgulVWFPywC1wdW+NGrsWXkkeNNCAedHdO/8YxSdwP+AFrWdaoQjK /ZzNn+BaW/Zjw== From: Yao Zi To: Yinbo Zhu , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Philipp Zabel Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi , Krzysztof Kozlowski , Huacai Chen Subject: [PATCH v3 1/3] dt-bindings: gpio: loongson: Document GPIO controller of LS2K0300 SoC Date: Thu, 4 Sep 2025 01:34:36 +0000 Message-ID: <20250904013438.2405-2-ziyao@disroot.org> In-Reply-To: <20250904013438.2405-1-ziyao@disroot.org> References: <20250904013438.2405-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson-2K0300 ships a GPIO controller whose input/output control logic is similar to previous generation of SoCs. Additionally, it acts as an interrupt-controller supporting both level and edge interrupts and has a distinct reset signal. Describe its compatible in devicetree. We enlarge the maximum value of ngpios to 128, since the controller technically supports at most 128 pins, although only 106 are routed out of the package. Properties for interrupt-controllers and resets are introduced and limited as LS2K0300 only. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Huacai Chen Reviewed-by: Linus Walleij --- .../bindings/gpio/loongson,ls-gpio.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml b= /Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml index b68159600e2b..69852444df23 100644 --- a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - loongson,ls2k-gpio + - loongson,ls2k0300-gpio - loongson,ls2k0500-gpio0 - loongson,ls2k0500-gpio1 - loongson,ls2k2000-gpio0 @@ -36,7 +37,7 @@ properties: =20 ngpios: minimum: 1 - maximum: 64 + maximum: 128 =20 "#gpio-cells": const: 2 @@ -49,6 +50,14 @@ properties: minItems: 1 maxItems: 64 =20 + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + resets: + maxItems: 1 + required: - compatible - reg @@ -58,6 +67,23 @@ required: - gpio-ranges - interrupts =20 +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-gpio + then: + required: + - "#interrupt-cells" + - interrupt-controller + - resets + else: + properties: + "#interrupts-cells": false + interrupt-controller: false + resets: false + additionalProperties: false =20 examples: --=20 2.50.1 From nobody Fri Oct 3 07:40:24 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1CE1B4231; Thu, 4 Sep 2025 01:35:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756949719; cv=none; b=QWp2JZ7OEqqnHZNK+PfIA+5VcoeIOQcilgkJgC6KO0vtFIjJnZeeKERK+v36Ny31ze5FULPcCsVQB7fSqVuRHr0+xdfETxRl9vbLG0MSPjvompmMz7HWmRzgKaU1OT/vBKL4wDLwN5J1QhOms8Len9wehZyNiQwnSklJ8ondiyc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756949719; c=relaxed/simple; bh=U7lUJQoVaQULHPf2hCMw+aPmeHh6eYTIuJF64fKrbME=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VL9TglhgnFX528v//bxFVV3SItQlWf2baHZYDFXNB7AtuwB4C/mkBVf2zmr8Agwaf6YcIcgYZzW0kh0HYgJLtIEeJnJLNEzSYIIZApwyPLMWZvuNyjjQoYPoM2t+pIVKo9vWIji+xecYrO5tCnyqSntA1eZWzFB7qE2rq8zJ4nI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=lG9qAuei; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="lG9qAuei" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 9B1A020B30; Thu, 4 Sep 2025 03:35:15 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id ZXmj01bP-rYT; Thu, 4 Sep 2025 03:35:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1756949714; bh=U7lUJQoVaQULHPf2hCMw+aPmeHh6eYTIuJF64fKrbME=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=lG9qAuei6th5BYD1/TqR7tt7lbHgI09oxRbZ7t/myIrrC4jlwVz8y6N1A3W2F2Zxi SzBUmFJU972nt8K854Z3U5BPnMgsknjRh2EgA0sDK9v1P5XwmislLclJZAZATWrYdD 4GjRc7t6oYds5YqYKsFWcJ0KZAdcUjsr9P1WVlXJfAPoIff7qWQ7oYefEei4OKwxj/ idkNUESJbh7xokeXUdBM/p10rBQbRmSC2Haaq2iYJ9dctGBuRsNArPoGhP4SxkZ1NR 7ZyW9Fx/frMRu/rapYTgbI64h40cdP4bwGhyP8yGQ9h2fWEFsiXDs+XcW+HtXVtgiT 9VPTmSHGweskA== From: Yao Zi To: Yinbo Zhu , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Philipp Zabel Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi , Huacai Chen Subject: [PATCH v3 2/3] gpio: loongson-64bit: Add support for Loongson-2K0300 SoC Date: Thu, 4 Sep 2025 01:34:37 +0000 Message-ID: <20250904013438.2405-3-ziyao@disroot.org> In-Reply-To: <20250904013438.2405-1-ziyao@disroot.org> References: <20250904013438.2405-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This controller's input and output logic is similar to previous generations of SoCs. Additionally, it's capable of interrupt masking, and could be configured to detect levels and edges, and is supplied with a distinct reset signal. The interrupt functionality is implemented through an irqchip, whose operations are written with previous generation SoCs in mind and could be reused. Since all Loongson SoCs with similar interrupt capability (LS2K1500, LS2K2000) support byte-control mode, these operations are for byte-control mode only for simplicity. Signed-off-by: Yao Zi Reviewed-by: Huacai Chen Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-loongson-64bit.c | 189 +++++++++++++++++++++++++++-- 2 files changed, 183 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a437fe652dbc..c55173643eb4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -437,6 +437,7 @@ config GPIO_LOONGSON_64BIT depends on LOONGARCH || COMPILE_TEST depends on OF_GPIO select GPIO_GENERIC + select GPIOLIB_IRQCHIP help Say yes here to support the GPIO functionality of a number of Loongson series of chips. The Loongson GPIO controller supports diff --git a/drivers/gpio/gpio-loongson-64bit.c b/drivers/gpio/gpio-loongso= n-64bit.c index 482e64ba9b42..f84f8c537249 100644 --- a/drivers/gpio/gpio-loongson-64bit.c +++ b/drivers/gpio/gpio-loongson-64bit.c @@ -7,6 +7,8 @@ =20 #include #include +#include +#include #include #include #include @@ -14,6 +16,7 @@ #include #include #include +#include #include =20 enum loongson_gpio_mode { @@ -28,6 +31,14 @@ struct loongson_gpio_chip_data { unsigned int out_offset; unsigned int in_offset; unsigned int inten_offset; + unsigned int intpol_offset; + unsigned int intedge_offset; + unsigned int intclr_offset; + unsigned int intsts_offset; + unsigned int intdual_offset; + unsigned int intr_num; + irq_flow_handler_t irq_handler; + const struct irq_chip *girqchip; }; =20 struct loongson_gpio_chip { @@ -137,7 +148,140 @@ static int loongson_gpio_to_irq(struct gpio_chip *chi= p, unsigned int offset) return platform_get_irq(pdev, offset); } =20 -static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chi= p *lgpio, +static void loongson_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); + struct loongson_gpio_chip *lgpio =3D to_loongson_gpio_chip(chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(data); + + writeb(0x1, lgpio->reg_base + lgpio->chip_data->intclr_offset + hwirq); +} + +static void loongson_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); + struct loongson_gpio_chip *lgpio =3D to_loongson_gpio_chip(chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(data); + + writeb(0x0, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); +} + +static void loongson_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); + struct loongson_gpio_chip *lgpio =3D to_loongson_gpio_chip(chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(data); + + writeb(0x1, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); +} + +static int loongson_gpio_irq_set_type(struct irq_data *data, unsigned int = type) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); + struct loongson_gpio_chip *lgpio =3D to_loongson_gpio_chip(chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(data); + u8 pol =3D 0, edge =3D 0, dual =3D 0; + + if ((type & IRQ_TYPE_SENSE_MASK) =3D=3D IRQ_TYPE_EDGE_BOTH) { + edge =3D 1; + dual =3D 1; + irq_set_handler_locked(data, handle_edge_irq); + } else { + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + pol =3D 1; + fallthrough; + case IRQ_TYPE_LEVEL_LOW: + irq_set_handler_locked(data, handle_level_irq); + break; + + case IRQ_TYPE_EDGE_RISING: + pol =3D 1; + fallthrough; + case IRQ_TYPE_EDGE_FALLING: + edge =3D 1; + irq_set_handler_locked(data, handle_edge_irq); + break; + + default: + return -EINVAL; + }; + } + + writeb(pol, lgpio->reg_base + lgpio->chip_data->intpol_offset + hwirq); + writeb(edge, lgpio->reg_base + lgpio->chip_data->intedge_offset + hwirq); + writeb(dual, lgpio->reg_base + lgpio->chip_data->intdual_offset + hwirq); + + return 0; +} + +static void loongson_gpio_ls2k0300_irq_handler(struct irq_desc *desc) +{ + struct loongson_gpio_chip *lgpio =3D irq_desc_get_handler_data(desc); + struct irq_chip *girqchip =3D irq_desc_get_chip(desc); + int i; + + chained_irq_enter(girqchip, desc); + + for (i =3D 0; i < lgpio->chip.gc.ngpio; i++) { + /* + * For the GPIO controller of LS2K0300, interrupts status bits + * may be wrongly set even if the corresponding interrupt is + * disabled. Thus interrupt enable bits are checked along with + * status bits to detect interrupts reliably. + */ + if (readb(lgpio->reg_base + lgpio->chip_data->intsts_offset + i) && + readb(lgpio->reg_base + lgpio->chip_data->inten_offset + i)) + generic_handle_domain_irq(lgpio->chip.gc.irq.domain, i); + } + + chained_irq_exit(girqchip, desc); +} + +static const struct irq_chip loongson_gpio_ls2k0300_irqchip =3D { + .irq_ack =3D loongson_gpio_irq_ack, + .irq_mask =3D loongson_gpio_irq_mask, + .irq_unmask =3D loongson_gpio_irq_unmask, + .irq_set_type =3D loongson_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int loongson_gpio_init_irqchip(struct platform_device *pdev, + struct loongson_gpio_chip *lgpio) +{ + const struct loongson_gpio_chip_data *data =3D lgpio->chip_data; + struct gpio_chip *chip =3D &lgpio->chip.gc; + int i; + + chip->irq.default_type =3D IRQ_TYPE_NONE; + chip->irq.handler =3D handle_bad_irq; + chip->irq.parent_handler =3D data->irq_handler; + chip->irq.parent_handler_data =3D lgpio; + gpio_irq_chip_set_chip(&chip->irq, data->girqchip); + + chip->irq.num_parents =3D data->intr_num; + chip->irq.parents =3D devm_kcalloc(&pdev->dev, data->intr_num, + sizeof(*chip->irq.parents), GFP_KERNEL); + if (!chip->parent) + return -ENOMEM; + + for (i =3D 0; i < data->intr_num; i++) { + chip->irq.parents[i] =3D platform_get_irq(pdev, i); + if (chip->irq.parents[i] < 0) + return dev_err_probe(&pdev->dev, chip->irq.parents[i], + "failed to get IRQ %d\n", i); + } + + for (i =3D 0; i < data->intr_num; i++) { + writeb(0x0, lgpio->reg_base + data->inten_offset + i); + writeb(0x1, lgpio->reg_base + data->intclr_offset + i); + } + + return 0; +} + +static int loongson_gpio_init(struct platform_device *pdev, struct loongso= n_gpio_chip *lgpio, void __iomem *reg_base) { struct gpio_generic_chip_config config; @@ -146,7 +290,7 @@ static int loongson_gpio_init(struct device *dev, struc= t loongson_gpio_chip *lgp lgpio->reg_base =3D reg_base; if (lgpio->chip_data->mode =3D=3D BIT_CTRL_MODE) { config =3D (typeof(config)){ - .dev =3D dev, + .dev =3D &pdev->dev, .sz =3D 8, .dat =3D lgpio->reg_base + lgpio->chip_data->in_offset, .set =3D lgpio->reg_base + lgpio->chip_data->out_offset, @@ -155,7 +299,7 @@ static int loongson_gpio_init(struct device *dev, struc= t loongson_gpio_chip *lgp =20 ret =3D gpio_generic_chip_init(&lgpio->chip, &config); if (ret) { - dev_err(dev, "unable to init generic GPIO\n"); + dev_err(&pdev->dev, "unable to init generic GPIO\n"); return ret; } } else { @@ -164,16 +308,21 @@ static int loongson_gpio_init(struct device *dev, str= uct loongson_gpio_chip *lgp lgpio->chip.gc.get_direction =3D loongson_gpio_get_direction; lgpio->chip.gc.direction_output =3D loongson_gpio_direction_output; lgpio->chip.gc.set =3D loongson_gpio_set; - lgpio->chip.gc.parent =3D dev; + lgpio->chip.gc.parent =3D &pdev->dev; spin_lock_init(&lgpio->lock); } =20 lgpio->chip.gc.label =3D lgpio->chip_data->label; lgpio->chip.gc.can_sleep =3D false; - if (lgpio->chip_data->inten_offset) + if (lgpio->chip_data->girqchip) { + ret =3D loongson_gpio_init_irqchip(pdev, lgpio); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to initialize irqchip\n"); + } else if (lgpio->chip_data->inten_offset) { lgpio->chip.gc.to_irq =3D loongson_gpio_to_irq; + } =20 - return devm_gpiochip_add_data(dev, &lgpio->chip.gc, lgpio); + return devm_gpiochip_add_data(&pdev->dev, &lgpio->chip.gc, lgpio); } =20 static int loongson_gpio_probe(struct platform_device *pdev) @@ -181,6 +330,7 @@ static int loongson_gpio_probe(struct platform_device *= pdev) void __iomem *reg_base; struct loongson_gpio_chip *lgpio; struct device *dev =3D &pdev->dev; + struct reset_control *rst; =20 lgpio =3D devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL); if (!lgpio) @@ -192,7 +342,11 @@ static int loongson_gpio_probe(struct platform_device = *pdev) if (IS_ERR(reg_base)) return PTR_ERR(reg_base); =20 - return loongson_gpio_init(dev, lgpio, reg_base); + rst =3D devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, = NULL); + if (IS_ERR(rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get reset cont= rol\n"); + + return loongson_gpio_init(pdev, lgpio, reg_base); } =20 static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data =3D { @@ -204,6 +358,23 @@ static const struct loongson_gpio_chip_data loongson_g= pio_ls2k_data =3D { .inten_offset =3D 0x30, }; =20 +static const struct loongson_gpio_chip_data loongson_gpio_ls2k0300_data = =3D { + .label =3D "ls2k0300_gpio", + .mode =3D BYTE_CTRL_MODE, + .conf_offset =3D 0x800, + .in_offset =3D 0xa00, + .out_offset =3D 0x900, + .inten_offset =3D 0xb00, + .intpol_offset =3D 0xc00, + .intedge_offset =3D 0xd00, + .intclr_offset =3D 0xe00, + .intsts_offset =3D 0xf00, + .intdual_offset =3D 0xf80, + .intr_num =3D 7, + .irq_handler =3D loongson_gpio_ls2k0300_irq_handler, + .girqchip =3D &loongson_gpio_ls2k0300_irqchip, +}; + static const struct loongson_gpio_chip_data loongson_gpio_ls2k0500_data0 = =3D { .label =3D "ls2k0500_gpio", .mode =3D BIT_CTRL_MODE, @@ -300,6 +471,10 @@ static const struct of_device_id loongson_gpio_of_matc= h[] =3D { .compatible =3D "loongson,ls2k-gpio", .data =3D &loongson_gpio_ls2k_data, }, + { + .compatible =3D "loongson,ls2k0300-gpio", + .data =3D &loongson_gpio_ls2k0300_data, + }, { .compatible =3D "loongson,ls2k0500-gpio0", .data =3D &loongson_gpio_ls2k0500_data0, --=20 2.50.1 From nobody Fri Oct 3 07:40:24 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33C0C45C14; Thu, 4 Sep 2025 01:36:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756949764; cv=none; b=krrST8ldnDPaXCz+sOGJWq5/nsEk4TLIrrGoBvQy4elD3Kz96Qj9v4IO7pPrsPj3q56vsL/wRYL14HiL0+AEUA/oTGJuuXzWjRJqmZ8ppQuQIyzKcfko0mKjg84zTynl9QHREKw8LFtkLzIW4t6259vz5JkCEfzRFwwaFr+ilSY= ARC-Message-Signature: i=1; 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charset="utf-8" Describe Loongson-2K0300's GPIO controller in devicetree. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/= boot/dts/loongson-2k0300.dtsi index 835d3c63537b..60a055b05c44 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi @@ -240,6 +240,26 @@ uart9: serial@16102400 { status =3D "disabled"; }; =20 + gpio: gpio@16104000 { + compatible =3D "loongson,ls2k0300-gpio"; + reg =3D <0x0 0x16104000 0x0 0x4000>; + interrupt-parent =3D <&liointc1>; + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <23 IRQ_TYPE_LEVEL_HIGH>, + <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + ngpios =3D <106>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 106>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + resets =3D <&rst RST_GPIO>; + }; + isa@16400000 { compatible =3D "isa"; #address-cells =3D <2>; --=20 2.50.1