From nobody Fri Oct 3 06:36:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4BC3337686; Thu, 4 Sep 2025 14:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996308; cv=none; b=FXs/a1FDAFwhwpszMVRI2Kp8Eiy9L08obsy3MoCCdzqyVMFPQqGOcrU5i2ycIdyRotsrzCQAKH11/KXf2tPM5yU6opVT6FlsdDGJPDNxGkkl8nuvDoyG9A3vqzNos1O8KhR3/k0gIa60x0qoLmKuzn9wdM/FefQI1N7qH4u6S2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996308; c=relaxed/simple; bh=zrXW+Azg1ybj1TP3cpfO/sfkOo2o+dZsnZjYmLh/LK8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rpErtZlkU2h1VczCFgABIR0rB3HMrMoEYqo9hxhld8oF61UJzo125S0+pBWFfv1DG1SY3/M34+71ru21+TBMGVQLzmHmVlo7opYrEPOOJchLCkNbBDIVt88gkOs2DmB7jFD2yyde1pOIjBNPQJfuN55l3xFvrxt3zb+6CVKk5mw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C02U6Ifz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C02U6Ifz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE8F8C4CEF0; Thu, 4 Sep 2025 14:31:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996308; bh=zrXW+Azg1ybj1TP3cpfO/sfkOo2o+dZsnZjYmLh/LK8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=C02U6IfzCnjPntWkpqfN55JYi+7tR1UyxDv2EQdPD5QKrddYeU6thbFlveMQMiZhz ETaW9jJ5wOR3oGI/1nw0RBNOlg7rSr7+ye9hlOIobPvP/M2Q4JiwM4EtOcYxjpTE8t xtOtcJk1pFzU3v3KDfNUJA2Kec6dpefNVU0cl7TXq5TeptIaX1JTiEwg5l42oaM3mV 9dHjPg/lWCDBpkdEmRpWaR6TVSDjBXubLoZY1A1U/rR432Sk8EKKcJTXHmHoALmRGp o3qVa8wg5oqV4lzYDjZVq8V/W9swLAZQLlayaXKAhquiRkdOlTdgSn7XHWJhfT4MOh 6jkkhdQn0raLw== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:24 +0200 Subject: [PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=1943; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=s0obim0MuDOlL4+p0Nk62B+LrJ+2kyEd8cmm4PAWtK8=; b=P8CmCRAIy6ipK3s7L7LsmaixnjgqhLcOehR6tKYWKSMguFg9xxmQpO8hqbbYYpglR5C5yzqSV 1l4LC8ILpdyAsn/Z7oQUi1WqP3niXbvTVRyCQs5eBoYl+Hn23uuMIfj X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The CCI hosts have both frequency and voltage requirements (which happen to be common across instances on a given SoC, at least so far). Express them by introducing an OPP table and linking it to the hosts. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a3= 58563329a02a4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -391,6 +391,15 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + cci_opp_table: opp-table-cci { + compatible =3D "operating-points-v2"; + + opp-37500000 { + opp-hz =3D /bits/ 64 <37500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + cpu0_opp_table: opp-table-cpu0 { compatible =3D "operating-points-v2"; opp-shared; @@ -4181,6 +4190,7 @@ cci0: cci@ac4a000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci0_default>; @@ -4222,6 +4232,7 @@ cci1: cci@ac4b000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci1_default>; @@ -4262,6 +4273,8 @@ cci2: cci@ac4c000 { "slow_ahb_src", "cpas_ahb", "cci"; + + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci2_default>; @@ -4303,6 +4316,7 @@ cci3: cci@ac4d000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci3_default>; --=20 2.51.0