From nobody Fri Oct 3 06:36:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF2B530CD87; Thu, 4 Sep 2025 14:31:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996292; cv=none; b=KAILQF7CVqZZm3+mf9SbEeaTC5qSzw8QUDoISPEutYmNoiAzpMcL3Y8tMORofCDk95VzTwz+UkkweOLSLs+dLfScz19CwWeP/1GhEAMLpoDEdio+F4jmdTN6viT43AFttCJKo1XnSJ+b01tiEQBm46op00uU3AWa1bjD51f07nU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996292; c=relaxed/simple; bh=iksx8PUQfiuwmD8CdUdvoNW6nuYCyEtsAWPXEBR+z8I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J4Kd5GxTZmwuGkpi9a9hPEAW1PAwjOcZFhKugmVI/wcWadESf0AJveEXqiH1LVFCBWrJS5lZEFlP3wPRoqPPiI4sHo0sVmoQS7iVAJOIvApyuGxemR1aVrWGkb9qrV/hd60tuvyQoZiJNIVmnJ3AngNG5dwvzncVM02yF72DtLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hJkMUK+9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hJkMUK+9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6A46C4CEF1; Thu, 4 Sep 2025 14:31:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996292; bh=iksx8PUQfiuwmD8CdUdvoNW6nuYCyEtsAWPXEBR+z8I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hJkMUK+9GMJnl0bSlsXtF+rt7p26ZrWXxRJltCYUBGfmovUm06w88q5XLNBpCihH8 o/KnOQqpcT0vLdPl/Frmp3FEN013iQ+VMsUiwmWl9pQY6TOoMSja62PfkByzqnFFnN PKqMuJ9T8cthii85/A8mPX0JQ5+tGIYwWOki39lrkD46dtefZGdUOABpvcFMrwaz+O DaBM2zRgraQVRdyynIzY/f1gFDI3ZPUoyvjIBrXTb65ow4M8IC1CraFsdvxFc6tN01 vXwdv3PulCFKe2lk/Z6Cs0a820YoDag7VlPsTYrn3Z+Aaer0+0fvQd1uYTkX1/MA2N mucytd3LwjZRA== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:20 +0200 Subject: [PATCH 1/5] arm64: dts: qcom: sc8280xp: Fix CCI3 interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-1-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=1021; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=n6oILZSJgSYg8kPWee79+SwLLdbG2n116e+YMKfn3+g=; b=ePjBofrdxpcTUHpZ01kswVQ7eurRMb8hHvDzjkCHQFfN0exoZlq2ybDXX3wtLMIhJKZ5uXjmB luSR+UCFSlJBO5snutg5G2pMWoyT2qsPPFxcBQ/iagqJZ1G6X/zQR+0 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio This was evidently wrong, as exemplified by the core failing to reset at probe (which would be completed by the IRQ firing). Fix it. Fixes: 7cfa2e758bf4 ("arm64: dts: qcom: sc8280xp: camss: Add CCI definition= s") Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 225233a37a4fd9f3d65735915c0338a993a322d1..18b5cb441f955f7a91204376e05= 536b203f3e28b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4292,7 +4292,7 @@ cci3: cci@ac4d000 { compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg =3D <0 0x0ac4d000 0 0x1000>; =20 - interrupts =3D ; + interrupts =3D ; =20 clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_SLOW_AHB_CLK_SRC>, --=20 2.51.0 From nobody Fri Oct 3 06:36:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 857EA31352F; Thu, 4 Sep 2025 14:31:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996296; cv=none; b=s6H397hupkicHUD+xYHQIfPAAY7ESXcym1YNTnyLv7TuLIYSd5+dWQg5hX0r3EfBX8vl0UBn1mVAVAa9D5iRrJ0ZNHPW4ig5JA/LcLiHgQZyieKE/sNZP17BU0LONqQp6YcMmTZjaXtY+68T6QKvs5jsGbjeyIg8yH4D28m8VIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996296; c=relaxed/simple; bh=ISIb2YxiCXzHSDHlaC2Prm4WI22Bzfj830rd9uxgk5M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OstAgQUdGhvAQNT089kbZa/R8zM1jkxGn6KXLwlpf16wBxlvXdV4WI4CscgwoMxKMGWb3x1g7AxNZbLTxXeJ7itxa6fffJ/FkTi9VbxHwtcVToeSpxkc+TfUTTe7TGvb/T90kwJXAk3zVgtIPkc+3MaMkx8/HFyGiyISoCZLDEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jXbp4Xix; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jXbp4Xix" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD378C4CEF0; Thu, 4 Sep 2025 14:31:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996296; bh=ISIb2YxiCXzHSDHlaC2Prm4WI22Bzfj830rd9uxgk5M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jXbp4XixaqUdEcHeYRV6P/gLicEScPkDcNtLmQrPJBZ72LsGha8hs3PSIsRibdgSJ 5SaczWW7C9ctOvAg25N7VCy7VeOyeJj478C8R43C1zJm9ur0P4MZZ2mN0+TTELfzAj PWYTnKVKYbtU9+bq8dZqiAO1VWzpp19h9Fz2XVi2fkr2no10ZqKgqwroF+lIZpkiH1 zJr0LOodB7MJmDXxzoikw0162gNV0yTBh6JbKQdMQb3X6/3U+x890T5IDwS8j53RMI Nzu7bKVkRm9xyr2aY3tUIVXToNNOGCUSjQFhXQpbkmFTYHetpJ18zrfSL+0AKg0T5A QYHzUNNvgESOg== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:21 +0200 Subject: [PATCH 2/5] dt-bindings: i2c: qcom-cci: Allow operating-points-v2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-2-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=837; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=H2KC20VDboBzuOfuUjQ10i65xbtF9likBztKG+8DrYs=; b=RgdO/lnfLGoZ2UruWKA/spa9WBpxdoK0cYZzJGFkaDL8M9rDRD91rqXI/X4LLvYOBSKAuxmHG 3ShuY0rcZR5Ds/BW5igoGilsqIeQOutIzXBG5cHvdzlU9EdyaxmT6xI X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio An OPP table is necessary to express combined voltage and frequency requirements for the CCI hw block. Allow passing one, without requiring its presence. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 73144473b9b24e574bfc6bd7d8908f2f3895e087..1bb9a70661a944c1bdc01d33647= 5952221450dba 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -54,6 +54,8 @@ properties: interrupts: maxItems: 1 =20 + operating-points-v2: true + power-domains: maxItems: 1 =20 --=20 2.51.0 From nobody Fri Oct 3 06:36:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08FAD320CA0; Thu, 4 Sep 2025 14:31:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996300; cv=none; b=rxQ5O93Vn3YxUcXDCtZuuvi3i2Yhukptd+ankDM+NiZ0TbwpJDQt26z9M0FcRFiIMbr8u+0Qyn8CMabOmI4UsoU2OXJQM9GDdLVCXOWnIqRN3QyKQjwlbLym9wSCcHzqDtNKytQ32Y2xui+HSY29pjtA9JbfPlOo0wP9mnVvQLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996300; c=relaxed/simple; bh=W3FRmWKbxHyNCOUd1Ra/+kxcH/HvrKsMg+junB/0Om4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pIoQBF3JUoWw5gdRie/LYO2I0+oioa0b9ADPPkWBgwHVjlRG7FgsM9yEUbTdp6hwjwZZfWSdjVxqW/y8B2QCRNVUs9DP/pEqGqYKSjLlzyjZ7eWJz1xRz2tYwwcR+1vhUQfHdF13tK/3XD1mHCtk1CsD2DcKl6F+PGLhkU/akdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q1YwK/tA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q1YwK/tA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7B5B1C4CEF7; Thu, 4 Sep 2025 14:31:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996299; bh=W3FRmWKbxHyNCOUd1Ra/+kxcH/HvrKsMg+junB/0Om4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Q1YwK/tAI88YuMOWlAWjfNW8vHMWlsnrvxoo8jEIZldic1uaIbdadBfHEpsvyL1Hk 822H3UZbyZ5WBv+SDpZ6fEaP6XcJ3OCeZe61Eyp0RbMzH0bUgknTnoi5XSBpBVIuR3 nydwRmt63tLs1nFSeCRg3ytwmGBjTHgDTI7dXyvSN3U3Xix29yGXYaDO/Qk1hzCokU f39INelvMuCL0RcOdz/OIDD94awvCkwqOdv11gNnCszLu+3B6UiLpqGN7qOBzvFqIm tJRzJGIgygK4LMjjcUMKmFeThgY9GztHXfwRAJI+Cztl0rDSUnfHWtxtTTkjmd2d6p 9x4spEnOYPKPg== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:22 +0200 Subject: [PATCH 3/5] i2c: qcom-cci: Drop single-line wrappers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-3-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=1950; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=WftzdXiZKmnGP1b2v0Y7K87fxqhQ28Y81WkkVpsPg+Q=; b=fUGSJ3BylEq92lSIcEo1k0bSIPUy6oBmacbpkpw61NhbnUTv3X+oxbt8hmwWDgiHk7q0xKgqB jOC775FI8wBCQGAdCnpaBsmTSDKK2N2RqxiNsqbV4iQM3aB0/6VU6t7 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The CCI clock en/disable functions simply call bulk_ops, remove them. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Reviewed-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index a3afa11a71a10dbb720ee9acb566991fe55b98a0..74fedfdec3ae4e034ec4d946179= e963c783b5923 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -466,21 +466,12 @@ static const struct i2c_algorithm cci_algo =3D { .functionality =3D cci_func, }; =20 -static int cci_enable_clocks(struct cci *cci) -{ - return clk_bulk_prepare_enable(cci->nclocks, cci->clocks); -} - -static void cci_disable_clocks(struct cci *cci) -{ - clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); -} - static int __maybe_unused cci_suspend_runtime(struct device *dev) { struct cci *cci =3D dev_get_drvdata(dev); =20 - cci_disable_clocks(cci); + clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); + return 0; } =20 @@ -489,11 +480,12 @@ static int __maybe_unused cci_resume_runtime(struct d= evice *dev) struct cci *cci =3D dev_get_drvdata(dev); int ret; =20 - ret =3D cci_enable_clocks(cci); + ret =3D clk_bulk_prepare_enable(cci->nclocks, cci->clocks); if (ret) return ret; =20 cci_init(cci); + return 0; } =20 @@ -592,7 +584,7 @@ static int cci_probe(struct platform_device *pdev) return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n"); cci->nclocks =3D ret; =20 - ret =3D cci_enable_clocks(cci); + ret =3D clk_bulk_prepare_enable(cci->nclocks, cci->clocks); if (ret < 0) return ret; =20 @@ -651,7 +643,7 @@ static int cci_probe(struct platform_device *pdev) error: disable_irq(cci->irq); disable_clocks: - cci_disable_clocks(cci); + clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); =20 return ret; } --=20 2.51.0 From nobody Fri Oct 3 06:36:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B16BC32142F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QxeJqDF4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84828C4CEF1; Thu, 4 Sep 2025 14:31:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996304; bh=vMwA0SB53TkFbWIrdRMPy5fzrwWXCHQQ/8K295B3rig=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QxeJqDF4c0vCQ+fU3l2j22mAgJ4wAMtH+g9/kRGR75p/hds+30SbjkFNkVPKNBlL2 CjQ3lGzdNharVE9D+dtKtAoAvQXbPadsimdfvurHOgvfsnIbvQGH73mXDbm+Y1Y+Vp shRk399GXQZkhGMqoEl28tkQiOCoqiJLl7vHqwuewHQ1cU8QeASCjVk3zsE+PaZwJS xaoVblJ9yQ6TMM/NusCGeYUSP6ZVMlszxDcL7pnKuerPqPSQnJmHSLsVoab6BXmCWV wkl5bbxLOpa2l1loYmJJTDDKmuaqiJ/xlt14bQegAXPG8fNsjQ6bpfbfFCOJhRdBCv wc3wiLf3rVIZg== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:23 +0200 Subject: [PATCH 4/5] i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=2740; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=esmE6Br08dCVGEBntkla7rJKl1xlxC8bF8RScCLVl3E=; b=NbX70ApqPifadDof2Jp1gvqdkTWncOItW7toAG2hQbHvqi4f/NnnUNBH1CfL6Tihr4l2XiUCL PkBaTu+OrALCUX0JGookjl55lemoW3a1d98EFxKgACQ+tx0e540c5Uh X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The CCI clock has voltage requirements, which need to be described through an OPP table. The 1 MHz FAST_PLUS mode requires the CCI core clock runs at 37,5 MHz (which is a value common across all SoCs), since it's not possible to reach the required timings with the default 19.2 MHz rate. Address both issues by introducing an OPP table and using it to vote for the faster rate. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/i2c/busses/i2c-qcom-cci.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index 74fedfdec3ae4e034ec4d946179e963c783b5923..d6192e2a5e3bc4d908cba594d19= 10a41f3a41e9c 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -10,6 +10,7 @@ #include #include #include +#include #include =20 #define CCI_HW_VERSION 0x0 @@ -121,6 +122,7 @@ struct cci_data { struct i2c_adapter_quirks quirks; u16 queue_size[NUM_QUEUES]; struct hw_params params[3]; + bool fast_mode_plus_supported; }; =20 struct cci { @@ -466,9 +468,22 @@ static const struct i2c_algorithm cci_algo =3D { .functionality =3D cci_func, }; =20 +static unsigned long cci_desired_clk_rate(struct cci *cci) +{ + if (cci->data->fast_mode_plus_supported) + return 37500000ULL; + + return 19200000ULL; +} + static int __maybe_unused cci_suspend_runtime(struct device *dev) { struct cci *cci =3D dev_get_drvdata(dev); + int ret; + + ret =3D dev_pm_opp_set_rate(dev, 0); + if (ret) + return ret; =20 clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); =20 @@ -484,6 +499,10 @@ static int __maybe_unused cci_resume_runtime(struct de= vice *dev) if (ret) return ret; =20 + ret =3D dev_pm_opp_set_rate(dev, cci_desired_clk_rate(cci)); + if (ret) + return ret; + cci_init(cci); =20 return 0; @@ -588,6 +607,19 @@ static int cci_probe(struct platform_device *pdev) if (ret < 0) return ret; =20 + ret =3D devm_pm_opp_set_clkname(dev, "cci"); + if (ret) + return ret; + + /* OPP table is optional */ + ret =3D devm_pm_opp_of_add_table(dev); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); + + ret =3D dev_pm_opp_set_rate(dev, cci_desired_clk_rate(cci)); + if (ret) + return ret; + /* Interrupt */ =20 ret =3D platform_get_irq(pdev, 0); @@ -775,6 +807,7 @@ static const struct cci_data cci_v2_data =3D { .trdhld =3D 3, .tsp =3D 3 }, + .fast_mode_plus_supported =3D true, }; =20 static const struct of_device_id cci_dt_match[] =3D { --=20 2.51.0 From nobody Fri Oct 3 06:36:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4BC3337686; Thu, 4 Sep 2025 14:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996308; cv=none; b=FXs/a1FDAFwhwpszMVRI2Kp8Eiy9L08obsy3MoCCdzqyVMFPQqGOcrU5i2ycIdyRotsrzCQAKH11/KXf2tPM5yU6opVT6FlsdDGJPDNxGkkl8nuvDoyG9A3vqzNos1O8KhR3/k0gIa60x0qoLmKuzn9wdM/FefQI1N7qH4u6S2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756996308; c=relaxed/simple; bh=zrXW+Azg1ybj1TP3cpfO/sfkOo2o+dZsnZjYmLh/LK8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rpErtZlkU2h1VczCFgABIR0rB3HMrMoEYqo9hxhld8oF61UJzo125S0+pBWFfv1DG1SY3/M34+71ru21+TBMGVQLzmHmVlo7opYrEPOOJchLCkNbBDIVt88gkOs2DmB7jFD2yyde1pOIjBNPQJfuN55l3xFvrxt3zb+6CVKk5mw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C02U6Ifz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C02U6Ifz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE8F8C4CEF0; Thu, 4 Sep 2025 14:31:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756996308; bh=zrXW+Azg1ybj1TP3cpfO/sfkOo2o+dZsnZjYmLh/LK8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=C02U6IfzCnjPntWkpqfN55JYi+7tR1UyxDv2EQdPD5QKrddYeU6thbFlveMQMiZhz ETaW9jJ5wOR3oGI/1nw0RBNOlg7rSr7+ye9hlOIobPvP/M2Q4JiwM4EtOcYxjpTE8t xtOtcJk1pFzU3v3KDfNUJA2Kec6dpefNVU0cl7TXq5TeptIaX1JTiEwg5l42oaM3mV 9dHjPg/lWCDBpkdEmRpWaR6TVSDjBXubLoZY1A1U/rR432Sk8EKKcJTXHmHoALmRGp o3qVa8wg5oqV4lzYDjZVq8V/W9swLAZQLlayaXKAhquiRkdOlTdgSn7XHWJhfT4MOh 6jkkhdQn0raLw== From: Konrad Dybcio Date: Thu, 04 Sep 2025 16:31:24 +0200 Subject: [PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756996284; l=1943; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=s0obim0MuDOlL4+p0Nk62B+LrJ+2kyEd8cmm4PAWtK8=; b=P8CmCRAIy6ipK3s7L7LsmaixnjgqhLcOehR6tKYWKSMguFg9xxmQpO8hqbbYYpglR5C5yzqSV 1l4LC8ILpdyAsn/Z7oQUi1WqP3niXbvTVRyCQs5eBoYl+Hn23uuMIfj X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The CCI hosts have both frequency and voltage requirements (which happen to be common across instances on a given SoC, at least so far). Express them by introducing an OPP table and linking it to the hosts. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a3= 58563329a02a4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -391,6 +391,15 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + cci_opp_table: opp-table-cci { + compatible =3D "operating-points-v2"; + + opp-37500000 { + opp-hz =3D /bits/ 64 <37500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + cpu0_opp_table: opp-table-cpu0 { compatible =3D "operating-points-v2"; opp-shared; @@ -4181,6 +4190,7 @@ cci0: cci@ac4a000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci0_default>; @@ -4222,6 +4232,7 @@ cci1: cci@ac4b000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci1_default>; @@ -4262,6 +4273,8 @@ cci2: cci@ac4c000 { "slow_ahb_src", "cpas_ahb", "cci"; + + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci2_default>; @@ -4303,6 +4316,7 @@ cci3: cci@ac4d000 { "cpas_ahb", "cci"; =20 + operating-points-v2 =3D <&cci_opp_table>; power-domains =3D <&camcc TITAN_TOP_GDSC>; =20 pinctrl-0 =3D <&cci3_default>; --=20 2.51.0