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Wed, 03 Sep 2025 23:56:21 -0700 (PDT) From: Abel Vesa Date: Thu, 04 Sep 2025 09:55:51 +0300 Subject: [PATCH 1/3] dt-bindings: phy: Add DP PHY compatible for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-phy-qcom-edp-add-glymur-support-v1-1-e83c6b9a145b@linaro.org> References: <20250904-phy-qcom-edp-add-glymur-support-v1-0-e83c6b9a145b@linaro.org> In-Reply-To: <20250904-phy-qcom-edp-add-glymur-support-v1-0-e83c6b9a145b@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the compatible for the Glymur platform. Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2..e572f6ea3523a483f701aedab38= 3a63af7abe0e5 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -24,6 +24,7 @@ properties: - qcom,sc8280xp-dp-phy - qcom,sc8280xp-edp-phy - qcom,x1e80100-dp-phy + - qcom,glymur-dp-phy - items: - enum: - qcom,qcs8300-edp-phy @@ -73,6 +74,7 @@ allOf: compatible: enum: - qcom,x1e80100-dp-phy + - qcom,glymur-dp-phy then: properties: clocks: --=20 2.45.2 From nobody Fri Oct 3 06:33:23 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EA6228850B for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add the missing v8 register offsets needed by the eDP/DP PHY driver. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h index d3b2292257bc521cb66562a5b6bfae8dc8c92cc1..7143925fbeecd9586d27ffef98e= d3e8a232f39e7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h @@ -33,6 +33,7 @@ #define QSERDES_V8_COM_CP_CTRL_MODE0 0x070 #define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 #define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 +#define QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c #define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 #define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 #define QSERDES_V8_COM_DEC_START_MODE0 0x088 @@ -40,25 +41,36 @@ #define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 #define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 #define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 +#define QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 #define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 +#define QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 #define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac #define QSERDES_V8_COM_BG_TIMER 0x0bc #define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 +#define QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 #define QSERDES_V8_COM_SSC_PER1 0x0cc #define QSERDES_V8_COM_SSC_PER2 0x0d0 #define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc +#define QSERDES_V8_COM_CLK_ENABLE1 0x0e0 +#define QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 #define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 +#define QSERDES_V8_COM_PLL_IVCO 0x0f4 #define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 #define QSERDES_V8_COM_RESETSM_CNTRL 0x118 +#define QSERDES_V8_COM_LOCK_CMP_EN 0x120 #define QSERDES_V8_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c #define QSERDES_V8_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V8_COM_CLK_SELECT 0x164 #define QSERDES_V8_COM_CORE_CLK_EN 0x170 #define QSERDES_V8_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V8_COM_SVS_MODE_CLK_SEL 0x180 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 #define QSERDES_V8_COM_CMN_STATUS 0x2c8 #define QSERDES_V8_COM_C_READY_STATUS 0x2f0 +#define QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 =20 #endif --=20 2.45.2 From nobody Fri Oct 3 06:33:23 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F8852874EB for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Qualcomm Glymur platform has the new v8 version of the eDP/DP PHY. So rework the driver to support this new version and add the platform specific configuration data. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 239 ++++++++++++++++++++++++++++++++= ++-- 1 file changed, 232 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 116b7f7b4f8be93e5128c3cc6f382ce7576accbc..26af8d8db4d765ce35132a0fd09= 2f8c8634e43d6 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -25,6 +25,7 @@ #include "phy-qcom-qmp-dp-phy.h" #include "phy-qcom-qmp-qserdes-com-v4.h" #include "phy-qcom-qmp-qserdes-com-v6.h" +#include "phy-qcom-qmp-qserdes-com-v8.h" =20 /* EDP_PHY registers */ #define DP_PHY_CFG 0x0010 @@ -32,7 +33,7 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 =20 -#define DP_AUX_CFG_SIZE 10 +#define DP_AUX_CFG_SIZE 13 #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) =20 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 @@ -76,6 +77,7 @@ struct phy_ver_ops { int (*com_power_on)(const struct qcom_edp *edp); int (*com_resetsm_cntrl)(const struct qcom_edp *edp); int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp); + int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); }; @@ -83,6 +85,8 @@ struct phy_ver_ops { struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; + int aux_cfg_size; + const u8 *vco_div_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -185,6 +189,10 @@ static const u8 edp_phy_aux_cfg_v4[10] =3D { 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; =20 +static const u8 edp_phy_vco_div_cfg_v4[4] =3D { + 0x1, 0x1, 0x2, 0x0, +}; + static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { { 0x05, 0x11, 0x17, 0x1d }, { 0x05, 0x11, 0x18, 0xff }, @@ -199,6 +207,14 @@ static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { { 0x0d, 0xff, 0xff, 0xff } }; =20 +static const u8 edp_phy_aux_cfg_v8[13] =3D { + 0x00, 0x00, 0xa0, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x4, +}; + +static const u8 edp_phy_vco_div_cfg_v8[4] =3D { + 0x1, 0x1, 0x1, 0x1, +}; + static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { .swing_hbr_rbr =3D &edp_swing_hbr_rbr, .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, @@ -224,7 +240,11 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) goto out_disable_supplies; =20 - memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); + memcpy(aux_cfg, edp->cfg->aux_cfg, edp->cfg->aux_cfg_size); + + ret =3D edp->cfg->ver_ops->com_clk_fwd_cfg(edp); + if (ret) + return ret; =20 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, @@ -252,7 +272,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 writel(0xfc, edp->edp + DP_PHY_MODE); =20 - for (int i =3D 0; i < DP_AUX_CFG_SIZE; i++) + for (int i =3D 0; i < edp->cfg->aux_cfg_size; i++) writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); =20 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | @@ -345,22 +365,22 @@ static int qcom_edp_set_vco_div(const struct qcom_edp= *edp, unsigned long *pixel =20 switch (dp_opts->link_rate) { case 1620: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[0]; *pixel_freq =3D 1620000000UL / 2; break; =20 case 2700: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[1]; *pixel_freq =3D 2700000000UL / 2; break; =20 case 5400: - vco_div =3D 0x2; + vco_div =3D edp->cfg->vco_div_cfg[2]; *pixel_freq =3D 5400000000UL / 4; break; =20 case 8100: - vco_div =3D 0x0; + vco_div =3D edp->cfg->vco_div_cfg[3]; *pixel_freq =3D 8100000000UL / 6; break; =20 @@ -398,6 +418,11 @@ static int qcom_edp_phy_com_resetsm_cntrl_v4(const str= uct qcom_edp *edp) val, val & BIT(0), 500, 10000); } =20 +static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp) +{ + return 0; +} + static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) { /* Turn on BIAS current for PHY/PLL */ @@ -530,6 +555,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, }; @@ -538,16 +564,21 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_c= fg =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -555,10 +586,37 @@ static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_= cfg =3D { static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 +static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + QSERDES_V8_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + QSERDES_V8_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp) +{ + writel(0x3f, edp->pll + QSERDES_V8_COM_CLK_FWD_CONFIG_1); + + return 0; +} + +static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x1f, edp->pll + QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp) { u32 val; @@ -724,6 +782,139 @@ static int qcom_edp_com_configure_pll_v6(const struct= qcom_edp *edp) return 0; } =20 +static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 step1; + u32 step2; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 8100: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + case 5400: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + QSERDES_V8_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + QSERDES_V8_COM_SSC_ADJ_PER1); + writel(0x6b, edp->pll + QSERDES_V8_COM_SSC_PER1); + writel(0x02, edp->pll + QSERDES_V8_COM_SSC_PER2); + writel(step1, edp->pll + QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0); + + return 0; +} + +static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 div_frac_start2_mode0; + u32 div_frac_start3_mode0; + u32 dec_start_mode0; + u32 lock_cmp1_mode0; + u32 lock_cmp2_mode0; + u32 code1_mode0; + u32 code2_mode0; + u32 hsclk_sel; + + switch (dp_opts->link_rate) { + case 1620: + hsclk_sel =3D 0x5; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x37; + lock_cmp2_mode0 =3D 0x04; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 2700: + hsclk_sel =3D 0x3; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x07; + lock_cmp2_mode0 =3D 0x07; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 5400: + hsclk_sel =3D 0x2; + dec_start_mode0 =3D 0x4f; + div_frac_start2_mode0 =3D 0xa0; + div_frac_start3_mode0 =3D 0x01; + lock_cmp1_mode0 =3D 0x18; + lock_cmp2_mode0 =3D 0x15; + code1_mode0 =3D 0x14; + code2_mode0 =3D 0x25; + break; + + case 8100: + hsclk_sel =3D 0x2; + dec_start_mode0 =3D 0x4f; + div_frac_start2_mode0 =3D 0xa0; + div_frac_start3_mode0 =3D 0x01; + lock_cmp1_mode0 =3D 0x18; + lock_cmp2_mode0 =3D 0x15; + code1_mode0 =3D 0x14; + code2_mode0 =3D 0x25; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + QSERDES_V8_COM_SVS_MODE_CLK_SEL); + writel(0x3b, edp->pll + QSERDES_V8_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + QSERDES_V8_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + QSERDES_V8_COM_CLK_ENABLE1); + writel(0x06, edp->pll + QSERDES_V8_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + QSERDES_V8_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + QSERDES_V8_COM_HSCLK_SEL_1); + writel(0x07, edp->pll + QSERDES_V8_COM_PLL_IVCO); + writel(0x00, edp->pll + QSERDES_V8_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + QSERDES_V8_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + QSERDES_V8_COM_PLL_RCTRL_MODE0); + writel(0x06, edp->pll + QSERDES_V8_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + QSERDES_V8_COM_DEC_START_MODE0); + writel(0x00, edp->pll + QSERDES_V8_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + QSERDES_V8_COM_DIV_FRAC_START2_M= ODE0); + writel(div_frac_start3_mode0, edp->pll + QSERDES_V8_COM_DIV_FRAC_START3_M= ODE0); + writel(0x96, edp->pll + QSERDES_V8_COM_CMN_CONFIG_1); + writel(0x3f, edp->pll + QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + QSERDES_V8_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + QSERDES_V8_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + QSERDES_V8_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + QSERDES_V8_COM_BG_TIMER); + writel(0x0a, edp->pll + QSERDES_V8_COM_CORECLK_DIV_MODE0); + writel(0x00, edp->pll + QSERDES_V8_COM_VCO_TUNE_CTRL); + writel(0x1f, edp->pll + QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + writel(0x00, edp->pll + QSERDES_V8_COM_CORE_CLK_EN); + writel(0xa0, edp->pll + QSERDES_V8_COM_VCO_TUNE1_MODE0); + writel(0x01, edp->pll + QSERDES_V8_COM_VCO_TUNE2_MODE0); + + writel(code1_mode0, edp->pll + QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0); + writel(code2_mode0, edp->pll + QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0); + + return 0; +} + static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D { .com_power_on =3D qcom_edp_phy_power_on_v6, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v6, @@ -732,12 +923,45 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = =3D { .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, }; =20 +static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + QSERDES_V8_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v8, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v8, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v8, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, + .com_configure_pll =3D qcom_edp_com_configure_pll_v8, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, +}; + static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 +static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v8, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v8), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops =3D &qcom_edp_phy_ops_v8, +}; + static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -1141,6 +1365,7 @@ static const struct of_device_id qcom_edp_phy_match_t= able[] =3D { { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &sc8280xp_edp_phy_cf= g, }, { .compatible =3D "qcom,x1e80100-dp-phy", .data =3D &x1e80100_phy_cfg, }, + { .compatible =3D "qcom,glymur-dp-phy", .data =3D &glymur_phy_cfg, }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); --=20 2.45.2