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Thu, 04 Sep 2025 07:07:14 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.194]) by smtp.gmail.com with ESMTPSA id af79cd13be357-80bdedfeaedsm212280285a.70.2025.09.04.07.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Sep 2025 07:07:14 -0700 (PDT) From: Denzeel Oliva Date: Thu, 04 Sep 2025 14:07:11 +0000 Subject: [PATCH v3 1/4] dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-perics-usi-v3-1-3ea109705cb6@gmail.com> References: <20250904-perics-usi-v3-0-3ea109705cb6@gmail.com> In-Reply-To: <20250904-perics-usi-v3-0-3ea109705cb6@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Igor Belwon , Andi Shyti , Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756994833; l=9680; i=wachiturroxd150@gmail.com; s=20250831; h=from:subject:message-id; bh=FWfkf2K/As/HY295WWG/h7wnSFwEcmpa3ryJTLAMao0=; b=gE/El9JO4DhQ8WfqRu+Cst8I2FxPHHt0V/SY5EhIK4V6kGjue5i9Q9DVKdEqhHPiUkJTyTjxD h33A/t2LiKtDb1522f3bO4FjSfRr4OONOskoL+a2TrdCmTAEGngPFSf X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=3fZmF8+BzoNPhZuzL19/BkBXzCDwLBPlLqQYILU0U5k= Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva --- .../bindings/clock/samsung,exynos990-clock.yaml | 24 +++ include/dt-bindings/clock/samsung,exynos990.h | 176 +++++++++++++++++= ++++ 2 files changed, 200 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-cloc= k.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.ya= ml index c15cc1752b026231d8d9c3c07bdab201016b6078..5cd2d80b8ed667af2b44e3686aa= cbe3de31e3e2d 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -30,6 +30,8 @@ description: | properties: compatible: enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 - samsung,exynos990-cmu-hsi0 - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top @@ -56,6 +58,28 @@ required: - reg =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU= _TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_= TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bin= dings/clock/samsung,exynos990.h index c60f15503d5b18b11ca9bdce86466512dc933901..47540307cb52ead9c8f82a99957= cdb2f1b0633e8 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -238,6 +238,182 @@ #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 #define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23 =20 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_UART_DBG 2 +#define CLK_MOUT_PERIC0_USI00_USI_USER 3 +#define CLK_MOUT_PERIC0_USI01_USI_USER 4 +#define CLK_MOUT_PERIC0_USI02_USI_USER 5 +#define CLK_MOUT_PERIC0_USI03_USI_USER 6 +#define CLK_MOUT_PERIC0_USI04_USI_USER 7 +#define CLK_MOUT_PERIC0_USI05_USI_USER 8 +#define CLK_MOUT_PERIC0_USI13_USI_USER 9 +#define CLK_MOUT_PERIC0_USI14_USI_USER 10 +#define CLK_MOUT_PERIC0_USI15_USI_USER 11 +#define CLK_MOUT_PERIC0_USI_I2C_USER 12 +#define CLK_DOUT_PERIC0_UART_DBG 13 +#define CLK_DOUT_PERIC0_USI00_USI 14 +#define CLK_DOUT_PERIC0_USI01_USI 15 +#define CLK_DOUT_PERIC0_USI02_USI 16 +#define CLK_DOUT_PERIC0_USI03_USI 17 +#define CLK_DOUT_PERIC0_USI04_USI 18 +#define CLK_DOUT_PERIC0_USI05_USI 19 +#define CLK_DOUT_PERIC0_USI13_USI 20 +#define CLK_DOUT_PERIC0_USI14_USI 21 +#define CLK_DOUT_PERIC0_USI15_USI 22 +#define CLK_DOUT_PERIC0_USI_I2C 23 +#define CLK_GOUT_PERIC0_CMU_PCLK 24 +#define CLK_GOUT_PERIC0_OSCCLK_CLK 25 +#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26 +#define CLK_GOUT_PERIC0_GPIO_PCLK 27 +#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40 +#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41 +#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42 +#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43 +#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44 +#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45 +#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46 +#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47 +#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48 +#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49 +#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50 +#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51 +#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59 +#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60 +#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61 +#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62 +#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63 +#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64 +#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65 +#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66 +#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67 +#define CLK_GOUT_PERIC0_BUSP_CLK 68 +#define CLK_GOUT_PERIC0_UART_DBG_CLK 69 +#define CLK_GOUT_PERIC0_USI00_USI_CLK 70 +#define CLK_GOUT_PERIC0_USI01_USI_CLK 71 +#define CLK_GOUT_PERIC0_USI02_USI_CLK 72 +#define CLK_GOUT_PERIC0_USI03_USI_CLK 73 +#define CLK_GOUT_PERIC0_USI04_USI_CLK 74 +#define CLK_GOUT_PERIC0_USI05_USI_CLK 75 +#define CLK_GOUT_PERIC0_USI13_USI_CLK 76 +#define CLK_GOUT_PERIC0_USI14_USI_CLK 77 +#define CLK_GOUT_PERIC0_USI15_USI_CLK 78 +#define CLK_GOUT_PERIC0_USI_I2C_CLK 79 +#define CLK_GOUT_PERIC0_SYSREG_PCLK 80 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_UART_BT_USER 2 +#define CLK_MOUT_PERIC1_USI06_USI_USER 3 +#define CLK_MOUT_PERIC1_USI07_USI_USER 4 +#define CLK_MOUT_PERIC1_USI08_USI_USER 5 +#define CLK_MOUT_PERIC1_USI09_USI_USER 6 +#define CLK_MOUT_PERIC1_USI10_USI_USER 7 +#define CLK_MOUT_PERIC1_USI11_USI_USER 8 +#define CLK_MOUT_PERIC1_USI12_USI_USER 9 +#define CLK_MOUT_PERIC1_USI18_USI_USER 10 +#define CLK_MOUT_PERIC1_USI16_USI_USER 11 +#define CLK_MOUT_PERIC1_USI17_USI_USER 12 +#define CLK_MOUT_PERIC1_USI_I2C_USER 13 +#define CLK_DOUT_PERIC1_UART_BT 14 +#define CLK_DOUT_PERIC1_USI06_USI 15 +#define CLK_DOUT_PERIC1_USI07_USI 16 +#define CLK_DOUT_PERIC1_USI08_USI 17 +#define CLK_DOUT_PERIC1_USI18_USI 18 +#define CLK_DOUT_PERIC1_USI12_USI 19 +#define CLK_DOUT_PERIC1_USI09_USI 20 +#define CLK_DOUT_PERIC1_USI10_USI 21 +#define CLK_DOUT_PERIC1_USI11_USI 22 +#define CLK_DOUT_PERIC1_USI16_USI 23 +#define CLK_DOUT_PERIC1_USI17_USI 24 +#define CLK_DOUT_PERIC1_USI_I2C 25 +#define CLK_GOUT_PERIC1_CMU_PCLK 26 +#define CLK_GOUT_PERIC1_UART_BT_CLK 27 +#define CLK_GOUT_PERIC1_USI12_USI_CLK 28 +#define CLK_GOUT_PERIC1_USI18_USI_CLK 29 +#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30 +#define CLK_GOUT_PERIC1_GPIO_PCLK 31 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40 +#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41 +#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42 +#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43 +#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44 +#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45 +#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46 +#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61 +#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62 +#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63 +#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64 +#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65 +#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66 +#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67 +#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68 +#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69 +#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70 +#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71 +#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72 +#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73 +#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74 +#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75 +#define CLK_GOUT_PERIC1_BUSP_CLK 76 +#define CLK_GOUT_PERIC1_OSCCLK_CLK 77 +#define CLK_GOUT_PERIC1_USI06_USI_CLK 78 +#define CLK_GOUT_PERIC1_USI07_USI_CLK 79 +#define CLK_GOUT_PERIC1_USI08_USI_CLK 80 +#define CLK_GOUT_PERIC1_USI09_USI_CLK 81 +#define CLK_GOUT_PERIC1_USI10_USI_CLK 82 +#define CLK_GOUT_PERIC1_USI11_USI_CLK 83 +#define CLK_GOUT_PERIC1_USI16_USI_CLK 84 +#define CLK_GOUT_PERIC1_USI17_USI_CLK 85 +#define CLK_GOUT_PERIC1_USI_I2C_CLK 86 +#define CLK_GOUT_PERIC1_SYSREG_PCLK 87 +#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88 +#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89 +#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90 +#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91 +#define CLK_GOUT_PERIC1_XIU_P_ACLK 92 + /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 #define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 --=20 2.50.1 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Docum= entation/devicetree/bindings/i2c/i2c-exynos5.yaml index 7ae8c7b1d0067e7e7a73a58e8bcb4aac71e87dd8..6fc03281a8f8440ba64df569f6c= 83ba2d9f6915e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -38,6 +38,7 @@ properties: - google,gs101-hsi2c - samsung,exynos2200-hsi2c - samsung,exynos850-hsi2c + - samsung,exynos990-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true --=20 2.50.1 From nobody Fri Oct 3 05:26:13 2025 Received: from mail-qk1-f176.google.com (mail-qk1-f176.google.com [209.85.222.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A45D5307AD9; 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a=ed25519-sha256; t=1756994833; l=63213; i=wachiturroxd150@gmail.com; s=20250831; h=from:subject:message-id; bh=lWN0ulIH0wwIJPga4ChEhM5mxUFxQkAfxBCmjxx95HM=; b=rENCkkbuimhOPxbNwSVRJer/1fm2AevIORgu02n3C8Du3FaK1Wu/EzTen9PCAO8vAz/SR8Ddh aty47+MfYVEDcnDuHIlBB8Fu9T7AQF1tnPWUoX/oEhRoLfuBLIUlZsq X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=3fZmF8+BzoNPhZuzL19/BkBXzCDwLBPlLqQYILU0U5k= Add clock controller support for Peripheral Connectivity 0 and 1 blocks. These provide clocks for USI, I2C and UART peripherals. Some clocks need to be marked as critical to prevent system hang when disabled. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 1152 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 1152 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 47a1e0850c3020ab66931ae0c5ac4920f41496d0..d6ae6c2e270c6e87beb029577e6= 61a9fba32b497 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -19,6 +19,8 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PCLK + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_XIU_P_ACLK + 1) #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= --- */ @@ -1351,6 +1353,1150 @@ static const struct samsung_cmu_info hsi0_cmu_info= __initconst =3D { .clk_name =3D "bus", }; =20 +/* ---- CMU_PERIC0 -------------------------------------------------------= -- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10400000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b4 +#define CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK = 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPOR= T_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x2= 00c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK = 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0= x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0= x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0= x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0= x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0= x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0= x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x= 2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x= 2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x= 2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x= 203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x= 2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x= 2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x= 2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x= 204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x= 2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x= 2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x= 2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x= 205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2= 060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2= 064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2= 068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2= 06c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2= 070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2= 074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x= 2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3 0x= 207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4 0x= 2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5 0x= 2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6 0x= 2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7 0x= 208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8 0x= 2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2= 094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15 0x= 2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3 0x2= 09c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4 0x2= 0a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5 0x2= 0a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6 0x2= 0a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7 0x2= 0ac +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8 0x2= 0b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT= _CLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLK= PORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCL= KPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCL= KPORT_CLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCL= KPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCL= KPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCL= KPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCL= KPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCL= KPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCL= KPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCL= KPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKP= ORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2= 0e4 + +static const unsigned long peric0_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER, + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, +}; + +/* Parent clock list for CMU_PERIC0 muxes */ +PNAME(mout_peric0_bus_user_p) =3D { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_uart_dbg_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi00_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi01_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi02_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi03_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi04_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi05_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi13_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi14_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi15_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_i2c_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg", + mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user", + mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user", + mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user", + mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user", + mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user", + mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user", + mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user", + mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user", + mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user", + mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user", + mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, + 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst =3D { + DIV(CLK_DOUT_PERIC0_UART_DBG, "dout_peric0_uart_dbg", + "mout_peric0_uart_dbg", + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", + "mout_peric0_usi00_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", + "mout_peric0_usi01_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", + "mout_peric0_usi02_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", + "mout_peric0_usi03_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", + "mout_peric0_usi04_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", + "mout_peric0_usi05_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi", + "mout_peric0_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi", + "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi", + "mout_peric0_usi15_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, + 0, 4), + DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", + "mout_peric0_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, + 0, 4), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_PERIC0_CMU_PCLK, "gout_peric0_cmu_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_OSCCLK_CLK, "gout_peric0_oscclk_clk", + "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_= CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PCLK, "gout_peric0_d_tpzc_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPIO_PCLK, "gout_peric0_gpio_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_CLK, "gout_peric0_lhm_axi_p_clk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_10, "gout_peric0_top0_ipclk_10", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_11, "gout_peric0_top0_ipclk_11", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_12, "gout_peric0_top0_ipclk_12", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_13, "gout_peric0_top0_ipclk_13", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_14, "gout_peric0_top0_ipclk_14", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_15, "gout_peric0_top0_ipclk_15", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_4, "gout_peric0_top0_ipclk_4", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_5, "gout_peric0_top0_ipclk_5", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_6, "gout_peric0_top0_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_7, "gout_peric0_top0_ipclk_7", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_8, "gout_peric0_top0_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_9, "gout_peric0_top0_ipclk_9", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_10, "gout_peric0_top0_pclk_10", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_11, "gout_peric0_top0_pclk_11", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_12, "gout_peric0_top0_pclk_12", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_13, "gout_peric0_top0_pclk_13", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_14, "gout_peric0_top0_pclk_14", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_15, "gout_peric0_top0_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_4, "gout_peric0_top0_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_5, "gout_peric0_top0_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_6, "gout_peric0_top0_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_7, "gout_peric0_top0_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_8, "gout_peric0_top0_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_9, "gout_peric0_top0_pclk_9", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_0, "gout_peric0_top1_ipclk_0", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_3, "gout_peric0_top1_ipclk_3", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_4, "gout_peric0_top1_ipclk_4", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_5, "gout_peric0_top1_ipclk_5", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_6, "gout_peric0_top1_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_7, "gout_peric0_top1_ipclk_7", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_8, "gout_peric0_top1_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_0, "gout_peric0_top1_pclk_0", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_15, "gout_peric0_top1_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_3, "gout_peric0_top1_pclk_3", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_4, "gout_peric0_top1_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_5, "gout_peric0_top1_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_6, "gout_peric0_top1_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_7, "gout_peric0_top1_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_8, "gout_peric0_top1_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_BUSP_CLK, "gout_peric0_busp_clk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_C= LK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_UART_DBG_CLK, "gout_peric0_uart_dbg_clk", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI00_USI_CLK, "gout_peric0_usi00_usi_clk", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI01_USI_CLK, "gout_peric0_usi01_usi_clk", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI02_USI_CLK, "gout_peric0_usi02_usi_clk", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI03_USI_CLK, "gout_peric0_usi03_usi_clk", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI04_USI_CLK, "gout_peric0_usi04_usi_clk", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI05_USI_CLK, "gout_peric0_usi05_usi_clk", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI13_USI_CLK, "gout_peric0_usi13_usi_clk", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI14_USI_CLK, "gout_peric0_usi14_usi_clk", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI15_USI_CLK, "gout_peric0_usi15_usi_clk", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI_I2C_CLK, "gout_peric0_usi_i2c_clk", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPOR= T_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PCLK, "gout_peric0_sysreg_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0) +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst =3D { + .mux_clks =3D peric0_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(peric0_mux_clks), + .div_clks =3D peric0_div_clks, + .nr_div_clks =3D ARRAY_SIZE(peric0_div_clks), + .gate_clks =3D peric0_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids =3D CLKS_NR_PERIC0, + .clk_regs =3D peric0_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(peric0_clk_regs), + .clk_name =3D "bus", +}; + +/* ---- CMU_PERIC1 -------------------------------------------------------= -- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10700000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c4 +#define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x182c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK = 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPO= RT_CLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLK= PORT_CLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLK= PORT_CLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2= 014 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_C= LK 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK = 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0= x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0= x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12 0= x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13 0= x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14 0= x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15 0= x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x= 203c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x= 2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x= 2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12 0x= 2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13 0x= 204c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14 0x= 2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x= 2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2= 058 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0 0x= 205c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1 0x= 2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10 0= x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12 0= x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13 0= x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14 0= x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15 0= x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2 0x= 207c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3 0x= 2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4 0x= 2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5 0x= 2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6 0x= 208c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7 0x= 2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9 0x= 2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0 0x2= 09c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1 0x2= 0a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10 0x= 20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12 0x= 20ac +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13 0x= 20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14 0x= 20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15 0x= 20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2 0x2= 0bc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3 0x2= 0c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4 0x2= 0c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5 0x2= 0c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6 0x2= 0cc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7 0x2= 0d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9 0x2= 0d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT= _CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPO= RT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCL= KPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCL= KPORT_CLK 0x20e8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCL= KPORT_CLK 0x20ec +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCL= KPORT_CLK 0x20f0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCL= KPORT_CLK 0x20f4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCL= KPORT_CLK 0x20f8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCL= KPORT_CLK 0x20fc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCL= KPORT_CLK 0x2100 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKP= ORT_CLK 0x2104 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2= 108 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK 0x210c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK 0x2110 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK 0x2114 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK 0x2118 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x21= 1c + +static const unsigned long peric1_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER, + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, +}; + +/* Parent clock list for CMU_PERIC1 muxes */ +PNAME(mout_peric1_bus_user_p) =3D { "oscclk", "dout_cmu_peric1_bus" }; +PNAME(mout_peric1_uart_bt_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi06_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi07_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi08_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi09_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi10_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi11_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi12_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi18_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi16_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi17_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi_i2c_user_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user", + mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user", + mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user", + mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user", + mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user", + mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user", + mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user", + mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user", + mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user", + mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user", + mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user", + mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, + 4, 1), + MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user", + mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, + 4, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst =3D { + DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt", + "mout_peric1_uart_bt_user", + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi", + "mout_peric1_usi06_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi", + "mout_peric1_usi07_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi", + "mout_peric1_usi08_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi", + "mout_peric1_usi18_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", + "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", + "mout_peric1_usi09_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", + "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", + "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", + "mout_peric1_usi16_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", + "mout_peric1_usi17_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", + "mout_peric1_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, + 0, 4), +}; + +static const struct samsung_gate_clock peric1_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_PERIC1_CMU_PCLK, "gout_peric1_cmu_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_UART_BT_CLK, "gout_peric1_uart_bt_clk", + "dout_peric1_uart_bt", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT= _CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI12_USI_CLK, "gout_peric1_usi12_usi_clk", + "dout_peric1_usi12_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI18_USI_CLK, "gout_peric1_usi18_usi_clk", + "dout_peric1_usi18_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_D_TZPC_PCLK, "gout_peric1_d_tzpc_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_GPIO_PCLK, "gout_peric1_gpio_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK, "gout_peric1_lhm_axi_p_csis_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CLK, "gout_peric1_lhm_axi_p_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_10, "gout_peric1_top0_ipclk_10", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_11, "gout_peric1_top0_ipclk_11", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_12, "gout_peric1_top0_ipclk_12", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_13, "gout_peric1_top0_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_14, "gout_peric1_top0_ipclk_14", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_15, "gout_peric1_top0_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_4, "gout_peric1_top0_ipclk_4", + "dout_peric1_uart_bt", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_10, "gout_peric1_top0_pclk_10", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_11, "gout_peric1_top0_pclk_11", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_12, "gout_peric1_top0_pclk_12", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_13, "gout_peric1_top0_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_14, "gout_peric1_top0_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_15, "gout_peric1_top0_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_4, "gout_peric1_top0_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_0, "gout_peric1_top1_ipclk_0", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_1, "gout_peric1_top1_ipclk_1", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_10, "gout_peric1_top1_ipclk_10", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_12, "gout_peric1_top1_ipclk_12", + "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_13, "gout_peric1_top1_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_14, "gout_peric1_top1_ipclk_14", + "dout_peric1_usi18_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_15, "gout_peric1_top1_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_2, "gout_peric1_top1_ipclk_2", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_3, "gout_peric1_top1_ipclk_3", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_4, "gout_peric1_top1_ipclk_4", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_5, "gout_peric1_top1_ipclk_5", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_6, "gout_peric1_top1_ipclk_6", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_7, "gout_peric1_top1_ipclk_7", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_9, "gout_peric1_top1_ipclk_9", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_0, "gout_peric1_top1_pclk_0", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_1, "gout_peric1_top1_pclk_1", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_10, "gout_peric1_top1_pclk_10", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_12, "gout_peric1_top1_pclk_12", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_13, "gout_peric1_top1_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_14, "gout_peric1_top1_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_15, "gout_peric1_top1_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_2, "gout_peric1_top1_pclk_2", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_3, "gout_peric1_top1_pclk_3", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_4, "gout_peric1_top1_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_5, "gout_peric1_top1_pclk_5", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_6, "gout_peric1_top1_pclk_6", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_7, "gout_peric1_top1_pclk_7", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_9, "gout_peric1_top1_pclk_9", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_BUSP_CLK, "gout_peric1_busp_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_C= LK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_OSCCLK_CLK, "gout_peric1_oscclk_clk", + "oscclk", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT= _CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI06_USI_CLK, "gout_peric1_usi06_usi_clk", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI07_USI_CLK, "gout_peric1_usi07_usi_clk", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI08_USI_CLK, "gout_peric1_usi08_usi_clk", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI09_USI_CLK, "gout_peric1_usi09_usi_clk", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI10_USI_CLK, "gout_peric1_usi10_usi_clk", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI11_USI_CLK, "gout_peric1_usi11_usi_clk", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_USI_CLK, "gout_peric1_usi16_usi_clk", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_USI_CLK, "gout_peric1_usi17_usi_clk", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI_I2C_CLK, "gout_peric1_usi_i2c_clk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPOR= T_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_SYSREG_PCLK, "gout_peric1_sysreg_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_PCLK, "gout_peric1_usi16_i3c_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_SCLK, "gout_peric1_usi16_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_PCLK, "gout_peric1_usi17_i3c_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_SCLK, "gout_peric1_usi17_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_XIU_P_ACLK, "gout_peric1_xiu_p_aclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, + 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst =3D { + .mux_clks =3D peric1_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(peric1_mux_clks), + .div_clks =3D peric1_div_clks, + .nr_div_clks =3D ARRAY_SIZE(peric1_div_clks), + .gate_clks =3D peric1_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(peric1_gate_clks), + .nr_clk_ids =3D CLKS_NR_PERIC1, + .clk_regs =3D peric1_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(peric1_clk_regs), + .clk_name =3D "bus", +}; + /* ---- CMU_PERIS --------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_PERIS (0x10020000) */ @@ -1544,6 +2690,12 @@ static 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af79cd13be357-809e8aaab57mr909452685a.14.1756994836809; Thu, 04 Sep 2025 07:07:16 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.194]) by smtp.gmail.com with ESMTPSA id af79cd13be357-80bdedfeaedsm212280285a.70.2025.09.04.07.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Sep 2025 07:07:16 -0700 (PDT) From: Denzeel Oliva Date: Thu, 04 Sep 2025 14:07:14 +0000 Subject: [PATCH v3 4/4] arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-perics-usi-v3-4-3ea109705cb6@gmail.com> References: <20250904-perics-usi-v3-0-3ea109705cb6@gmail.com> In-Reply-To: <20250904-perics-usi-v3-0-3ea109705cb6@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Igor Belwon , Andi Shyti , Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756994833; l=1581; i=wachiturroxd150@gmail.com; s=20250831; h=from:subject:message-id; bh=2QadQ6p8DLVRx/cTe7HdT6hSMdg6XZNjMfLKvG2yQww=; b=lhQ28jDDQdtdqkS4uzcvkeiUDTYYHpnSRGBbH3JSREg1X9aSx2b7oxOVidB1+ag+Id/8EocOy SdDO4lDJsJnBk0iZx1BQW2zDy23X5do+OlT4DHo+XBt+zMPTK8f3W3R X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=3fZmF8+BzoNPhZuzL19/BkBXzCDwLBPlLqQYILU0U5k= Add clock controller nodes for PERIC0 and PERIC1 blocks for USI nodes. Signed-off-by: Denzeel Oliva --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dt= s/exynos/exynos990.dtsi index dd7f99f51a75412f5c3b91c3425a63652546fa5e..418fc59fd9e9122f3059482276d= 3388920fab382 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -225,12 +225,34 @@ gic: interrupt-controller@10101000 { #size-cells =3D <1>; }; =20 + cmu_peric0: clock-controller@10400000 { + compatible =3D "samsung,exynos990-cmu-peric0"; + reg =3D <0x10400000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names =3D "oscclk", "bus", "ip"; + }; + pinctrl_peric0: pinctrl@10430000 { compatible =3D "samsung,exynos990-pinctrl"; reg =3D <0x10430000 0x1000>; interrupts =3D ; }; =20 + cmu_peric1: clock-controller@10700000 { + compatible =3D "samsung,exynos990-cmu-peric1"; + reg =3D <0x10700000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names =3D "oscclk", "bus", "ip"; + }; + pinctrl_peric1: pinctrl@10730000 { compatible =3D "samsung,exynos990-pinctrl"; reg =3D <0x10730000 0x1000>; --=20 2.50.1