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Thu, 04 Sep 2025 09:40:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEmaVrqqvWvNCJ18FSo86iVsdvqCApjzOy7HSZ7MVp/HHNY25R6gM8RCj1Eh+eB9N6zP6fXQg== X-Received: by 2002:a05:6a20:7491:b0:24b:1a6d:298b with SMTP id adf61e73a8af0-24b1a6d2b96mr5045604637.34.1757004012076; Thu, 04 Sep 2025 09:40:12 -0700 (PDT) Received: from hu-wasimn-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4cd006e2c6sm17346371a12.2.2025.09.04.09.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Sep 2025 09:40:09 -0700 (PDT) From: Wasim Nazir Date: Thu, 04 Sep 2025 22:09:06 +0530 Subject: [PATCH v3 10/14] arm64: dts: qcom: lemans-evk: Enable first USB controller in device mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250904-lemans-evk-bu-v3-10-8bbaac1f25e8@oss.qualcomm.com> References: <20250904-lemans-evk-bu-v3-0-8bbaac1f25e8@oss.qualcomm.com> In-Reply-To: <20250904-lemans-evk-bu-v3-0-8bbaac1f25e8@oss.qualcomm.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran , Bartosz Golaszewski Cc: kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, linux-i2c@vger.kernel.org, Krishna Kurapati , Wasim Nazir X-Mailer: b4 0.15-dev-e44bb X-Developer-Signature: v=1; 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The USB port is a Type-C port controlled by HD3SS3320 port controller. The role switch notifications would need to be routed to glue driver by adding an appropriate usb-c-connector node in DT. However in the design, the vbus supply that is to be provided to connected peripherals when port is configured as an DFP, is controlled by a GPIO. There is also one ID line going from Port controller chip to GPIO-50 of the SoC. As per the datasheet of HD3SS3320: "Upon detecting a UFP device, HD3SS3220 will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V, the HD3SS3220 will assert ID pin low. This is done to enforce Type-C requirement that VBUS must be at VSafe0V before re-enabling VBUS." The current HD3SS3220 driver doesn't have this functionality present. So, putting the first USB controller in device mode for now. Once the vbus control based on ID pin is implemented in hd3ss3220.c, the usb-c-connector will be implemented and dr mode would be made OTG. Signed-off-by: Krishna Kurapati Signed-off-by: Wasim Nazir Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts index d065528404c0..6ec6f9ed1ec9 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -538,6 +538,29 @@ &ufs_mem_phy { status =3D "okay"; }; =20 +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l6c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l7a>; + + status =3D "okay"; +}; + &xo_board_clk { clock-frequency =3D <38400000>; }; --=20 2.51.0