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[34.125.3.185]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-24c9c2b1288sm25505435ad.106.2025.09.03.15.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 15:55:09 -0700 (PDT) From: Chia-I Wu To: Boris Brezillon , Steven Price , Liviu Dudau , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH 1/2] dt-bindings: gpu: mali-valhall-csf: add MediaTek MT8196 compatible Date: Wed, 3 Sep 2025 15:55:03 -0700 Message-ID: <20250903225504.542268-2-olvaffe@gmail.com> X-Mailer: git-send-email 2.51.0.338.gd7d06c2dae-goog In-Reply-To: <20250903225504.542268-1-olvaffe@gmail.com> References: <20250903225504.542268-1-olvaffe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek MT8196 has Mali-G925-Immortalis, which can be supported by panthor. Signed-off-by: Chia-I Wu --- Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yam= l b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e00217587..7ad5a3ffc5f5c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - mediatek,mt8196-mali - rockchip,rk3588-mali - const: arm,mali-valhall-csf # Mali Valhall GPU model/revisio= n is fully discoverable =20 --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:39:21 2025 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83F312EF65E; Wed, 3 Sep 2025 22:55:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[34.125.3.185]) by smtp.gmail.com with UTF8SMTPSA id 41be03b00d2f7-b4fb15f50d6sm2243371a12.0.2025.09.03.15.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 15:55:10 -0700 (PDT) From: Chia-I Wu To: Boris Brezillon , Steven Price , Liviu Dudau , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH 2/2] drm/panthor: add initial mt8196 support Date: Wed, 3 Sep 2025 15:55:04 -0700 Message-ID: <20250903225504.542268-3-olvaffe@gmail.com> X-Mailer: git-send-email 2.51.0.338.gd7d06c2dae-goog In-Reply-To: <20250903225504.542268-1-olvaffe@gmail.com> References: <20250903225504.542268-1-olvaffe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add panthor_soc_data to control custom ASN_HASH. Add compatible string for "mediatek,mt8196-mali" and enable custom ASN_HASH for the soc. Without custom ASN_HASH, FW fails to boot panthor 48000000.gpu: [drm] *ERROR* Unhandled Page fault in AS0 at VA 0x0= 000000000000000 panthor 48000000.gpu: [drm] *ERROR* Failed to boot MCU (status=3Dfatal) panthor 48000000.gpu: probe with driver panthor failed with error -110 With custom ASN_HASH, panthor probes fine and userspace boots to ui just fine as well panthor 48000000.gpu: [drm] clock rate =3D 0 panthor 48000000.gpu: EM: created perf domain panthor 48000000.gpu: [drm] Mali-G925-Immortalis id 0xd830 major 0x0 mino= r 0x1 status 0x5 panthor 48000000.gpu: [drm] Features: L2:0x8130306 Tiler:0x809 Mem:0x301 = MMU:0x2830 AS:0xff panthor 48000000.gpu: [drm] shader_present=3D0xee0077 l2_present=3D0x1 ti= ler_present=3D0x1 panthor 48000000.gpu: [drm] Firmware protected mode entry not be supporte= d, ignoring panthor 48000000.gpu: [drm] Firmware git sha: 27713280172c742d467a4b7d111= 80930094092ec panthor 48000000.gpu: [drm] CSF FW using interface v3.13.0, Features 0x10= Instrumentation features 0x71 [drm] Initialized panthor 1.5.0 for 48000000.gpu on minor 1 Signed-off-by: Chia-I Wu --- drivers/gpu/drm/panthor/Kconfig | 6 +++++ drivers/gpu/drm/panthor/Makefile | 2 ++ drivers/gpu/drm/panthor/panthor_device.c | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 4 +++ drivers/gpu/drm/panthor/panthor_drv.c | 4 +++ drivers/gpu/drm/panthor/panthor_gpu.c | 26 +++++++++++++++++++- drivers/gpu/drm/panthor/panthor_regs.h | 4 +++ drivers/gpu/drm/panthor/panthor_soc.h | 26 ++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_soc_mt8196.c | 9 +++++++ 9 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/panthor/panthor_soc.h create mode 100644 drivers/gpu/drm/panthor/panthor_soc_mt8196.c diff --git a/drivers/gpu/drm/panthor/Kconfig b/drivers/gpu/drm/panthor/Kcon= fig index 55b40ad07f3b0..a207962cb518d 100644 --- a/drivers/gpu/drm/panthor/Kconfig +++ b/drivers/gpu/drm/panthor/Kconfig @@ -21,3 +21,9 @@ config DRM_PANTHOR =20 Note that the Mali-G68 and Mali-G78, while Valhall architecture, will be supported with the panfrost driver as they are not CSF GPUs. + +config DRM_PANTHOR_SOC_MT8196 + bool "Enable MediaTek MT8196 support" + depends on DRM_PANTHOR + help + Enable SoC-specific code for MediaTek MT8196. diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Mak= efile index 02db21748c125..75e92c461304b 100644 --- a/drivers/gpu/drm/panthor/Makefile +++ b/drivers/gpu/drm/panthor/Makefile @@ -12,4 +12,6 @@ panthor-y :=3D \ panthor_mmu.o \ panthor_sched.o =20 +panthor-$(CONFIG_DRM_PANTHOR_SOC_MT8196) +=3D panthor_soc_mt8196.o + obj-$(CONFIG_DRM_PANTHOR) +=3D panthor.o diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/pan= thor/panthor_device.c index 81df49880bd87..c7033d82cef55 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -172,6 +172,8 @@ int panthor_device_init(struct panthor_device *ptdev) struct page *p; int ret; =20 + ptdev->soc_data =3D of_device_get_match_data(ptdev->base.dev); + init_completion(&ptdev->unplug.done); ret =3D drmm_mutex_init(&ptdev->base, &ptdev->unplug.lock); if (ret) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 4fc7cf2aeed57..160977834e017 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -28,6 +28,7 @@ struct panthor_job; struct panthor_mmu; struct panthor_fw; struct panthor_perfcnt; +struct panthor_soc_data; struct panthor_vm; struct panthor_vm_pool; =20 @@ -93,6 +94,9 @@ struct panthor_device { /** @base: Base drm_device. */ struct drm_device base; =20 + /** @soc_data: Optional SoC data. */ + const struct panthor_soc_data *soc_data; + /** @phys_addr: Physical address of the iomem region. */ phys_addr_t phys_addr; =20 diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/pantho= r/panthor_drv.c index 9256806eb6623..061ba38dd1bad 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -33,6 +33,7 @@ #include "panthor_mmu.h" #include "panthor_regs.h" #include "panthor_sched.h" +#include "panthor_soc.h" =20 /** * DOC: user <-> kernel object copy helpers. @@ -1683,6 +1684,9 @@ static struct attribute *panthor_attrs[] =3D { ATTRIBUTE_GROUPS(panthor); =20 static const struct of_device_id dt_match[] =3D { +#ifdef CONFIG_DRM_PANTHOR_SOC_MT8196 + { .compatible =3D "mediatek,mt8196-mali", .data =3D &panthor_soc_data_med= iatek_mt8196, }, +#endif { .compatible =3D "rockchip,rk3588-mali" }, { .compatible =3D "arm,mali-valhall-csf" }, {} diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index db69449a5be09..e68001a330790 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -19,6 +19,7 @@ #include "panthor_device.h" #include "panthor_gpu.h" #include "panthor_regs.h" +#include "panthor_soc.h" =20 /** * struct panthor_gpu - GPU block management data. @@ -52,6 +53,28 @@ static void panthor_gpu_coherency_set(struct panthor_dev= ice *ptdev) ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE); } =20 +static void panthor_gpu_l2_config_set(struct panthor_device *ptdev) +{ + const struct panthor_soc_data *data =3D ptdev->soc_data; + u32 l2_config; + u32 i; + + if (!data || !data->asn_hash_enable) + return; + + if (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) < 11) { + drm_err(&ptdev->base, "Custom ASN hash not supported by the device"); + return; + } + + for (i =3D 0; i < ARRAY_SIZE(data->asn_hash); i++) + gpu_write(ptdev, GPU_ASN_HASH(i), data->asn_hash[i]); + + l2_config =3D gpu_read(ptdev, GPU_L2_CONFIG); + l2_config |=3D GPU_L2_CONFIG_ASN_HASH_ENABLE; + gpu_write(ptdev, GPU_L2_CONFIG, l2_config); +} + static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 stat= us) { gpu_write(ptdev, GPU_INT_CLEAR, status); @@ -241,8 +264,9 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptde= v) hweight64(ptdev->gpu_info.shader_present)); } =20 - /* Set the desired coherency mode before the power up of L2 */ + /* Set the desired coherency mode and L2 config before the power up of L2= */ panthor_gpu_coherency_set(ptdev); + panthor_gpu_l2_config_set(ptdev); =20 return panthor_gpu_power_on(ptdev, L2, 1, 20000); } diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panth= or/panthor_regs.h index 8bee76d01bf83..8fa69f33e911e 100644 --- a/drivers/gpu/drm/panthor/panthor_regs.h +++ b/drivers/gpu/drm/panthor/panthor_regs.h @@ -64,6 +64,8 @@ =20 #define GPU_FAULT_STATUS 0x3C #define GPU_FAULT_ADDR 0x40 +#define GPU_L2_CONFIG 0x48 +#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24) =20 #define GPU_PWR_KEY 0x50 #define GPU_PWR_KEY_UNLOCK 0x2968A819 @@ -110,6 +112,8 @@ =20 #define GPU_REVID 0x280 =20 +#define GPU_ASN_HASH(n) (0x2C0 + ((n) * 4)) + #define GPU_COHERENCY_FEATURES 0x300 #define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name) =20 diff --git a/drivers/gpu/drm/panthor/panthor_soc.h b/drivers/gpu/drm/pantho= r/panthor_soc.h new file mode 100644 index 0000000000000..784f4f359f0bb --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_soc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 or MIT */ +/* Copyright 2025 Google LLC */ + +#ifndef __PANTHOR_SOC_H__ +#define __PANTHOR_SOC_H__ + +#include + +struct panthor_device; + +/** + * struct panthor_soc_data - Panthor SoC Data + */ +struct panthor_soc_data { + /** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. = */ + bool asn_hash_enable; + + /** @asn_hash: ASN_HASH values when asn_hash_enable is true. */ + u32 asn_hash[3]; +}; + +#ifdef CONFIG_DRM_PANTHOR_SOC_MT8196 +extern const struct panthor_soc_data panthor_soc_data_mediatek_mt8196; +#endif + +#endif /* __PANTHOR_SOC_H__ */ diff --git a/drivers/gpu/drm/panthor/panthor_soc_mt8196.c b/drivers/gpu/drm= /panthor/panthor_soc_mt8196.c new file mode 100644 index 0000000000000..d85b2168c158c --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_soc_mt8196.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* Copyright 2025 Google LLC */ + +#include "panthor_soc.h" + +const struct panthor_soc_data panthor_soc_data_mediatek_mt8196 =3D { + .asn_hash_enable =3D true, + .asn_hash =3D { 0xb, 0xe, 0x0, }, +}; --=20 2.51.0.338.gd7d06c2dae-goog