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Wed, 03 Sep 2025 09:17:33 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:9019:aa0f:b6e4:7952]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3db72983560sm5645734f8f.1.2025.09.03.09.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 09:17:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Tomi Valkeinen , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH v8 5/6] drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support Date: Wed, 3 Sep 2025 17:17:17 +0100 Message-ID: <20250903161718.180488-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250903161718.180488-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250903161718.180488-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add LPCLK clock handling to the RZ/G2L MIPI DSI driver to support proper DSI timing parameter configuration on RZ/V2H SoCs. While lpclk is present on both RZ/G2L and RZ/V2H SoCs, the RZ/V2H SoC specifically uses the lpclk rate to configure the DSI timing parameter ULPSEXIT. Introduce a new lpclk field in the rzg2l_mipi_dsi structure and acquire the "lpclk" clock during probe to enable lpclk rate-based timing calculations on RZ/V2H while maintaining compatibility with RZ/G2L. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Tomi Valkeinen --- v7->v8: - Updated commit message - Switched to use devm_clk_get() instead of devm_clk_get_optional() as lpclk clock is available on all SoCs. v6->v7: - New patch Note, this patch was previously part of series [0]. [0] https://lore.kernel.org/all/20250609225630.502888-1-prabhakar.mahadev-l= ad.rj@bp.renesas.com/ --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 3b52dfc0ea1e..bb03b49b1e85 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -68,6 +68,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; =20 struct clk *vclk; + struct clk *lpclk; =20 enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -979,6 +980,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device= *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); =20 + dsi->lpclk =3D devm_clk_get(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + dsi->rstc =3D devm_reset_control_get_optional_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), --=20 2.51.0