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Wed, 03 Sep 2025 09:17:32 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:9019:aa0f:b6e4:7952]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3db72983560sm5645734f8f.1.2025.09.03.09.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 09:17:31 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Tomi Valkeinen , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v8 4/6] dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N Date: Wed, 3 Sep 2025 17:17:16 +0100 Message-ID: <20250903161718.180488-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250903161718.180488-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250903161718.180488-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, the RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and requires five clocks instead of six. To reflect these hardware differences, update the binding schema to support the reduced clock and reset requirements for RZ/V2H(P). Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is reused for RZ/V2N. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Reviewed-by: Tomi Valkeinen --- v7->v8: - Added reviewed-by tags from Geert and Tomi v6->v7: - Renamed pllclk to pllrefclk - Preserved the reviewed by tag from Geert and Krzysztof v5->v6: - Preserved the sort order (by part number). - Added reviewed tag from Geert. v4->v5: - No changes v3->v4: - No changes v2->v3: - Collected reviewed tag from Krzysztof v1->v2: - Kept the sort order for schema validation - Added `port@1: false` for RZ/V2H(P) SoC --- .../bindings/display/bridge/renesas,dsi.yaml | 120 +++++++++++++----- 1 file changed, 91 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.y= aml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index 5a99d9b9635e..c20625b8425e 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,21 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. =20 -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + + - items: + - const: renesas,r9a09g056-mipi-dsi # RZ/V2N + - const: renesas,r9a09g057-mipi-dsi + - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) =20 reg: maxItems: 1 @@ -49,34 +54,56 @@ properties: - const: debug =20 clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL reference clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock =20 clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllrefclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk =20 resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N =20 reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst =20 power-domains: maxItems: 1 @@ -130,6 +157,41 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include --=20 2.51.0