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Wed, 03 Sep 2025 07:54:13 -0700 (PDT) From: Hendrik Hamerlinck To: dlan@gentoo.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Cc: skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Hendrik Hamerlinck Subject: [PATCH] riscv: dts: spacemit: add UART pinctrl combinations Date: Wed, 3 Sep 2025 16:53:34 +0200 Message-ID: <20250903145334.425633-1-hendrik.hamerlinck@hammernet.be> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds UART pinctrl configurations based on the SoC datasheet and the downstream Bianbu Linux tree. The drive strength values were taken from the downstream implementation, which uses medium drive strength. For convenience, the board DTS files have been updated to include all UART instances with their possible pinmux options in a disabled state. Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards.=20 Signed-off-by: Hendrik Hamerlinck --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 18 ++ .../boot/dts/spacemit/k1-orangepi-rv2.dts | 18 ++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 276 +++++++++++++++++- 3 files changed, 309 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 6013be258542..661d47d1ce9e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -49,3 +49,21 @@ &uart0 { pinctrl-0 =3D <&uart0_2_cfg>; status =3D "okay"; }; + +&uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart5_3_cfg>; + status =3D "disabled"; +}; + +&uart8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart8_2_cfg>; + status =3D "disabled"; +}; + +&uart9 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart9_2_cfg>; + status =3D "disabled"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/= boot/dts/spacemit/k1-orangepi-rv2.dts index 337240ebb7b7..dc45b75b1ad4 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -38,3 +38,21 @@ &uart0 { pinctrl-0 =3D <&uart0_2_cfg>; status =3D "okay"; }; + +&uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart5_3_cfg>; + status =3D "disabled"; +}; + +&uart8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart8_2_cfg>; + status =3D "disabled"; +}; + +&uart9 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart9_2_cfg>; + status =3D "disabled"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index 381055737422..43425530b5bf 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -11,12 +11,282 @@ #define K1_GPIO(x) (x / 32) (x % 32) =20 &pinctrl { + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { + pinmux =3D , /* uart0_txd */ + ; /* uart0_rxd */ + power-source =3D <3300>; + bias-pull-up; + drive-strength =3D <19>; + }; + }; + + uart0_1_cfg: uart0-1-cfg { + uart0-1-pins { + pinmux =3D , /* uart0_txd */ + ; /* uart0_rxd */ + power-source =3D <3300>; + bias-pull-up; + drive-strength =3D <19>; + }; + }; + uart0_2_cfg: uart0-2-cfg { uart0-2-pins { - pinmux =3D , - ; + pinmux =3D , /* uart0_txd */ + ; /* uart0_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; =20 - bias-pull-up =3D <0>; + uart2_0_cfg: uart2-0-cfg { + uart2-0-pins { + pinmux =3D , /* uart2_txd */ + , /* uart2_rxd */ + , /* uart2_cts */ + ; /* uart2_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart3_0_cfg: uart3-0-cfg { + uart3-0-pins { + pinmux =3D , /* uart3_txd */ + , /* uart3_rxd */ + , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart3_1_cfg: uart3-1-cfg { + uart3-1-pins { + pinmux =3D , /* uart3_txd */ + , /* uart3_rxd */ + , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart3_2_cfg: uart3-2-cfg { + uart3-2-pins { + pinmux =3D , /* uart3_txd */ + , /* uart3_rxd */ + , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart4_0_cfg: uart4-0-cfg { + uart4-0-pins { + pinmux =3D , /* uart4_txd */ + ; /* uart4_rxd */ + power-source =3D <3300>; + bias-pull-up; + drive-strength =3D <19>; + }; + }; + + uart4_1_cfg: uart4-1-cfg { + uart4-1-pins { + pinmux =3D , /* uart4_cts */ + , /* uart4_rts */ + , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart4_2_cfg: uart4-2-cfg { + uart4-2-pins { + pinmux =3D , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart4_3_cfg: uart4-3-cfg { + uart4-3-pins { + pinmux =3D , /* uart4_txd */ + , /* uart4_rxd */ + , /* uart4_cts */ + ; /* uart4_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart4_4_cfg: uart4-4-cfg { + uart4-4-pins { + pinmux =3D , /* uart4_txd */ + , /* uart4_rxd */ + , /* uart4_cts */ + ; /* uart4_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart5_0_cfg: uart5-0-cfg { + uart5-0-pins { + pinmux =3D , /* uart5_txd */ + ; /* uart5_rxd */ + power-source =3D <3300>; + bias-pull-up; + drive-strength =3D <19>; + }; + }; + + uart5_1_cfg: uart5-1-cfg { + uart5-1-pins { + pinmux =3D , /* uart5_txd */ + , /* uart5_rxd */ + , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart5_2_cfg: uart5-2-cfg { + uart5-2-pins { + pinmux =3D , /* uart5_txd */ + , /* uart5_rxd */ + , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart5_3_cfg: uart5-3-cfg { + uart5-3-pins { + pinmux =3D , /* uart5_txd */ + , /* uart5_rxd */ + , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart6_0_cfg: uart6-0-cfg { + uart6-0-pins { + pinmux =3D , /* uart6_cts */ + , /* uart6_txd */ + , /* uart6_rxd */ + ; /* uart6_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart6_1_cfg: uart6-1-cfg { + uart6-1-pins { + pinmux =3D , /* uart6_txd */ + , /* uart6_rxd */ + , /* uart6_cts */ + ; /* uart6_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart6_2_cfg: uart6-2-cfg { + uart6-2-pins { + pinmux =3D , /* uart6_txd */ + ; /* uart6_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart7_0_cfg: uart7-0-cfg { + uart7-0-pins { + pinmux =3D , /* uart7_txd */ + ; /* uart7_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart7_1_cfg: uart7-1-cfg { + uart7-1-pins { + pinmux =3D , /* uart7_txd */ + , /* uart7_rxd */ + , /* uart7_cts */ + ; /* uart7_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart8_0_cfg: uart8-0-cfg { + uart8-0-pins { + pinmux =3D , /* uart8_txd */ + ; /* uart8_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart8_1_cfg: uart8-1-cfg { + uart8-1-pins { + pinmux =3D , /* uart8_txd */ + , /* uart8_rxd */ + , /* uart8_cts */ + ; /* uart8_rts */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart8_2_cfg: uart8-2-cfg { + uart8-2-pins { + pinmux =3D , /* uart8_txd */ + , /* uart8_rxd */ + , /* uart8_cts */ + ; /* uart8_rts */ + power-source =3D <3300>; + bias-pull-up; + drive-strength =3D <19>; + }; + }; + + uart9_0_cfg: uart9-0-cfg { + uart9-0-pins { + pinmux =3D , /* uart9_txd */ + ; /* uart9_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart9_1_cfg: uart9-1-cfg { + uart9-1-pins { + pinmux =3D , /* uart9_cts */ + , /* uart9_rts */ + , /* uart9_txd */ + ; /* uart9_rxd */ + bias-pull-up; + drive-strength =3D <32>; + }; + }; + + uart9_2_cfg: uart9-2-cfg { + uart9-2-pins { + pinmux =3D , /* uart9_txd */ + ; /* uart9_rxd */ + bias-pull-up; drive-strength =3D <32>; }; }; --=20 2.43.0