From nobody Tue Dec 16 07:29:34 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B1FB2EC57C for ; Wed, 3 Sep 2025 10:59:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756897173; cv=none; b=PPMzxNQWfxiOBgivPiSApXCZshTMgp41UND3AheUL1Vwar8ee+W/hYm+F3EESG/eRoG9CYLBxaF8RzrFQLxHbqzwUWI5cXZ5iyCsBRJ3hlmWmThj3LqTSF1Ct2DgyiTj1lWTZBz4GL/W7J9kcHHcOJdJFPlx6ChEyWjFKRG8jQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756897173; c=relaxed/simple; bh=INwx13AqAfiN/OmTXiGiepnbnsp4tughoNEj7zAlXII=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=BfoIEi4X2/FzMxm/ui818WUeIG0xw2anwsRh56o4Y6wvtSY90ajE7KHAXIokrBbqR3I7l33eKX1TmjROg4isncxU24WMBHD34tBloEd8em7wUWONTrS7EOzrIJ0ZYY31U83qs3nTrsNAfZph62fny+GFphjmu8+50MJ0DDcGJf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pgG0iKLd; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pgG0iKLd" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 583AxR7g2753182; Wed, 3 Sep 2025 05:59:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756897167; bh=2ePqsIFvvYXVPKunzCWZj6k6JrCoCIdpXe0VE1H9j9g=; h=From:To:CC:Subject:Date; b=pgG0iKLdQk+VnT3dHk6ffRodif254b75gQbcy3Wbat7EiBDu/9EuzdqVRAkkuOPiA Mzgr4ECw1WNBiBWII/AD/DnfgdHuCSAolPsZhmKXB3Lznqnr6mzSG+nS+44EOd6Mxk yhmP76Op3Pu2ppzYzWtfRN0hliMymnkFD7mZ+B2Q= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 583AxRRF029452 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 3 Sep 2025 05:59:27 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 3 Sep 2025 05:59:26 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 3 Sep 2025 05:59:26 -0500 Received: from hkshenoy.dhcp.ti.com (hkshenoy.dhcp.ti.com [172.24.235.208]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 583AxMR21169200; Wed, 3 Sep 2025 05:59:23 -0500 From: Harikrishna Shenoy To: , , , , , , , , , , CC: Subject: [PATCH] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register Date: Wed, 3 Sep 2025 16:29:22 +0530 Message-ID: <20250903105922.2602183-1-h-shenoy@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in TRM Table 2-1 MAIN Domain Memory Map. Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY") Signed-off-by: Harikrishna Shenoy --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index ab3666ff4297..3fa7537d5414 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 { * the PHY driver. */ reg =3D <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_AP= B */ - <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + <0x00 0x04f40000 0x00 0x100>; /* DSS_EDP0_INTG_CFG_VP */ reg-names =3D "mhdptx", "j721e-intg"; =20 clocks =3D <&k3_clks 151 36>; --=20 2.34.1