From nobody Fri Oct 3 08:52:33 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B81E2DA74D for ; Wed, 3 Sep 2025 07:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884582; cv=none; b=Zlh82YUtD0Fgg5WXy6qxWUhiL5uXnJlB1w1A1164m/GpgCmE/iYLwVfkfCXvDixXhFiCevomKMB5L0fAS/IVBmdneQewPQE45CRGktB9nGoZuXqlHF4tSu6PKXTUV/Cn6RxOv05/npoEIc6RHnRMcsv20BtlOwjCb4VZv93wuRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884582; c=relaxed/simple; bh=d+P1sCzPwT6rsH5h10bLtBk+dAxWn3P60LDgemHQfwE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=LDuUSDhJZ6inTqL4IDdBk7U+uB18IkeEg0kbDhyEGJ1dr8qXHqetZLtrQKgmseUV1g0vwSahGZWsiLkD3QwJOvl4cHYcZkQj3Up349Fq0CK5e5ZAVSaVT7Q4Ws5xInpDyzDDrO9LgXzN3GVxViy1P/OWkMgbsg9B8sHFNstJ5W0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Efuz+Vbw; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Efuz+Vbw" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250903072938epoutp01c6348dc397bfe14cc35a2380cce0209a~htTdRdfsl1339713397epoutp01y for ; Wed, 3 Sep 2025 07:29:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250903072938epoutp01c6348dc397bfe14cc35a2380cce0209a~htTdRdfsl1339713397epoutp01y DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884578; bh=1cHHzvpcToVfUQ+s6oKU0F9PCcevPZTTm727qZ7syWg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Efuz+Vbwwk8pbAgOELhnkw7hJu1m8keUdVoSODbouG7xhGThr6vyO1uULlJFKmh1c hvBNyY2zj/iznMaBT9BphmP2w9KrirP60YU5uGZxITVaJBRzi/FZGZPHyT2vIVvyTF 5lz4f9Ighpe8Nx5gOE7c/kjDSjESnnZlsT4bUlNY= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250903072937epcas5p363acb7df02fcdd202b8299e1b35f697e~htTccMDIK2807428074epcas5p3D; Wed, 3 Sep 2025 07:29:37 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.92]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4cGvPr5vCcz6B9m5; Wed, 3 Sep 2025 07:29:36 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250903072936epcas5p4a28d0e63c7f0792b516b0cbc68bf3a8e~htTa3DKDo2045620456epcas5p4v; Wed, 3 Sep 2025 07:29:36 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072932epsmtip20e01ed3ee241f03e3553f0744bf70758~htTXz-USp2480024800epsmtip2N; Wed, 3 Sep 2025 07:29:32 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 1/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible Date: Wed, 3 Sep 2025 13:08:22 +0530 Message-Id: <20250903073827.3015662-2-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072936epcas5p4a28d0e63c7f0792b516b0cbc68bf3a8e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072936epcas5p4a28d0e63c7f0792b516b0cbc68bf3a8e References: <20250903073827.3015662-1-pritam.sutar@samsung.com> Document support for the USB20 phy found on the ExynosAutov920 SoC. The USB20 phy is functionally identical to that on the Exynos850 SoC, so no driver changes are needed to support this phy. However, add a dedicated compatible string for USB20 phy found in this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index e906403208c0..8d8114eb5660 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy =20 clocks: minItems: 1 @@ -110,6 +111,15 @@ properties: vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. =20 + dvdd-supply: + description: 0.75V power supply for the USB phy. + + vdd18-supply: + description: 1.8V power supply for the USB phy. + + vdd33-supply: + description: 3.3V power supply for the USB phy. + required: - compatible - clocks @@ -219,6 +229,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy then: properties: clocks: @@ -236,6 +247,24 @@ allOf: reg-names: maxItems: 1 =20 + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-usbdrd-phy + then: + required: + - dvdd-supply + - vdd18-supply + - vdd33-supply + + else: + properties: + dvdd-supply: false + vdd18-supply: false + vdd33-supply: false + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Fri Oct 3 08:52:33 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE0682DA755 for ; Wed, 3 Sep 2025 07:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884586; cv=none; b=ddbs8KbkNhNyJCE4TB3JS37483gg3lK48+ghNhsnEvJSn0ziI8j7Dib3uoyoBmUXMMLnh1pcKO2qvpsKqbFGmCamXhU7qNZOASYQfENeb6GKX3aj6CrWqHVR5tVh3UZ1feLjOYMcaZCrksXi63tJUT7hFiLYRaZiJNVLwrbRyII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884586; c=relaxed/simple; bh=Gm2E2sJtKFZPhVOnzdaJMksHNnXrrhbi06hGWGdtWm4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=i9BkTVBrq3rQ0I0zQueusYaiN8brz+CQkrWMD1OwttGoEf2kMMDi+Vllp1X2r/10kl8Sqhpx2b9PaSJxkOUG36T6KDw+o+XibLSxkuOEVk3/UAOU2OwiuIzty5tPx6vnHCmK/f7OHdqSi0Uv000V4m0cnCCzqk2H9q6PrPs1DUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=ocj6b0Mk; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="ocj6b0Mk" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250903072941epoutp048dcc64609602453d38b09a078ede7cf4~htTgLyQlD0137101371epoutp04Y for ; Wed, 3 Sep 2025 07:29:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250903072941epoutp048dcc64609602453d38b09a078ede7cf4~htTgLyQlD0137101371epoutp04Y DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884582; bh=cZe9429oyNXrWvEpscYQyeVvvnpZ7FV59KJwa3UHBBo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ocj6b0MkI+oEGtBeb89BXZrO1+Za9l7Zekvha+WMQo/6cOHM5+4jY5/wvRMnMcCmW druuYvzJzjwxr2b+fQHKuqwwMrcxi/6XXeJIG7P/1AMhkrOxcFSlmbKVnKDlOI7Emx OEnId6njIkFh1IU00qzACZxxKZTXQQJg0qUEcg98= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250903072941epcas5p32e859f04d7b72cca5f74526f01689f10~htTfbCa7g2832228322epcas5p3J; Wed, 3 Sep 2025 07:29:41 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.88]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4cGvPv74x0z2SSKh; Wed, 3 Sep 2025 07:29:39 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250903072939epcas5p4b36818cd2e2b5c59fdd4a1b90579eb47~htTdxvOTE2774827748epcas5p4y; Wed, 3 Sep 2025 07:29:39 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072936epsmtip25f75eeda0e67e8aa7a95aed9507ccc9b~htTa5q2ev2487024870epsmtip2d; Wed, 3 Sep 2025 07:29:36 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Date: Wed, 3 Sep 2025 13:08:23 +0530 Message-Id: <20250903073827.3015662-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072939epcas5p4b36818cd2e2b5c59fdd4a1b90579eb47 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072939epcas5p4b36818cd2e2b5c59fdd4a1b90579eb47 References: <20250903073827.3015662-1-pritam.sutar@samsung.com> Enable UTMI+ phy support for this SoC which is very similar to what the existing Exynos850 supports. Add required change in phy driver to support HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 123 ++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 125 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index a88ba95bdc8f..dfc2cc71e579 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -2054,6 +2054,126 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* Bypass PHY isol */ + inst->phy_cfg->phy_isol(inst, false); + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret =3D regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_usb20_regulators[] =3D { + "dvdd", "vdd18", "vdd33", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] =3D= { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = =3D { + .phy_cfg =3D phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb20_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2380,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-phy", + .data =3D &exynosautov920_usbdrd_phy }, { }, }; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 71e0c09a49eb..4923f9be3d1f 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -688,4 +688,6 @@ #define GS101_GRP2_INTR_BID_UPEND (0x0208) #define GS101_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* exynosautov920 */ +#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1 From nobody Fri Oct 3 08:52:33 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E21C72DECDF for ; Wed, 3 Sep 2025 07:29:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884589; cv=none; b=aD2/3vxvsXA1l36XDjuoVZLTwouZANzLQtxWWXAFL8Rg7x8M3KbM4S1eswMeSE+3t1sQzWw2C3EehMd5HXNB/9bzDBDO5ENSR5MaZOZVwKBTcjNDEMS101daJPxQioGxCKB1cZM449b/bYiymEjf4QyWYXUOp/kVRDMTff4nG0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884589; c=relaxed/simple; bh=AccgHMjhdT5b8PhDHeBEe8SY7qfzk70Mw1MG6hqDEo0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=sSSg31C4C1h9ruEsBixcmVoAnEab8RBjAfycLGRfq1zOuBUwSR15qJ4XzXDeeXb763jRJbZaHj53ghX1u2iZe3/5kY3LvViaMEujqjh1KlmfA896a+x/q+Up8dtiUiNn4TI/GUP9QAoEn5IorhNEyKokqh+M1YooBI9jRt5Yr6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=I0Dze26X; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="I0Dze26X" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250903072945epoutp04f939cce35f7cf1013a5018814cb2e1d6~htTjGZZqi3174331743epoutp04Z for ; Wed, 3 Sep 2025 07:29:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250903072945epoutp04f939cce35f7cf1013a5018814cb2e1d6~htTjGZZqi3174331743epoutp04Z DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884585; bh=U8biUgrbmhqoy6ImwYHNZ85z7bDPbo86mIUx8VSMBxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I0Dze26XPryFpTCs+1wxaIKAifxm8NmL2jCygMKbFw/KQy7Jb0aOAMn+tUCc5tZV4 jV0o3ykGLexR+OA1rCpjMM8+ztOFPT16O0+jHX9PiCNYBwEx3Qz3aPTf+1Zu2Q0irj f/smhA90zhg36xVn7nivtMqUC1KpQCYi9pgCz/ZI= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250903072944epcas5p31eb60c88907761fda0defbcfa85ee83e~htTiY2_Cu2293822938epcas5p31; Wed, 3 Sep 2025 07:29:44 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.87]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4cGvPz2T8Yz3hhTD; Wed, 3 Sep 2025 07:29:43 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250903072942epcas5p2154a85b45152af50e2714248c38c5adc~htTg3bZdO1236712367epcas5p2g; Wed, 3 Sep 2025 07:29:42 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072939epsmtip2455dc285a7eb49093c51aabf1e508bac~htTeA3VNU2549225492epsmtip2G; Wed, 3 Sep 2025 07:29:39 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 3/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo hsphy Date: Wed, 3 Sep 2025 13:08:24 +0530 Message-Id: <20250903073827.3015662-4-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072942epcas5p2154a85b45152af50e2714248c38c5adc X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072942epcas5p2154a85b45152af50e2714248c38c5adc References: <20250903073827.3015662-1-pritam.sutar@samsung.com> The USBDRD31 5nm controller consists of Synopsys USB2.0 femptophy and USBSS combophy. Add-on USB20 femptophy is required to support USB20 data rates along with USBSS phy. Document support for the USB2.0 femptophy found on combophy of the this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- .../devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 8d8114eb5660..4a8bcf63cd91 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 clocks: @@ -229,6 +230,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: properties: @@ -252,6 +254,7 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: required: --=20 2.34.1 From nobody Fri Oct 3 08:52:33 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140B62DFF0D for ; Wed, 3 Sep 2025 07:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884592; cv=none; b=mClzCCly5jub3vp7/d4F9hNUn2Uta3THJ8mCMj4vbbGnw27efZijqNZRhfc9l8DfzsnOBc5BDDZ15Xp0JdbUDXJWj29CWCQF74ogYnPR0NSnroxVN0FeptVKQQaCRJTnolWSXHhSMW9TbarjIMiGBg+8f3fE8Fpj+/yjTqBdFYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884592; c=relaxed/simple; bh=VSIW0s3H6+4nsFXwzxG606WycV9wMM1tR0jX8+lRdDc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=sh4Mld7iX7wvDqi9YPHH3fZw2jeyBR6UztJcYJ15lNsYaYUqkFW2ASIKEIu4h1WJWNF5BcmhpN4GrrXQDRQ5rzNfLev6gVIvfhBI3YI4eGDsyeHVnShFGszkp/mrJNY+TOZTIzW6kDzmIeZKDKC271iMVFB451CyYjYvPMRss+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=Y4EQOn+e; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="Y4EQOn+e" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250903072948epoutp0265864782164668bd0d1c8072f1dd3f59~htTmQQ90n3170331703epoutp02b for ; Wed, 3 Sep 2025 07:29:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250903072948epoutp0265864782164668bd0d1c8072f1dd3f59~htTmQQ90n3170331703epoutp02b DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884588; bh=zwyovO0ASEWGRpGzQGQdUfUh30qf34h0maaSJcAyoVU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y4EQOn+eRn+X2nWMztQDli0ToGXKve3WrUWZddKQCZ6wtPWlo+zizde6SLukqt+jK N/4y8By3ptWNPgUr+fqDMHqazlwqz61eV9g8o3HS4eV90Dd566W30mL6QtV60XRs9H H47m2t9SfBYlzAw9dg4G+u3nl+smJn/N92RxsDDY= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250903072947epcas5p2444604a2356154af605746e59479ae1a~htTlfF1Df1236712367epcas5p2r; Wed, 3 Sep 2025 07:29:47 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.86]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4cGvQ253s6z2SSKZ; Wed, 3 Sep 2025 07:29:46 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250903072946epcas5p371f7d0e15d8757f738c08f80a8eefb60~htTkAnYzY2293822938epcas5p36; Wed, 3 Sep 2025 07:29:46 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072942epsmtip2b4e3eaf3636d0132734a9f1c1b9c2919~htThGciqr2480024800epsmtip2S; Wed, 3 Sep 2025 07:29:42 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 4/6] phy: exynos5-usbdrd: support HS combo phy for ExynosAutov920 Date: Wed, 3 Sep 2025 13:08:25 +0530 Message-Id: <20250903073827.3015662-5-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072946epcas5p371f7d0e15d8757f738c08f80a8eefb60 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072946epcas5p371f7d0e15d8757f738c08f80a8eefb60 References: <20250903073827.3015662-1-pritam.sutar@samsung.com> Support UTMI+ combo phy for this SoC which is somewhat simmilar to what the existing Exynos850 support does. The difference is that some register offsets and bit fields are defferent from Exynos850. Add required change in phy driver to support combo HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 211 +++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index dfc2cc71e579..c52b0e25a423 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -41,6 +41,13 @@ #define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1) =20 #define EXYNOS2200_DRD_UTMI 0x10 + +/* ExynosAutov920 bits */ +#define UTMICTL_FORCE_UTMI_SUSPEND BIT(13) +#define UTMICTL_FORCE_UTMI_SLEEP BIT(12) +#define UTMICTL_FORCE_DPPULLDOWN BIT(9) +#define UTMICTL_FORCE_DMPULLDOWN BIT(8) + #define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1) #define EXYNOS2200_UTMI_FORCE_BVALID BIT(0) =20 @@ -250,6 +257,22 @@ #define EXYNOS850_DRD_HSP_TEST 0x5c #define HSP_TEST_SIDDQ BIT(24) =20 +#define EXYNOSAUTOV920_DRD_HSP_CLKRST 0x100 +#define HSPCLKRST_PHY20_SW_PORTRESET BIT(3) +#define HSPCLKRST_PHY20_SW_POR BIT(1) +#define HSPCLKRST_PHY20_SW_POR_SEL BIT(0) + +#define EXYNOSAUTOV920_DRD_HSPCTL 0x104 +#define HSPCTRL_VBUSVLDEXTSEL BIT(13) +#define HSPCTRL_VBUSVLDEXT BIT(12) +#define HSPCTRL_EN_UTMISUSPEND BIT(9) +#define HSPCTRL_COMMONONN BIT(8) + +#define EXYNOSAUTOV920_DRD_HSP_TEST 0x10c + +#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 +#define HSPPLLTUNE_FSEL GENMASK(18, 16) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2054,6 +2077,140 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This + * forces QACTIVE signal in Q-Channel interface to HIGH level, + * to make sure the PHY clock is not gated by the hardware. + */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* De-assert link reset */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + + /* Set PHY POR High */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_POR_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* Enable UTMI+ */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg &=3D ~(UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP | + UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_EN_UTMISUSPEND | HSPCTRL_COMMONONN; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + fsleep(100); + + /* Set VBUS Valid and DP-Pull up control by VBUS pad usage */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D EXYNOS2200_UTMI_FORCE_VBUSVALID | EXYNOS2200_UTMI_FORCE_BVALID; + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_VBUSVLDEXTSEL | HSPCTRL_VBUSVLDEXT; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + /* Setting FSEL for refference clock */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + reg &=3D ~HSPPLLTUNE_FSEL; + + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + + /* Enable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg &=3D ~HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* before POR low, 10us delay is needed to Finish PHY reset */ + fsleep(10); + + /* Set PHY POR Low */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR_SEL; + reg &=3D ~(HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_PORTRESET); + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ + fsleep(75); + + /* force pipe3 signal for link */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_PIPE_EN; + reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; + reg |=3D LINKCTRL_FORCE_RXELECIDLE; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); +} + +static void +exynosautov920_usbdrd_hsphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + u32 reg; + void __iomem *reg_phy =3D phy_drd->reg_phy; + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP; + reg &=3D ~(UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* Disable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg |=3D HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* clear force q-channel */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg &=3D ~LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* link sw reset is need for USB_DP/DM high-z in host mode */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + fsleep(10); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); +} + static int exynosautov920_usbdrd_phy_init(struct phy *phy) { struct phy_usb_instance *inst =3D phy_get_drvdata(phy); @@ -2095,6 +2252,27 @@ static int exynosautov920_usbdrd_phy_exit(struct phy= *phy) return 0; } =20 +static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret =3D 0; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) + exynosautov920_usbdrd_hsphy_disable(phy_drd); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) { struct phy_usb_instance *inst =3D phy_get_drvdata(phy); @@ -2146,6 +2324,36 @@ static const char * const exynosautov920_usb20_regul= ators[] =3D { "dvdd", "vdd18", "vdd33", }; =20 +static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct +exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usbdrd_utmi_init, + }, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_combo_hsphy =3D { + .phy_cfg =3D usbdrd_hsphy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_combo_hsphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb20_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_phy_exit, @@ -2380,6 +2588,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", + .data =3D &exynosautov920_usbdrd_combo_hsphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-phy", .data =3D &exynosautov920_usbdrd_phy --=20 2.34.1 From nobody Fri Oct 3 08:52:33 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88822DCBFD for ; Wed, 3 Sep 2025 07:29:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884595; cv=none; b=oh00ffMVKk/GVFvrYuIXGXQvdw5ciQMLJO+FwTKdq+5uQUAsoal24gwSJ58GU9HQ5bkB0rDoXYORLH/095e0j9nBAHgx7RHV7HonJjjCAEMYt3zkiWnXWVRcksMqg9PCq5oLo3S43ZwQ1T9ApDIvCEveGGcJ/+cxN7/YFSm9nZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884595; c=relaxed/simple; bh=NnwsCIAo9crWwevyth/UDVKqxje3frkUx9ImbIZzwgU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=msgtvXUhjC66gxoZToXnifDaVRE/tyVyDXj5rCJ1vQ6zB+q8a1ZUs+oyVuMak2Mx4ImemlbL/0sXPCXMxS9aZa0JsT4hvOsj2sI4j8kq9+2ThmQ7aMy9LA/P1QMDXgxbUQkuYugy8L4ECWycc4SJR3C5CSOMlHCeDbFyqCp4EjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=UCk+SPk4; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="UCk+SPk4" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250903072952epoutp04805d10fe44888f6ecc3b2194123571b2~htTpozNEW3244932449epoutp04I for ; Wed, 3 Sep 2025 07:29:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250903072952epoutp04805d10fe44888f6ecc3b2194123571b2~htTpozNEW3244932449epoutp04I DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884592; bh=TpuYL4TT61lQI9x+lJB1ZTckMbvty0pgE6VMnOCTsnw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UCk+SPk4mku7KQMh1sLhcUfFM2ajMqPk/yMDVugl1jV3cekR+2xgLU7x3ITPx9iYC KHMQ/CqBTudMpS711QDqN2sdTdp9yma0d6/EEiF+Sp5+lnInykCvFQ44l1bxNM3hl1 jOvWseO9n3YK2+bwbCrnfr41O3DS86QcXoRFFrzc= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20250903072951epcas5p2532bcdf559d1db330fdc8619e96a8460~htTo9aiZS1205312053epcas5p2I; Wed, 3 Sep 2025 07:29:51 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.95]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4cGvQ62bDHz3hhTS; Wed, 3 Sep 2025 07:29:50 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250903072949epcas5p11a1e474fad83ff3036be2c443ed5bc35~htTnHrOau2114721147epcas5p1K; Wed, 3 Sep 2025 07:29:49 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072946epsmtip2c4c26661b9c4e852e257cab46c8c124e~htTkPc_AO2480024800epsmtip2T; Wed, 3 Sep 2025 07:29:46 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo ssphy Date: Wed, 3 Sep 2025 13:08:26 +0530 Message-Id: <20250903073827.3015662-6-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072949epcas5p11a1e474fad83ff3036be2c443ed5bc35 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072949epcas5p11a1e474fad83ff3036be2c443ed5bc35 References: <20250903073827.3015662-1-pritam.sutar@samsung.com> The USBDRD31 5nm controller consists of Synopsys USB20 femptoPhy and USB31 SSP+ combophy. Document support for the USB31 SSP+ phy found on combophy of the ExynosAutov920 SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 4a8bcf63cd91..72d41ccdb090 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 @@ -230,6 +231,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: @@ -254,18 +256,32 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: required: - dvdd-supply - vdd18-supply - - vdd33-supply =20 else: properties: dvdd-supply: false vdd18-supply: false + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-usbdrd-combo-hsphy + - samsung,exynosautov920-usbdrd-phy + then: + required: + - vdd33-supply + + else: + properties: vdd33-supply: false =20 unevaluatedProperties: false --=20 2.34.1 From nobody Fri Oct 3 08:52:33 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A28B52DAFBB for ; Wed, 3 Sep 2025 07:29:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884599; cv=none; b=gSiwGmmBJy4zAyCZdcKWOgOwZsPcqt3ScZfLVuwn8wnZXPtMjp24r5/i6UJij3OF4Wqg7K4RZimWpyRXziMDiHuszV5nOEYzxgWXeD4wFPcIW8st+KVLpDnLp9xyrHMBxVJB6BK5BA550MpueWWQiNLBReHFQrcUkUabUIIqjyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756884599; c=relaxed/simple; bh=+giTEm0adYYpa8mNqgrwEqgmh4I2X5VhDzLDTgU5/Es=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=eDARYHStQTlqcqMxoNCEahlVV9/m4J/64SYZrWxIuhnMYPuBdRxK/67dwXrFrLLf5SFaka2tpuB7NNQwF+Q48dsCw5XFrWb1uz0wW7F09AYoNTTTdbXyNxXIc6qiFh1CIIHEiPtGwTGkar1/RR6m5AiIxjB9KSL2tTEFjuKrTOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=GwLESgLe; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="GwLESgLe" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250903072954epoutp038e31ff16494371e278d49e83c1776ac2~htTsPFrTT2355823558epoutp03f for ; Wed, 3 Sep 2025 07:29:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250903072954epoutp038e31ff16494371e278d49e83c1776ac2~htTsPFrTT2355823558epoutp03f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756884594; bh=UZHovCT0y+Y1M1P5CFLdOpLT99/IG7Uzy3gUbPfjVos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GwLESgLe3B+J3JAD36cPWCY8qNs7uLxK3a1MFdTfyaoR9tt8uj1Y5Trhsy2Xx0zV5 g8GGB/cEo+VimA5615TWBCFJ+7vGfeO+VT8uKRfNF9MmS+8NjUNxa/5/M4KfLaj0I3 aXTW4iF1pijxcC+WYxFIVP55KQNTZBG9gGu8KLXA= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250903072954epcas5p1a88a7b97ab50b787f7054a8f15771beb~htTrqTQa40696306963epcas5p1E; Wed, 3 Sep 2025 07:29:54 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.86]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4cGvQ92XyFz6B9mG; Wed, 3 Sep 2025 07:29:53 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250903072952epcas5p38eaa34521236ad10d963783137748069~htTqPGBK-2832228322epcas5p3e; Wed, 3 Sep 2025 07:29:52 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250903072949epsmtip2677b22f283712236a68984197c0e4ad2~htTnWyekp2475724757epsmtip2A; Wed, 3 Sep 2025 07:29:49 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v8 6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920 Date: Wed, 3 Sep 2025 13:08:27 +0530 Message-Id: <20250903073827.3015662-7-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903073827.3015662-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250903072952epcas5p38eaa34521236ad10d963783137748069 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250903072952epcas5p38eaa34521236ad10d963783137748069 References: <20250903073827.3015662-1-pritam.sutar@samsung.com> Add required change in phy driver to support combo SS phy for this SoC. Signed-off-by: Pritam Manohar Sutar Reviewed-by: Alim Akhtar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 325 +++++++++++++++++++- include/linux/soc/samsung/exynos-regs-pmu.h | 1 + 2 files changed, 322 insertions(+), 4 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index c52b0e25a423..53a5b72ff249 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -273,6 +273,36 @@ #define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 #define HSPPLLTUNE_FSEL GENMASK(18, 16) =20 +/* ExynosAutov920 phy usb31drd port reg */ +#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000 +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5) +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4) +#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1) +#define PHY_RST_CTRL_PHY_RESET BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004 +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008 + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0) +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100 +#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14) +#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13) +#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c +#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110 +#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2077,6 +2107,251 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool hi= gh) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if (high) + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + else + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + fsleep(1); +} + +static void +exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd) +{ + struct device *dev =3D phy_drd->dev; + void __iomem *reg_phy =3D phy_drd->reg_phy; + static const unsigned int timeout_us =3D 20000; + static const unsigned int sleep_us =3D 40; + u32 reg; + int err; + + /* Clear cr_para_con */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &=3D ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * The maximum time from phy reset de-assertion to de-assertion of + * tx/rx_ack can be as high as 5ms in fast simulation mode. + * Time to phy ready is < 20ms + */ + err =3D readl_poll_timeout(reg_phy + + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0, + reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK), + sleep_us, timeout_us); + if (err) + dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); +} + +static void +exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd, + u16 addr, u16 data) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 cnt =3D 0; + u32 reg; + + /* Pre Clocking */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx clks must be available prior to assertion of tx req. + * tx pstate p2 to p0 transition directly is not permitted. + * tx clk ready must be asserted synchronously on tx clk prior + * to internal transmit clk alignment sequence in the phy + * when entering from p2 to p1 to p0. + */ + do { + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + cnt++; + } while (cnt < 15); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx data path is active when tx lane is in p0 state + * and tx data en asserted. enable cr_para_wr_en. + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + reg &=3D ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) | + PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + /* write addr */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) | + PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* check cr_para_ack*/ + cnt =3D 0; + do { + /* + * data symbols are captured by phy on rising edge of the + * tx_clk when tx data enabled. + * completion of the write cycle is acknowledged by assertion + * of the cr_para_ack. + */ + exynosautov920_usb31drd_cr_clk(phy_drd, true); + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK)) + break; + + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * wait for minimum of 10 cr_para_clk cycles after phy reset + * is negated, before accessing control regs to allow for + * internal resets. + */ + cnt++; + } while (cnt < 10); + + if (cnt < 10) + exynosautov920_usb31drd_cr_clk(phy_drd, false); +} + +static void +exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int = val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg &=3D ~PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg |=3D PHY_RST_CTRL_PHY_RESET; + else + reg &=3D ~PHY_RST_CTRL_PHY_RESET; + + reg |=3D PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, in= t val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N; + else + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N; + + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Phy and Pipe Lane reset assert. + * assert reset (phy_reset =3D 1). + * The lane-ack outputs are asserted during reset (tx_ack =3D rx_ack =3D = 1) + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + + /* + * ANA Power En, PCS & PMA PWR Stable Set + * ramp-up power suppiles + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + reg |=3D PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE | + PHY_CONFIG0_PHY0_PMA_PWR_STABLE; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + + fsleep(10); + + /* + * phy is not functional in test_powerdown mode, test_powerdown to be + * de-asserted for normal operation + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg &=3D ~PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + + /* + * phy reset signal be asserted for minimum 10us after power + * supplies are ramped-up + */ + fsleep(10); + + /* + * Phy and Pipe Lane reset assert de-assert + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 0); + exynosautov920_usb31drd_lane0_reset(phy_drd, 0); + + /* Pipe_rx0_sris_mode_en =3D 1 */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + reg |=3D PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + + /* + * wait for lane ack outputs to de-assert (tx_ack =3D rx_ack =3D 0) + * Exit from the reset state is indicated by de-assertion of *_ack + */ + exynosautov920_usb31drd_port_phy_ready(phy_drd); + + /* override values for level settings */ + exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5); +} + +static void +exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* 1. Assert reset (phy_reset =3D 1) */ + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + + /* phy test power down */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg |=3D PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); +} + static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) { @@ -2172,12 +2447,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbd= rd_phy *phy_drd) /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ fsleep(75); =20 - /* force pipe3 signal for link */ + /* Disable forcing pipe interface */ reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); - reg |=3D LINKCTRL_FORCE_PIPE_EN; - reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; - reg |=3D LINKCTRL_FORCE_RXELECIDLE; + reg &=3D ~LINKCTRL_FORCE_PIPE_EN; writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* Pclk to pipe_clk */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D EXYNOS2200_CLKRST_LINK_PCLK_SEL; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); } =20 static void @@ -2264,6 +2542,8 @@ static int exynosautov920_usbdrd_combo_phy_exit(struc= t phy *phy) =20 if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) exynosautov920_usbdrd_hsphy_disable(phy_drd); + else if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_PIPE3) + exynosautov920_usb31drd_ssphy_disable(phy_drd); =20 /* enable PHY isol */ inst->phy_cfg->phy_isol(inst, true); @@ -2320,10 +2600,44 @@ static int exynosautov920_usbdrd_phy_power_off(stru= ct phy *phy) return 0; } =20 +static const char * const exynosautov920_usb30_regulators[] =3D { + "dvdd", "vdd18", +}; + static const char * const exynosautov920_usb20_regulators[] =3D { "dvdd", "vdd18", "vdd33", }; =20 +static const struct +exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_PIPE3, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usb31drd_pipe3_init, + }, +}; + +static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy =3D { + .phy_cfg =3D usb31drd_phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usb31drd_combo_ssphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB31, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb30_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb30_regulators), +}; + static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_combo_phy_exit, @@ -2588,6 +2902,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usb31drd-combo-ssphy", + .data =3D &exynosautov920_usb31drd_combo_ssphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", .data =3D &exynosautov920_usbdrd_combo_hsphy diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 4923f9be3d1f..f96c773b85c9 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -690,4 +690,5 @@ =20 /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) +#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1