From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BD132D8DBB; Wed, 3 Sep 2025 06:47:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882045; cv=none; b=sA1/97DtMU7zhqRkihQ7HJ18yOezni+Z67rFNXydJScm6Uecgu0S12QG54DCwawzrEP0zhEvBBWgRvYEaYenSM9SvMi9mNUwJO7I7N8eqIpKMlc8ipWYProbK/Irqwzhgn13N2Dvgj3N7NUP+No+afTPQN5GDuIF0h93LWWYwc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882045; c=relaxed/simple; bh=fT3sDIHjSujlwY4VLBHqNBqr18zjKD3cM+JhfiCXGY0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U0ZylNs8vUBl46Zdm/72C9FV+/tz8O4WggTF/7YWx7SFHvkONb8woSX5kulw8io2Q5W9VDYxWkt3K3EY/ySXiYmQolCPGv/ioAAXck5Oki9k4z6wSxQpz+Q6850jwH7spNDy89qLSAeqrbPIYmXN3ROx3bB8OcyACjHrVOIdY9s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I2uj9oo1; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I2uj9oo1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882043; x=1788418043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fT3sDIHjSujlwY4VLBHqNBqr18zjKD3cM+JhfiCXGY0=; b=I2uj9oo1yUC0A1ySH1AGxZHynazr4MmB4u17uV36k0a8SpJlCmozXo/O z8l2Fnstx5G5fgp7HI+MIF5uLJUgo0aQS8IkzirtHIvUomVHO+gDm9Fh6 FQS396ThJpV77RjT2HCjcfHgTjNd6MRwxv8L7QRhSoVu3TWrCVZzUZbqa ZlYlnXhWsy7kq+6OT3LGodHrR/rUDp2bpwItQmhS4YtvNmnavZx+AyJHB ws4ePSZbfTqJpwMgdMEWGrMyT/4/Gl7OmlHnMcx0sXOOyZQ8DRartxvJB XcAjei0BIpjx+FqvkfkYT/d6spqyujxuvJiuHmZ71NslVCTO+jkrtkRnY w==; X-CSE-ConnectionGUID: Y5Su2BURQ+Cr723a9IoxVg== X-CSE-MsgGUID: VBMplUriQmabEXLVCSi/lg== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003767" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003767" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:23 -0700 X-CSE-ConnectionGUID: 9DDQH7J6Q7eCm4Mq+wy5CA== X-CSE-MsgGUID: 2aLHXF9aRl+b6l31inNhvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656534" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:19 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi , Yi Lai Subject: [kvm-unit-tests patch v3 1/8] x86/pmu: Add helper to detect Intel overcount issues Date: Wed, 3 Sep 2025 14:45:54 +0800 Message-Id: <20250903064601.32131-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng For Intel Atom CPUs, the PMU events "Instruction Retired" or "Branch Instruction Retired" may be overcounted for some certain instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD and complex SGX/SMX/CSTATE instructions/flows. The detailed information can be found in the errata (section SRF7): https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-cores-sp= ecification-update/errata-details/ For the Atom platforms before Sierra Forest (including Sierra Forest), Both 2 events "Instruction Retired" and "Branch Instruction Retired" would be overcounted on these certain instructions, but for Clearwater Forest only "Instruction Retired" event is overcounted on these instructions. So add a helper detect_inst_overcount_flags() to detect whether the platform has the overcount issue and the later patches would relax the precise count check by leveraging the gotten overcount flags from this helper. Signed-off-by: dongsheng [Rewrite comments and commit message - Dapeng] Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/processor.h | 27 ++++++++++++++++++++++++++ x86/pmu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 62f3d578..937f75e4 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -1188,4 +1188,31 @@ static inline bool is_lam_u57_enabled(void) return !!(read_cr3() & X86_CR3_LAM_U57); } =20 +/* Copy from kernel arch/x86/lib/cpu.c */ +static inline u32 x86_family(u32 sig) +{ + u32 x86; + + x86 =3D (sig >> 8) & 0xf; + + if (x86 =3D=3D 0xf) + x86 +=3D (sig >> 20) & 0xff; + + return x86; +} + +static inline u32 x86_model(u32 sig) +{ + u32 fam, model; + + fam =3D x86_family(sig); + + model =3D (sig >> 4) & 0xf; + + if (fam >=3D 0x6) + model +=3D ((sig >> 16) & 0xf) << 4; + + return model; +} + #endif diff --git a/x86/pmu.c b/x86/pmu.c index a6b0cfcc..87365aff 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -159,6 +159,14 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; =20 +/* + * Flags for Intel "Instruction Retired" and "Branch Instruction Retired" + * overcount flaws. + */ +#define INST_RETIRED_OVERCOUNT BIT(0) +#define BR_RETIRED_OVERCOUNT BIT(1) +static u32 intel_inst_overcount_flags; + static int has_ibpb(void) { return this_cpu_has(X86_FEATURE_SPEC_CTRL) || @@ -959,6 +967,43 @@ static void check_invalid_rdpmc_gp(void) "Expected #GP on RDPMC(64)"); } =20 +/* + * For Intel Atom CPUs, the PMU events "Instruction Retired" or + * "Branch Instruction Retired" may be overcounted for some certain + * instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD + * and complex SGX/SMX/CSTATE instructions/flows. + * + * The detailed information can be found in the errata (section SRF7): + * https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-core= s-specification-update/errata-details/ + * + * For the Atom platforms before Sierra Forest (including Sierra Forest), + * Both 2 events "Instruction Retired" and "Branch Instruction Retired" wo= uld + * be overcounted on these certain instructions, but for Clearwater Forest + * only "Instruction Retired" event is overcounted on these instructions. + */ +static u32 detect_inst_overcount_flags(void) +{ + u32 flags =3D 0; + struct cpuid c =3D cpuid(1); + + if (x86_family(c.a) =3D=3D 0x6) { + switch (x86_model(c.a)) { + case 0xDD: /* Clearwater Forest */ + flags =3D INST_RETIRED_OVERCOUNT; + break; + + case 0xAF: /* Sierra Forest */ + case 0x4D: /* Avaton, Rangely */ + case 0x5F: /* Denverton */ + case 0x86: /* Jacobsville */ + flags =3D INST_RETIRED_OVERCOUNT | BR_RETIRED_OVERCOUNT; + break; + } + } + + return flags; +} + int main(int ac, char **av) { int instruction_idx; @@ -985,6 +1030,8 @@ int main(int ac, char **av) branch_idx =3D INTEL_BRANCHES_IDX; branch_miss_idx =3D INTEL_BRANCH_MISS_IDX; =20 + intel_inst_overcount_flags =3D detect_inst_overcount_flags(); + /* * For legacy Intel CPUS without clflush/clflushopt support, * there is no way to force to trigger a LLC miss, thus set --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D29022D94BC; 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charset="utf-8" From: dongsheng As the VM-Exit/VM-Entry overcount issue on Intel Atom platforms, there is no way to validate the precise count for "instructions" and "branches" events on these overcounted Atom platforms. Thus relax the precise count validation on these overcounted platforms. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 87365aff..04946d10 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -237,10 +237,15 @@ static void adjust_events_range(struct pmu_event *gp_= events, * occur while running the measured code, e.g. if the host takes IRQs. */ if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) { - gp_events[instruction_idx].min =3D LOOP_INSNS; - gp_events[instruction_idx].max =3D LOOP_INSNS; - gp_events[branch_idx].min =3D LOOP_BRANCHES; - gp_events[branch_idx].max =3D LOOP_BRANCHES; + if (!(intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT)) { + gp_events[instruction_idx].min =3D LOOP_INSNS; + gp_events[instruction_idx].max =3D LOOP_INSNS; + } + + if (!(intel_inst_overcount_flags & BR_RETIRED_OVERCOUNT)) { + gp_events[branch_idx].min =3D LOOP_BRANCHES; + gp_events[branch_idx].max =3D LOOP_BRANCHES; + } } =20 /* --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC50B2D9493; Wed, 3 Sep 2025 06:47:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882052; cv=none; b=NobOZIeow8lCuvkXvm0SBpicj1XoekzScABsz3glwkab8HCO3uHdRbUV/uRPM+c5X5j+/zrWdw468n/qJyTaYxjA/AQU7IxHXdRrgj7jXnMmptZEE9mdV+u76QeeRlpQBJft3GnHi/hUxAfn6lkstxcqU4pDESB3rHmkNOvq/rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882052; c=relaxed/simple; bh=xZaOT2faqwrZtdkqO+qLsZJ8quiYyhmYLU8cnJOdgsM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KtblZ3f54NrW6Jw6IKp3+ERz9lTJ4r78OhgXgZ/M1nR2HVjoAOKlKJ1ETKvGrPsMtshJmxFDh9BcbSWYEAZBMl9RcY35msRozMOTvkfDdnYpYIaOmei2E+aywPuFqgTKJPKBhIB2a0YGHsLM4wMU2rLNQRIk7cbqpp81FYtIr7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ACxWQse7; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ACxWQse7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882051; x=1788418051; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xZaOT2faqwrZtdkqO+qLsZJ8quiYyhmYLU8cnJOdgsM=; b=ACxWQse7dr2CrGqmj7YNUyf5Cz306OO53YrGH5dkf37gOf/DurMapfLn 7cJk+ejW1M/U51SmTeWng0/i+t5s8VoK5NlDPKx27YtXKKfkl3QDGXEjt 73FrbUc49ccOs49ezXqFD9a4FUBMP8REMnkctChXUHVm1iJjhWP8vrONm QBjryNgN0KHS63KHK6v1sewUmzwDV+bVS/NIr6Yx00w/G0m/eeu11NIpL jYC5ImDEMc84EjhqrbZ6EhNkqyJxgNa98Sx/Ff/o6jviQ1OxT1IWUUrfd q4DkuoQmjh8typXR5HHdY1w7S6ymdshFnYtAHbrNV+wWNAxxSpKmngRLS A==; X-CSE-ConnectionGUID: AnYtYTDWSoqQHT9KuLTsjQ== X-CSE-MsgGUID: YffnVTnqTPeA/sit+jtQWQ== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003787" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003787" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:30 -0700 X-CSE-ConnectionGUID: l9t6ZK0nQde/Yzlo7gkvoQ== X-CSE-MsgGUID: eWVUgLahS1GtyroimvSKaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656563" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:27 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi , Yi Lai Subject: [kvm-unit-tests patch v3 3/8] x86/pmu: Fix incorrect masking of fixed counters Date: Wed, 3 Sep 2025 14:45:56 +0800 Message-Id: <20250903064601.32131-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng The current implementation mistakenly limits the width of fixed counters to the width of GP counters. Corrects the logic to ensure fixed counters are properly masked according to their own width. Opportunistically refine the GP counter bitwidth processing code. Signed-off-by: dongsheng Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 04946d10..44c728a5 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -556,18 +556,16 @@ static void check_counter_overflow(void) int idx; =20 cnt.count =3D overflow_preset; - if (pmu_use_full_writes()) - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; - if (i =3D=3D pmu.nr_gp_counters) { if (!pmu.is_intel) break; =20 cnt.ctr =3D fixed_events[0].unit_sel; - cnt.count =3D measure_for_overflow(&cnt); - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; + cnt.count &=3D (1ull << pmu.fixed_counter_width) - 1; } else { cnt.ctr =3D MSR_GP_COUNTERx(i); + if (pmu_use_full_writes()) + cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; } =20 if (i % 2) --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1AE32DC335; Wed, 3 Sep 2025 06:47:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882056; cv=none; b=mWSRGdsbboB74EjXtc04dwkM8Zfx1iCH6cT0X3kl1QGtdVo0McBBrMf0I0TprMhI5kt9qIuzXmfrxfZiivBVbAQ5yDtJg8/jZUEdrqMJYWacHy+t62CotKiVCm6I9X5FnXB98YXWihlGvQBoAwDX5JEHxLlcRH/7x/OGLwpSXxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882056; c=relaxed/simple; bh=S7lk8W1qOqN6f2hlk12G1kiNj2WSIVk7J9ru7MHfT5M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=csWmIw99Bg25QHBEm7HS1mzjAhGGNqb4DwQYTCob+v+okPoBYkQ3yaSttr510fh7KrXakBfSjlyzV49qeGR1DFJRWoJVQvZRoG78uRo5ruQ+hCut3FtT8qBwD1+QPK/+z814ULPpZYHJSrwqiBkDhpkRBtIkqtesFzIL5DY4q9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Jehl0DtD; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Jehl0DtD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882055; x=1788418055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S7lk8W1qOqN6f2hlk12G1kiNj2WSIVk7J9ru7MHfT5M=; b=Jehl0DtDILmfGRZmG/BYj+kWqsIl8fafkJDvx4s0HZ6/CghYQ1s3wCg+ 3YQCY93FI7ruywijGu+B3qZ95VdkLo2ZmXgXilx3z6wmg8OpArwtPFF6V 1oI/I+XGqox/rZy0A3A8RXcVKI75rbajxG/Ff7z4FSLg9oS5x3BCEgez/ XqB5a2HnYpZ3CMnrbD4VhubpXXslk7KSDolOV+wd7/WhpnzFdi2nQeJEh 7HLfRjqTOM9aPv6A0PF842h3z4FhrldMi3YvAJeU8qpxQPZ7AoNAxjo5C 0piKbfyob5c11NY1ra59/rOeK/Z8lN7ehswp1p9HpWAzup/7YMS0byRBz Q==; X-CSE-ConnectionGUID: J28ZRZziR1e/GFd8NQVZwA== X-CSE-MsgGUID: 3Iz14ZRNS2eJ6YqNMMaEMg== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003795" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003795" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:34 -0700 X-CSE-ConnectionGUID: LpA9vQ6+TqS217Norf3d6w== X-CSE-MsgGUID: etATi+9KTgCK8HyQ7dDLrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656577" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:30 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi , Yi Lai Subject: [kvm-unit-tests patch v3 4/8] x86/pmu: Handle instruction overcount issue in overflow test Date: Wed, 3 Sep 2025 14:45:57 +0800 Message-Id: <20250903064601.32131-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng During the execution of __measure(), VM exits (e.g., due to WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the instruction overcount issue, each VM-Exit/VM-Entry can erroneously increment the instruction count by one, leading to false failures in overflow tests. To address this, the patch introduces a range-based validation in place of precise instruction count checks. Additionally, overflow_preset is now statically set to 1 - LOOP_INSNS, rather than being dynamically determined via measure_for_overflow(). These changes ensure consistent and predictable behavior aligned with the intended loop instruction count, while avoiding modifications to the subsequent status and status-clear testing logic. The chosen validation range is empirically derived to maintain test reliability across hardware variations. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 44c728a5..c54c0988 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -518,6 +518,21 @@ static void check_counters_many(void) =20 static uint64_t measure_for_overflow(pmu_counter_t *cnt) { + /* + * During the execution of __measure(), VM exits (e.g., due to + * WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the + * instruction overcount issue, each VM-Exit/VM-Entry can erroneously + * increment the instruction count by one, leading to false failures + * in overflow tests. + * + * To mitigate this, if the overcount issue is detected, we hardcode + * the overflow preset to (1 - LOOP_INSNS) instead of calculating it + * dynamically. This ensures that an overflow will reliably occur, + * regardless of any overcounting caused by VM exits. + */ + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + return 1 - LOOP_INSNS; + __measure(cnt, 0); /* * To generate overflow, i.e. roll over to '0', the initial count just @@ -574,8 +589,12 @@ static void check_counter_overflow(void) cnt.config &=3D ~EVNTSEL_INT; idx =3D event_to_global_idx(&cnt); __measure(&cnt, cnt.count); - if (pmu.is_intel) - report(cnt.count =3D=3D 1, "cntr-%d", i); + if (pmu.is_intel) { + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + report(cnt.count < 14, "cntr-%d", i); + else + report(cnt.count =3D=3D 1, "cntr-%d", i); + } else report(cnt.count =3D=3D 0xffffffffffff || cnt.count < 7, "cntr-%d", i); =20 --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 074B32DCBFD; Wed, 3 Sep 2025 06:47:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882059; cv=none; b=uFvirZ7FI4vayifqWn/H75nAvToGBJs2xUT9X1ZHBSH1Ck2ctkUgzx+XhgFoThoz9sGHL9+pyvSEa35pwNXtY/uPySGznxVfwz3GZPsgFDirzTFoVT8BtrstCwHDovGeUOZT1FcPiZRQGn2Gys3J5zS6X+G0lscsp1qIS9FtJGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882059; c=relaxed/simple; bh=1CVYfQYEkfyq8SaYox+DXBOLRWq3Y8uewK6cgv1Mi6A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J5Kek8ZLiNPtSimzG/Wiqm7RbLlRX5W89PipAflIXaBilBqdb939+97P0kpiLVSGSQeUsQyQCSkpgZtrBJk0aee5OZffSpIvIOLM0jPfndMQDRUFBInQBJJvy7oOKqoGF+TfSpzQ9Q00clGFSyNOeZj2K4qn6jPhsv8bihiV/1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=oF25FEcF; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="oF25FEcF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882058; x=1788418058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1CVYfQYEkfyq8SaYox+DXBOLRWq3Y8uewK6cgv1Mi6A=; b=oF25FEcF2hpNlm5a2mNsCdKndQeZbUBsMXl0nka1HvOJapa5Xn04z+F4 +FbEAeAMlLvNl3oSdU2SzdgoQPiMmTdPYZRcR3d0NkQ5q7tcPRx6Rvc5b gF73qWd/WargcxGE6UejSZoQJpd9ZhHXjvh+c2SfqzAuWZS8+AtxmbGV0 NnRcnnV1ojMbEwAGsu+KPYtZiY9CcwU9nGLOUpGCZNTJ8X+LOvTrROVSi WLNNnZ4Kl6uTuFaXEfL+FMXcrehjSNNw6TIN8+zuBivKlsEIpIxX9ly33 YuRpuZ0UVknGHQiLHdv2xTNKdmLVpR/fkJ8uVUWZibsfQQ/pYTLHmVaUl g==; X-CSE-ConnectionGUID: X5ty7pj9TqK043YieMwyhA== X-CSE-MsgGUID: jGRMybmDSK6ALYwhtHHvug== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003800" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003800" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:38 -0700 X-CSE-ConnectionGUID: LFbD5dAxQTKfVWz13P3aDg== X-CSE-MsgGUID: Zf/Ydu3WRlyRkqDTsJAukw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656591" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:35 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , Dapeng Mi Subject: [kvm-unit-tests patch v3 5/8] x86/pmu: Relax precise count check for emulated instructions tests Date: Wed, 3 Sep 2025 14:45:58 +0800 Message-Id: <20250903064601.32131-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Relax precise count check for emulated instructions tests on these platforms with HW overcount issues. Signed-off-by: Dapeng Mi --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index c54c0988..6bf6eee3 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -790,7 +790,7 @@ static void check_emulated_instr(void) =20 // Check that the end count - start count is at least the expected // number of instructions and branches. - if (this_cpu_has_perf_global_ctrl()) { + if (this_cpu_has_perf_global_ctrl() && !intel_inst_overcount_flags) { report(instr_cnt.count - instr_start =3D=3D KVM_FEP_INSNS, "instruction count"); report(brnch_cnt.count - brnch_start =3D=3D KVM_FEP_BRANCHES, --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6A1D2DE1E3; Wed, 3 Sep 2025 06:47:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882063; cv=none; b=KVht5eezNmJrQvSO15ll8LnjbEjs1Tit6zhTcaRB+rUuMzn7zy5nUcBfIIJLz1+2Bq0OCMsVZ8rrZ7D2WMdtZV91O2VhaB1wxtH3+vXQG+Jr2QIqvCgV117+2TuHpNS1QBrwEaFfFzVi9DZ028kZ25hi+RQMBBxTFNVXWseQnYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882063; c=relaxed/simple; bh=wHLvEGEjfsXeVsBn+aRGI7VBJk4E3CE8D19/SY1RQcM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OtVqDQE2s7DkbttJcUUPwXmQ03+aVYJ6jiRasYpW9eT5zRbOle+KiEE8X2rbUhODXGhc5azJfsS6yqUmsXIw9/xJqLXUWtySFem/CfuLay9OYdrXOF8WZDxZbkq2mbXSPan9AWDQSMqzW5DjHEeIMbiBkWbosoU3s3PGGm/AbBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fl7zXJaM; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fl7zXJaM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882062; x=1788418062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wHLvEGEjfsXeVsBn+aRGI7VBJk4E3CE8D19/SY1RQcM=; b=fl7zXJaMrYGWWbxOzGNUK824jafxQH3t8RYLAbniXbDR8iLGe6vddA3B OSpcXI1cXeiu32XcMzuwYUpNFJGbwBfiNOMnNTf8VJk44vK2q/HjXa+Bq nOX9RtAEQYTZTLM5P9OZPjJLX8FsTAmFD7/iOjuRhbsdEXr+NPXEK4mK0 ytvGP+UqQH5vHdpZB5JLC2fzG+RiOy79Tx3qIDzAcpiVti4m0XJtRa5Hf /FBAdTwJapGn2n0Ld1vdY5hfDK85zQVKenMoVUu9IiM2hCYSvVD7q2DTZ 9pbQB7rdCIb52ohfpNQXZgsAgH++k1N4HJOGQyryofbOKDxe8WQECKdUS A==; X-CSE-ConnectionGUID: GdSCfy53QduXhI3G45Gw7Q== X-CSE-MsgGUID: 3wyQmkNoSsSaeZ2WVDjGZA== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003806" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003806" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:41 -0700 X-CSE-ConnectionGUID: 7fkrRwcHRJqg9lkGn1+R1A== X-CSE-MsgGUID: JxeZYSXdRNeBPHUBxMjSug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656607" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:38 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , dongsheng , Dapeng Mi , Yi Lai Subject: [kvm-unit-tests patch v3 6/8] x86/pmu: Expand "llc references" upper limit for broader compatibility Date: Wed, 3 Sep 2025 14:45:59 +0800 Message-Id: <20250903064601.32131-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng Increase the upper limit of the "llc references" test to accommodate results observed on additional Intel CPU models, including CWF and SRF. These CPUs exhibited higher reference counts that previously caused the test to fail. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 6bf6eee3..49d25f68 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -116,7 +116,7 @@ struct pmu_event { {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"ref cycles", 0x013c, 1*N, 30*N}, - {"llc references", 0x4f2e, 1, 2*N}, + {"llc references", 0x4f2e, 1, 2.5*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 1, 0.1*N}, --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E4F2D94A4; Wed, 3 Sep 2025 06:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882067; cv=none; b=Uw69jKzU+xaXGsIywRVgd/wfm7SLSrcGYv6Oyo9BZH6QVoJThz3CSiNgQTNFDb7m2+8IAgHDCJWw/sjD+TK/UTGLMNkyCYlZhJHaVpcINtufPMZTcpSryeCI85Ec932xrxFYuBxTDV/A+rDChb5IRrBlRdaD46UIPgnmAz+U/yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882067; c=relaxed/simple; bh=IM6ZpntWH9mILQir1heZmjp9QGGWbJ+kZ3cIa25NE84=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ML83JkMZYb9kNjBBWME/ShUpVSDv3YFUj4gTDWszlhwjibV2aDOBBlrhgzuKYH44aFASD5vWRcy6zl8dSdaZpW32rCiZxBre6BdHtcL642/T+rOll72dc9PBTW+VOS4wSZoJ/vRPZtE7Kpb/+6vKs1aEU5UAGeBLNOXqh3LlYH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bSorm1IE; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bSorm1IE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882065; x=1788418065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IM6ZpntWH9mILQir1heZmjp9QGGWbJ+kZ3cIa25NE84=; b=bSorm1IEdP9XadG1ORgHJLUgtMzej2DRrW2bUfjbsv63IiYw4zzdJz0z Hqpux9zvj5Zo+2JNFCNV85+xf0/g82t2QyKxhKJLUAmHM+wv7yt8pFGz+ lGfi3fMdcV87mXU6jsm0OeBNUBT1xiWYv0LHaQUqtcYvlLeIGg6dK/yvz GY1ou6/lm8BtMJba2KvtvQQrqpotEPefXa2gSLnew+ROizXBJWt7yrPBU fPe4Yw8/foORN7KODgP6XpQ8JR+DfhanR/pMhQ5OSYql2AJGIUc96fgop Cu+OXN+jQcZPL7XgS6QK0i/VcknfQDN0Z/0wzN93503NMVhcWZ+bxLu8k Q==; X-CSE-ConnectionGUID: dlKMFmNcQ2yMeeYZ1wyVWg== X-CSE-MsgGUID: SWN+kreiQuysKP3VQ3wBCA== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003813" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003813" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:45 -0700 X-CSE-ConnectionGUID: 2k8TZlO2SLepA7aqjhDHlw== X-CSE-MsgGUID: zX8sWfvSTf2zDyq2q9Q/hQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656620" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:42 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , Dapeng Mi , Yi Lai Subject: [kvm-unit-tests patch v3 7/8] x86: pmu_pebs: Remove abundant data_cfg_match calculation Date: Wed, 3 Sep 2025 14:46:00 +0800 Message-Id: <20250903064601.32131-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove abundant data_cfg_match calculation. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu_pebs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 6e73fc34..2848cc1e 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -296,7 +296,6 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size =3D pebs_rec->format_size >> RECORD_SIZE_OFFSET; pebs_idx_match =3D pebs_rec->applicable_counters & bitmask; pebs_size_match =3D pebs_record_size =3D=3D get_pebs_record_size(pebs_da= ta_cfg, use_adaptive); - data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D p= ebs_data_cfg; data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D (use_adaptive ? pebs_data_cfg : 0); expected =3D pebs_idx_match && pebs_size_match && data_cfg_match; --=20 2.34.1 From nobody Fri Oct 3 08:49:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55F8D2DF149; Wed, 3 Sep 2025 06:47:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882070; cv=none; b=HFwaS5otX3F2kNju1hdOfN2T5uJrCi8a7pNBWOBxK4df3B3101WzeKkmFbwrIf+Ev23wMGuaZmbk4nx1QeOe8+Z8/JjyUgCOW5ZjiAp2N0MJq8UquP98eKeFcCHiz63ytdArdpOpdEoU2B4dH2EJijU8HsaG8K4g19U/zYv+InA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756882070; c=relaxed/simple; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PPe0LcwPRW6x9wb2GNJ3ghgJfioHlsTrp9YkI0YP0jKWqs8cItwRLChzqhErKkFpPuaPCh9ANdhfoyhDRPXnC4FT1IiJtYxIdV+3nzCOiozVZzo9Av5/nCVXZ/Z72ETp49Wu2pUsmqQQfEfoljHTnWHkY4E0WtO53uJaL9AxsLc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MwHI6Ri7; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MwHI6Ri7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756882069; x=1788418069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0hNsv9KESme0CC07v7qNNGShOQXUwWV1Ff+LbnZiLcI=; b=MwHI6Ri7Z/T2mmv1XU4a0tB7KL3DfOJkFDP6Maxv5k6PEE4sqdBjYh99 U2kvCCTmnk4zT0TpIVdGVcri7hxuUQBwT4Lw6Tvghxtqb8mTwJJ83FIRZ 9MKDCbgN8tcpvAjmj+4Lhwe9tRwgt+5fBJ7oVInoJpKabo4mf6EWAtIMN jC60VHV/9H7+rWQiY9gNHXQLtDLFmsShgdyFSrqiEF4B8n3/CBGMUt4E1 ntc0W6kn8GfOgs+DNv+Jaz6RRVeq0GLp8wXza/jo7SHaHyjG6Ftpvvdiw 8aHqlMjqAoqbe7NbLv5/uEa82fVHE6Bl8XEKRR3EwADnp8GOSWHJ6rzGM w==; X-CSE-ConnectionGUID: N5/kN1YyQfW3HpNQO+v5mQ== X-CSE-MsgGUID: 8eCz7QzJRIazeB7p+Sg6GA== X-IronPort-AV: E=McAfee;i="6800,10657,11541"; a="63003829" X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="63003829" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2025 23:47:49 -0700 X-CSE-ConnectionGUID: tM+BjTxgRDaGjDVLC5HbSA== X-CSE-MsgGUID: 46LiZpr/RYmUuHE5RbFCsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,233,1751266800"; d="scan'208";a="171656647" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa008.jf.intel.com with ESMTP; 02 Sep 2025 23:47:45 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Xiaoyao Li , Dapeng Mi , Dapeng Mi , Kan Liang , Yi Lai Subject: [kvm-unit-tests patch v3 8/8] x86: pmu_pebs: Support to validate timed PEBS record on GNR/SRF Date: Wed, 3 Sep 2025 14:46:01 +0800 Message-Id: <20250903064601.32131-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> References: <20250903064601.32131-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Intel GNR/SRF platform, timed PEBS is introduced. Timed PEBS adds a new "retired latency" field in basic info group to show the timing info. IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to indicate whether timed PEBS is supported. After introducing timed PEBS, the PEBS record format field shrinks to bits[31:0] and the bits[47:32] is used to record retired latency. Thus shrink the record format to bits[31:0] accordingly and avoid the retired latency field is recognized a part of record format to compare and cause failure on GNR/SRF. Please find detailed information about timed PEBS in section 8.4.1 "Timed Processor Event Based Sampling" of "Intel Architecture Instruction Set Extensions and Future Features". Reviewed-by: Kan Liang Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/pmu.h | 6 ++++++ x86/pmu_pebs.c | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h index c7dc68c1..86a7a05f 100644 --- a/lib/x86/pmu.h +++ b/lib/x86/pmu.h @@ -20,6 +20,7 @@ #define PMU_CAP_LBR_FMT 0x3f #define PMU_CAP_FW_WRITES (1ULL << 13) #define PMU_CAP_PEBS_BASELINE (1ULL << 14) +#define PMU_CAP_PEBS_TIMING_INFO (1ULL << 17) #define PERF_CAP_PEBS_FORMAT 0xf00 =20 #define EVNSEL_EVENT_SHIFT 0 @@ -188,4 +189,9 @@ static inline bool pmu_has_pebs_baseline(void) return pmu.perf_cap & PMU_CAP_PEBS_BASELINE; } =20 +static inline bool pmu_has_pebs_timing_info(void) +{ + return pmu.perf_cap & PMU_CAP_PEBS_TIMING_INFO; +} + #endif /* _X86_PMU_H_ */ diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 2848cc1e..bc37e8e3 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -277,6 +277,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive unsigned int count =3D 0; bool expected, pebs_idx_match, pebs_size_match, data_cfg_match; void *cur_record; + u64 format_mask; =20 expected =3D (ds->pebs_index =3D=3D ds->pebs_buffer_base) && !pebs_rec->f= ormat_size; if (!(rdmsr(MSR_CORE_PERF_GLOBAL_STATUS) & GLOBAL_STATUS_BUFFER_OVF)) { @@ -289,6 +290,8 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive return; } =20 + /* Record format shrinks to bits[31:0] after timed PEBS is introduced. */ + format_mask =3D pmu_has_pebs_timing_info() ? GENMASK_ULL(31, 0) : GENMASK= _ULL(47, 0); expected =3D ds->pebs_index >=3D ds->pebs_interrupt_threshold; cur_record =3D (void *)pebs_buffer; do { @@ -296,8 +299,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size =3D pebs_rec->format_size >> RECORD_SIZE_OFFSET; pebs_idx_match =3D pebs_rec->applicable_counters & bitmask; pebs_size_match =3D pebs_record_size =3D=3D get_pebs_record_size(pebs_da= ta_cfg, use_adaptive); - data_cfg_match =3D (pebs_rec->format_size & GENMASK_ULL(47, 0)) =3D=3D - (use_adaptive ? pebs_data_cfg : 0); + data_cfg_match =3D (pebs_rec->format_size & format_mask) =3D=3D (use_ada= ptive ? pebs_data_cfg : 0); expected =3D pebs_idx_match && pebs_size_match && data_cfg_match; report(expected, "PEBS record (written seq %d) is verified (including size, counte= rs and cfg).", count); @@ -327,7 +329,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_da= ta_cfg, bool use_adaptive pebs_record_size, get_pebs_record_size(pebs_data_cfg, use_adapti= ve)); if (!data_cfg_match) printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with the effectiv= e MSR_PEBS_DATA_CFG (0x%lx).\n", - pebs_rec->format_size & 0xffffffffffff, use_adaptive ? pebs_data= _cfg : 0); + pebs_rec->format_size & format_mask, use_adaptive ? pebs_data_cf= g : 0); } } =20 --=20 2.34.1