From nobody Fri Oct 3 10:15:01 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19121C8611; Wed, 3 Sep 2025 06:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756880734; cv=none; b=If35j0vYsBvl/utsWsnK1MLxj7zmASlR74w3fiQIFy/lGPnuwoefVbrR8Zr6BPU64jMcHSbBJtNcn9b7fbn60uy047ZRaaNgsQol+n/6FbULw3bA5eswymdTDPQSNB3SUaXmPwa9rRb50acerjyGt+M47O9Wv3hYYbL/5pR+34c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756880734; c=relaxed/simple; bh=dv1D0+8u7XvNsA1GCnn3RcGqe49QNmvyNC7OO8voAUo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VDLw+wjQjBgR9N0M7YUH6RJSEA6h4fcbeJDBnh1ML91tFSSefOODJw9UKzS1hyyv4riFO4EksfXR74M7rF/cIE+qZNBOkRBURmU9eVtnLx8kcSXMz05o9PrtbhJEi2bRLpPjsHajorZdG+BArGodStqOo5ZJckaxj/+/gtwLpbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wHm5jQxN; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wHm5jQxN" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5836PLUA3161908; Wed, 3 Sep 2025 01:25:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756880721; bh=LmY9DUK5RkcdEZJ8Yi/upFZ9xXuOGPE9LZUfMrKallU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wHm5jQxNq8oOokqf2CPxE9OH4grQ4dLNGaDz1fjezfUo68QgBBOA+ETvo/kgVYowg IhHRHyZXdfeqqR+oni9cBYxzA3Iq5O0IsJf4lp3CmETnAj/vJxELLyxxx+FXExYN+Y Lp7C+M7ryd3u/dTLJJsNCFEscuiteU2JPXHFTBQ8= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5836PLNN3315610 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 3 Sep 2025 01:25:21 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 3 Sep 2025 01:25:20 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 3 Sep 2025 01:25:20 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5836PJwc1116011; Wed, 3 Sep 2025 01:25:20 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , Subject: [PATCH v3 1/2] arm64: dts: ti: k3-am62a-main: Fix main padcfg length Date: Wed, 3 Sep 2025 11:55:12 +0530 Message-ID: <20250903062513.813925-2-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903062513.813925-1-p-bhagat@ti.com> References: <20250903062513.813925-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vibhore Vardhan The main pad configuration register region starts with the register MAIN_PADCFG_CTRL_MMR_CFG0_PADCONFIG0 with address 0x000f4000 and ends with the MAIN_PADCFG_CTRL_MMR_CFG0_PADCONFIG150 register with address 0x000f4258, as a result of which, total size of the region is 0x25c instead of 0x2ac. Reference Docs TRM (AM62A) - https://www.ti.com/lit/ug/spruj16b/spruj16b.pdf TRM (AM62D) - https://www.ti.com/lit/ug/sprujd4/sprujd4.pdf Fixes: 5fc6b1b62639c ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Cc: Signed-off-by: Vibhore Vardhan Signed-off-by: Paresh Bhagat Reviewed-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 9cad79d7bbc1..260279702c01 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -267,7 +267,7 @@ secure_proxy_sa3: mailbox@43600000 { =20 main_pmx0: pinctrl@f4000 { compatible =3D "pinctrl-single"; - reg =3D <0x00 0xf4000 0x00 0x2ac>; + reg =3D <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells =3D <1>; pinctrl-single,register-width =3D <32>; pinctrl-single,function-mask =3D <0xffffffff>; --=20 2.34.1