From nobody Fri Oct 3 10:13:16 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2078.outbound.protection.outlook.com [40.107.92.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B6862D7DEF; Wed, 3 Sep 2025 06:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.78 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756880277; cv=fail; b=f8aSlCHoJS9ZugZVS6e2IpFbmrJgc/5NzP2RMxVMVp7Nv5wSsa3lwzvsMjZkm0+hdn1D/SHCnvsJdprl/jkrFgSjELakTeXmG5Lwf4+e7l+s9Q7FweQhDFufV4if7aeTD2rWZizpdO0F1RFsVz39a7OSKEatZ9AGn3c5mdjHkTg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756880277; c=relaxed/simple; bh=obVB456u+6WEUFqDjkIao8MqnxweC7AbD8f6TXEpOYI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B1J6cY+olw8ilbi38v7/8n1OlBpDaaBlx+Lu2wNzdKdLOMaCmGWo16i+81mt1awbahdcINTs76QHaTV7rgJnsyXunheUbyQ5hZwFVxXK1cZ62YiqBqP3bkQewxF/Rj3BeAmfuz7bFesMGHgucUsEOS/6pKoYqElO/ATgMSdgdV0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=GvH/vgl9; arc=fail smtp.client-ip=40.107.92.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="GvH/vgl9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZMtmApbMXStJ2Rd/hjRnyqnXOHFkwNtJC56eUY3p3iwA0/F/KhACNFXspmonVdXK2lVQ5sfmN0y9CfH0N0mzNSSj7mIeYko4oqwRGtZjIe6De7MO7xgTB4XwPFaxC9exPXkizL8RRGNFz1BjDGK9LGVovhj5sr7ro6P7LMCawQz9jhW9wqR2VE5GlBkKGACuzLuyFfOXZhvIaHX2dThM0DFWGlp2PiaAKDSN6N+o9N1rBTrzoaseSNwbNICjKRhnBt8CBD89OIBGVR6kHRtj6ewzzE+FILlba9/u2eN8TSXxSYDPKuRCS8ZLPSvaGh+9LdGIvDIdVy5Enq7gCrH4gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GZDPuJxY1c+2P1yI2WRvV8oHsKIktCmeOabCeNkRGxo=; b=V4DToOXtSG2imQa3nk0c2Yd6sZCSahSv18MVj3Y2BRP426CqF9tDWM/y22EIwcFstQwEhVEO+MwyVm8ifVc8BeB3AWjDHs/1hJ7LV5OpT1zeDLwqStokA+Q8rO5vKVOi1ZvV+RUxuB6c7S9w2qpRP8myK0OJ00x2P6yLwXXHMZXk04HuVfwitymUdF0cC85wDLWTUff/cVeNpvV82azU1lLfIOyc7nYyZzpW8AYk3grqeHraUd0ej+0XWny8z4DpWn/1pvrwT91Z5+yrso8Gnl86T26HRTv2FbNdgg1UviHmvmGoGJzElij6I2+kUiZZf3xGRPyWZugWIjXdUKRPzg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=davemloft.net smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GZDPuJxY1c+2P1yI2WRvV8oHsKIktCmeOabCeNkRGxo=; b=GvH/vgl9Oz5uAYwyuk0nCLfcFnwA/AtdRHivytN863q9l+l7/NwMR5ip+TNQrsnzklpCaA29VYjRar6Z59iO/FgiYwgQLoI16AVYYeBXCttLurIvTBA0c7EiU2Al+D7cNKpqSE+r0Zh2zvdNnoykoteXGC/+N0PVTIS5HHGNrmU= Received: from MN0PR05CA0015.namprd05.prod.outlook.com (2603:10b6:208:52c::28) by DM6PR12MB4330.namprd12.prod.outlook.com (2603:10b6:5:21d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9073.27; Wed, 3 Sep 2025 06:17:49 +0000 Received: from BL6PEPF0001AB75.namprd02.prod.outlook.com (2603:10b6:208:52c:cafe::27) by MN0PR05CA0015.outlook.office365.com (2603:10b6:208:52c::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9094.16 via Frontend Transport; Wed, 3 Sep 2025 06:17:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL6PEPF0001AB75.mail.protection.outlook.com (10.167.242.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9094.14 via Frontend Transport; Wed, 3 Sep 2025 06:17:49 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 3 Sep 2025 01:17:45 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.1748.10; Tue, 2 Sep 2025 23:17:45 -0700 Received: from xhdabhijitg41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 3 Sep 2025 01:17:40 -0500 From: Abhijit Gangurde To: , , , , , , , , CC: , , , , , , , Abhijit Gangurde , Shannon Nelson , =?UTF-8?q?Pablo=20Casc=C3=B3n?= Subject: [PATCH v6 06/14] net: ionic: Provide doorbell and CMB region information Date: Wed, 3 Sep 2025 11:45:58 +0530 Message-ID: <20250903061606.4139957-7-abhijit.gangurde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250903061606.4139957-1-abhijit.gangurde@amd.com> References: <20250903061606.4139957-1-abhijit.gangurde@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|DM6PR12MB4330:EE_ X-MS-Office365-Filtering-Correlation-Id: f7aab8f4-664d-4c2c-bf4a-08ddeab19b71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ZzBCcnhvOG9DNzY2UjJDTzFLelc5Q3g0bjFyclpaQUYybFZXOTFEVHJQdEtF?= =?utf-8?B?VjJYMGQzaSthWjlBOEo3Yzd1NGlsOGtQb2kvU2w1dkd5Tzk2VEVSUGN6OGxC?= =?utf-8?B?RGl5OEhRZEtUWUt0OXZzelFtL01RbW5PMW0vaUc4YVBBNGRBc0hadzJnek9U?= =?utf-8?B?cVpyK1hpK2l3cW9rQllTemFxbi9QNjhGWmloemEvOUpvK1oxVFhQNllxYkta?= =?utf-8?B?YzlPNnNqcDA3VlZPQjU5ZG4yN0h3MVdSbVpwTlhzbXlIdTNWaUg2N0pvTEk5?= =?utf-8?B?dm9UOXMxejl5MEtvZlg4RHlrTU9mL29XTWtta3RjVWJ5WkplNUlYajJxSUZR?= =?utf-8?B?cFByQy8vK3pOaE1kZElHaDRYZEFDcnZib3YyRWVNK0lMb3IvUHF4VWxpY1VX?= =?utf-8?B?QVlYN0xiT0E1VG5CZUdDNGNzWGtWOGRWN2RuMzJVVnlPM2xpV05MS2F5K2I4?= =?utf-8?B?djN4OGdpMHQwb0w0RFNnTnkxWXdtSXNEVlEzSGtZUS9wamQ5eVdqbnA1MVNo?= =?utf-8?B?UVBtaUdJM2RTZGF0UFQ1OE5Kdmx4UXNsZDdQS2JxUnBMdEQ0Qmk0dUtVTFFO?= =?utf-8?B?SXI4YVdUalJrdmZpVk5LT21BclgvRjk2eUdVbmNsYzJDYlU0Yk51Z0RiSVhF?= =?utf-8?B?c21RTWxQaGw5cnZndkFCeDYvTEhQdW5UZS93ME9wTGtOYldoc1QyR2xCVW1m?= =?utf-8?B?dnA3NTJaOTRaWjJkYVVwTzNFb1NicjZnY294V0xZVCtzNzFFRFBGQWdBYVYz?= =?utf-8?B?TjZEaHFrQlJuVEFCamhQck5idERwdWFYSU9jWVJTUmtuNUV6Y1E0RzFmMEhQ?= =?utf-8?B?dHphVFFTdTRqbnBmK0pFWXVnUVhIZktCbWMvUit2RU1wdkVLMG5xdDNDOVpE?= =?utf-8?B?Q2RLL01ZV3dYOVk5NVMrVWxpQ2pDN1BoaG44Q1dlN25yNHZ4cFJZdVNQd3A5?= =?utf-8?B?TkNiZXNWcUt5QVIrQUVockR4SHkzUE01WTVIVG1kMmJiMlpBcEY3UE5CR205?= =?utf-8?B?WWF1aU0vS1JwYkdzcndxSFBvNUovUndtL05LZzFacVBEZjdERGJ1WEpZL3pF?= =?utf-8?B?TkJoL25yQUcxeE1EcU5DNXEzQ1M1eHRtd0Z1SmlCNXY0K2t5UUpJTnF6Vkc1?= =?utf-8?B?OG9QUENKeTJjRVp4bDhmZ1kxSGFINE9lb0I2V1ZtSjhaMzRaa2R1UkJlTzg4?= =?utf-8?B?M0l1VTh3VzJvRGtqQktLOXFiTld3MkZDdjBIVzBmWVByVWVmazBjaHkzTC9X?= =?utf-8?B?Y0tKRG9ESGhHaktFSloycThGNnFUMzJzb1dHeWs1b3Brc1BhUno4N0hqYmlO?= =?utf-8?B?YkhLMG1nWXZqU29UdDM4Zmk4THJXTHZCYnVGMTZ2MnhRVkdHbzFhQ2xKYlVn?= =?utf-8?B?NWtJcjNrRUE3dnZoeERsNU85R3ZZUW1ZZDFRcEkxVUhOYTlmMWJWVGhRbVRw?= =?utf-8?B?d21UUnM4L0dmcjNVYStZRDJUUHFWTjV0Z25pcEYxM0NOaGd4NmdDcUt4NTF5?= =?utf-8?B?dytyL0ZBc0FoRkgvajR0ZEpIM2tOSXNNbkZDR25VK0hnckVrdzhydnN5N25N?= =?utf-8?B?NGk0LzZLTG9QN2Q3K2xiM3ZZVnJ5aWRZdXY5akQrUE5VMm1nZXRYVUd0UW5W?= =?utf-8?B?RWtFUGVubVFZTklIQ1l6b1hIby8yeVRoS09JalZrM1JBcE9USWJhbSsydTNV?= =?utf-8?B?bUJSd0c4bkpQKzVUeGRIaFVBVGhML2RIM0RKcFd5N0NkeXE2VkswMDRJVW9K?= =?utf-8?B?Lzd6QVhqR2JjZEJUcDVUYkRoMUhERXVnMHhDaCtMQ2FIcWhHWXJFVlJqYmk2?= =?utf-8?B?cStHd2l3Qjl3eW9lK1FzWXlnV1dxQzVJWWdWV20xMk9UbGU4UkI4eGtnNVht?= =?utf-8?B?cTc2dmF1N3NMYXhSbmE0MUJEQitUOFlpd1lJUk1ncUdnZzg4QnAxVnFHeU9U?= =?utf-8?B?UWttRkJLVnkvWm5yODlvVEJuVmEyZjI2Qm1XV25oazRoaFczQjNBcWtEMU0x?= =?utf-8?B?MDRDOFliNk91RWpBUUg4WmRLbkVQc1pXelBNaHVpRTQwRGJIcTE0ME4xRHRS?= =?utf-8?Q?ZYZ4dS?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2025 06:17:49.4073 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7aab8f4-664d-4c2c-bf4a-08ddeab19b71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4330 The RDMA device needs information of controller memory bar and doorbell capability to share with user context. Discover CMB regions and express doorbell capabilities on device init. Reviewed-by: Shannon Nelson Co-developed-by: Pablo Casc=C3=B3n Signed-off-by: Pablo Casc=C3=B3n Co-developed-by: Allen Hubbe Signed-off-by: Allen Hubbe Signed-off-by: Abhijit Gangurde --- .../net/ethernet/pensando/ionic/ionic_api.h | 22 ++ .../ethernet/pensando/ionic/ionic_bus_pci.c | 2 + .../net/ethernet/pensando/ionic/ionic_dev.c | 270 +++++++++++++++++- .../net/ethernet/pensando/ionic/ionic_dev.h | 14 +- .../net/ethernet/pensando/ionic/ionic_if.h | 89 ++++++ .../net/ethernet/pensando/ionic/ionic_lif.c | 2 +- 6 files changed, 381 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/pensando/ionic/ionic_api.h b/drivers/net/= ethernet/pensando/ionic/ionic_api.h index 5fd23aa8c5a1..bd88666836b8 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_api.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_api.h @@ -106,4 +106,26 @@ int ionic_intr_alloc(struct ionic_lif *lif, struct ion= ic_intr_info *intr); */ void ionic_intr_free(struct ionic_lif *lif, int intr); =20 +/** + * ionic_get_cmb - Reserve cmb pages + * @lif: Logical interface + * @pgid: First page index + * @pgaddr: First page bus addr (contiguous) + * @order: Log base two number of pages (PAGE_SIZE) + * @stride_log2: Size of stride to determine CMB pool + * @expdb: Will be set to true if this CMB region has expdb enabled + * + * Return: zero or negative error status + */ +int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, + int order, u8 stride_log2, bool *expdb); + +/** + * ionic_put_cmb - Release cmb pages + * @lif: Logical interface + * @pgid: First page index + * @order: Log base two number of pages (PAGE_SIZE) + */ +void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); + #endif /* _IONIC_API_H_ */ diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/= net/ethernet/pensando/ionic/ionic_bus_pci.c index f8752b1d2790..70d86c5f52fb 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c @@ -272,6 +272,8 @@ static int ionic_setup_one(struct ionic *ionic) } ionic_debugfs_add_ident(ionic); =20 + ionic_map_cmb(ionic); + err =3D ionic_init(ionic); if (err) { dev_err(dev, "Cannot init device: %d, aborting\n", err); diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/= ethernet/pensando/ionic/ionic_dev.c index 093c5358b6e8..ab27e9225c1e 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c @@ -199,13 +199,201 @@ void ionic_init_devinfo(struct ionic *ionic) dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); } =20 +static void ionic_map_disc_cmb(struct ionic *ionic) +{ + struct ionic_identity *ident =3D &ionic->ident; + u32 length_reg0, length, offset, num_regions; + struct ionic_dev_bar *bar =3D ionic->bars; + struct ionic_dev *idev =3D &ionic->idev; + struct device *dev =3D ionic->dev; + int err, sz, i; + u64 end; + + mutex_lock(&ionic->dev_cmd_lock); + + ionic_dev_cmd_discover_cmb(idev); + err =3D ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); + if (!err) { + sz =3D min(sizeof(ident->cmb_layout), + sizeof(idev->dev_cmd_regs->data)); + memcpy_fromio(&ident->cmb_layout, + &idev->dev_cmd_regs->data, sz); + } + mutex_unlock(&ionic->dev_cmd_lock); + + if (err) { + dev_warn(dev, "Cannot discover CMB layout, disabling CMB\n"); + return; + } + + bar +=3D 2; + + num_regions =3D le32_to_cpu(ident->cmb_layout.num_regions); + if (!num_regions || num_regions > IONIC_MAX_CMB_REGIONS) { + dev_warn(dev, "Invalid number of CMB entries (%d)\n", + num_regions); + return; + } + + dev_dbg(dev, "ionic_cmb_layout_identity num_regions %d flags %x:\n", + num_regions, ident->cmb_layout.flags); + + for (i =3D 0; i < num_regions; i++) { + offset =3D le32_to_cpu(ident->cmb_layout.region[i].offset); + length =3D le32_to_cpu(ident->cmb_layout.region[i].length); + end =3D offset + length; + + dev_dbg(dev, "CMB entry %d: bar_num %u cmb_type %u offset %x length %u\n= ", + i, ident->cmb_layout.region[i].bar_num, + ident->cmb_layout.region[i].cmb_type, + offset, length); + + if (end > (bar->len >> IONIC_CMB_SHIFT_64K)) { + dev_warn(dev, "Out of bounds CMB region %d offset %x length %u\n", + i, offset, length); + return; + } + } + + /* if first entry matches PCI config, expdb is not supported */ + if (ident->cmb_layout.region[0].bar_num =3D=3D bar->res_index && + le32_to_cpu(ident->cmb_layout.region[0].length) =3D=3D bar->len && + !ident->cmb_layout.region[0].offset) { + dev_warn(dev, "No CMB mapping discovered\n"); + return; + } + + /* process first entry for regular mapping */ + length_reg0 =3D le32_to_cpu(ident->cmb_layout.region[0].length); + if (!length_reg0) { + dev_warn(dev, "region len =3D 0. No CMB mapping discovered\n"); + return; + } + + /* Verify first entry size matches expected 8MB size (in 64KB pages) */ + if (length_reg0 !=3D IONIC_BAR2_CMB_ENTRY_SIZE >> IONIC_CMB_SHIFT_64K) { + dev_warn(dev, "Unexpected CMB size in entry 0: %u pages\n", + length_reg0); + return; + } + + sz =3D BITS_TO_LONGS((length_reg0 << IONIC_CMB_SHIFT_64K) / + PAGE_SIZE) * sizeof(long); + idev->cmb_inuse =3D kzalloc(sz, GFP_KERNEL); + if (!idev->cmb_inuse) { + dev_warn(dev, "No memory for CMB, disabling\n"); + idev->phy_cmb_pages =3D 0; + idev->phy_cmb_expdb64_pages =3D 0; + idev->phy_cmb_expdb128_pages =3D 0; + idev->phy_cmb_expdb256_pages =3D 0; + idev->phy_cmb_expdb512_pages =3D 0; + idev->cmb_npages =3D 0; + return; + } + + for (i =3D 0; i < num_regions; i++) { + /* check this region matches first region length as to + * ease implementation + */ + if (le32_to_cpu(ident->cmb_layout.region[i].length) !=3D + length_reg0) + continue; + + offset =3D le32_to_cpu(ident->cmb_layout.region[i].offset); + + switch (ident->cmb_layout.region[i].cmb_type) { + case IONIC_CMB_TYPE_DEVMEM: + idev->phy_cmb_pages =3D bar->bus_addr + offset; + idev->cmb_npages =3D + (length_reg0 << IONIC_CMB_SHIFT_64K) / PAGE_SIZE; + dev_dbg(dev, "regular cmb mapping: bar->bus_addr %pa region[%d].length = %u\n", + &bar->bus_addr, i, length); + dev_dbg(dev, "idev->phy_cmb_pages %pad, idev->cmb_npages %u\n", + &idev->phy_cmb_pages, idev->cmb_npages); + break; + + case IONIC_CMB_TYPE_EXPDB64: + idev->phy_cmb_expdb64_pages =3D + bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K); + dev_dbg(dev, "idev->phy_cmb_expdb64_pages %pad\n", + &idev->phy_cmb_expdb64_pages); + break; + + case IONIC_CMB_TYPE_EXPDB128: + idev->phy_cmb_expdb128_pages =3D + bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K); + dev_dbg(dev, "idev->phy_cmb_expdb128_pages %pad\n", + &idev->phy_cmb_expdb128_pages); + break; + + case IONIC_CMB_TYPE_EXPDB256: + idev->phy_cmb_expdb256_pages =3D + bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K); + dev_dbg(dev, "idev->phy_cmb_expdb256_pages %pad\n", + &idev->phy_cmb_expdb256_pages); + break; + + case IONIC_CMB_TYPE_EXPDB512: + idev->phy_cmb_expdb512_pages =3D + bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K); + dev_dbg(dev, "idev->phy_cmb_expdb512_pages %pad\n", + &idev->phy_cmb_expdb512_pages); + break; + + default: + dev_warn(dev, "[%d] Invalid cmb_type (%d)\n", + i, ident->cmb_layout.region[i].cmb_type); + break; + } + } +} + +static void ionic_map_classic_cmb(struct ionic *ionic) +{ + struct ionic_dev_bar *bar =3D ionic->bars; + struct ionic_dev *idev =3D &ionic->idev; + struct device *dev =3D ionic->dev; + int sz; + + bar +=3D 2; + /* classic CMB mapping */ + idev->phy_cmb_pages =3D bar->bus_addr; + idev->cmb_npages =3D bar->len / PAGE_SIZE; + dev_dbg(dev, "classic cmb mapping: bar->bus_addr %pa bar->len %lu\n", + &bar->bus_addr, bar->len); + dev_dbg(dev, "idev->phy_cmb_pages %pad, idev->cmb_npages %u\n", + &idev->phy_cmb_pages, idev->cmb_npages); + + sz =3D BITS_TO_LONGS(idev->cmb_npages) * sizeof(long); + idev->cmb_inuse =3D kzalloc(sz, GFP_KERNEL); + if (!idev->cmb_inuse) { + idev->phy_cmb_pages =3D 0; + idev->cmb_npages =3D 0; + } +} + +void ionic_map_cmb(struct ionic *ionic) +{ + struct pci_dev *pdev =3D ionic->pdev; + struct device *dev =3D ionic->dev; + + if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM)) { + dev_dbg(dev, "No CMB, disabling\n"); + return; + } + + if (ionic->ident.dev.capabilities & cpu_to_le64(IONIC_DEV_CAP_DISC_CMB)) + ionic_map_disc_cmb(ionic); + else + ionic_map_classic_cmb(ionic); +} + int ionic_dev_setup(struct ionic *ionic) { struct ionic_dev_bar *bar =3D ionic->bars; unsigned int num_bars =3D ionic->num_bars; struct ionic_dev *idev =3D &ionic->idev; struct device *dev =3D ionic->dev; - int size; u32 sig; int err; =20 @@ -255,16 +443,11 @@ int ionic_dev_setup(struct ionic *ionic) mutex_init(&idev->cmb_inuse_lock); if (num_bars < 3 || !ionic->bars[IONIC_PCI_BAR_CMB].len) { idev->cmb_inuse =3D NULL; + idev->phy_cmb_pages =3D 0; + idev->cmb_npages =3D 0; return 0; } =20 - idev->phy_cmb_pages =3D bar->bus_addr; - idev->cmb_npages =3D bar->len / PAGE_SIZE; - size =3D BITS_TO_LONGS(idev->cmb_npages) * sizeof(long); - idev->cmb_inuse =3D kzalloc(size, GFP_KERNEL); - if (!idev->cmb_inuse) - dev_warn(dev, "No memory for CMB, disabling\n"); - return 0; } =20 @@ -277,6 +460,11 @@ void ionic_dev_teardown(struct ionic *ionic) idev->phy_cmb_pages =3D 0; idev->cmb_npages =3D 0; =20 + idev->phy_cmb_expdb64_pages =3D 0; + idev->phy_cmb_expdb128_pages =3D 0; + idev->phy_cmb_expdb256_pages =3D 0; + idev->phy_cmb_expdb512_pages =3D 0; + if (ionic->wq) { destroy_workqueue(ionic->wq); ionic->wq =3D NULL; @@ -698,28 +886,79 @@ void ionic_dev_cmd_adminq_init(struct ionic_dev *idev= , struct ionic_qcq *qcq, ionic_dev_cmd_go(idev, &cmd); } =20 +void ionic_dev_cmd_discover_cmb(struct ionic_dev *idev) +{ + union ionic_dev_cmd cmd =3D { + .discover_cmb.opcode =3D IONIC_CMD_DISCOVER_CMB, + }; + + ionic_dev_cmd_go(idev, &cmd); +} + int ionic_db_page_num(struct ionic_lif *lif, int pid) { return (lif->hw_index * lif->dbid_count) + pid; } =20 -int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, i= nt order) +int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, + int order, u8 stride_log2, bool *expdb) { struct ionic_dev *idev =3D &lif->ionic->idev; - int ret; + void __iomem *nonexpdb_pgptr; + phys_addr_t nonexpdb_pgaddr; + int i, idx; =20 mutex_lock(&idev->cmb_inuse_lock); - ret =3D bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order); + idx =3D bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order); mutex_unlock(&idev->cmb_inuse_lock); =20 - if (ret < 0) - return ret; + if (idx < 0) + return idx; + + *pgid =3D (u32)idx; + + if (idev->phy_cmb_expdb64_pages && + stride_log2 =3D=3D IONIC_EXPDB_64B_WQE_LG2) { + *pgaddr =3D idev->phy_cmb_expdb64_pages + idx * PAGE_SIZE; + if (expdb) + *expdb =3D true; + } else if (idev->phy_cmb_expdb128_pages && + stride_log2 =3D=3D IONIC_EXPDB_128B_WQE_LG2) { + *pgaddr =3D idev->phy_cmb_expdb128_pages + idx * PAGE_SIZE; + if (expdb) + *expdb =3D true; + } else if (idev->phy_cmb_expdb256_pages && + stride_log2 =3D=3D IONIC_EXPDB_256B_WQE_LG2) { + *pgaddr =3D idev->phy_cmb_expdb256_pages + idx * PAGE_SIZE; + if (expdb) + *expdb =3D true; + } else if (idev->phy_cmb_expdb512_pages && + stride_log2 =3D=3D IONIC_EXPDB_512B_WQE_LG2) { + *pgaddr =3D idev->phy_cmb_expdb512_pages + idx * PAGE_SIZE; + if (expdb) + *expdb =3D true; + } else { + *pgaddr =3D idev->phy_cmb_pages + idx * PAGE_SIZE; + if (expdb) + *expdb =3D false; + } =20 - *pgid =3D ret; - *pgaddr =3D idev->phy_cmb_pages + ret * PAGE_SIZE; + /* clear the requested CMB region, 1 PAGE_SIZE ioremap at a time */ + nonexpdb_pgaddr =3D idev->phy_cmb_pages + idx * PAGE_SIZE; + for (i =3D 0; i < (1 << order); i++) { + nonexpdb_pgptr =3D + ioremap_wc(nonexpdb_pgaddr + i * PAGE_SIZE, PAGE_SIZE); + if (!nonexpdb_pgptr) { + ionic_put_cmb(lif, *pgid, order); + return -ENOMEM; + } + memset_io(nonexpdb_pgptr, 0, PAGE_SIZE); + iounmap(nonexpdb_pgptr); + } =20 return 0; } +EXPORT_SYMBOL_NS(ionic_get_cmb, "NET_IONIC"); =20 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order) { @@ -729,6 +968,7 @@ void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int= order) bitmap_release_region(idev->cmb_inuse, pgid, order); mutex_unlock(&idev->cmb_inuse_lock); } +EXPORT_SYMBOL_NS(ionic_put_cmb, "NET_IONIC"); =20 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, struct ionic_intr_info *intr, diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/= ethernet/pensando/ionic/ionic_dev.h index 68cf4da3c6b3..35566f97eaea 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h @@ -35,6 +35,11 @@ #define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ #define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 4) /* 4s */ =20 +#define IONIC_EXPDB_64B_WQE_LG2 6 +#define IONIC_EXPDB_128B_WQE_LG2 7 +#define IONIC_EXPDB_256B_WQE_LG2 8 +#define IONIC_EXPDB_512B_WQE_LG2 9 + struct ionic_dev_bar { void __iomem *vaddr; phys_addr_t bus_addr; @@ -171,6 +176,11 @@ struct ionic_dev { dma_addr_t phy_cmb_pages; u32 cmb_npages; =20 + dma_addr_t phy_cmb_expdb64_pages; + dma_addr_t phy_cmb_expdb128_pages; + dma_addr_t phy_cmb_expdb256_pages; + dma_addr_t phy_cmb_expdb512_pages; + u32 port_info_sz; struct ionic_port_info *port_info; dma_addr_t port_info_pa; @@ -351,8 +361,8 @@ void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, = struct ionic_qcq *qcq, =20 int ionic_db_page_num(struct ionic_lif *lif, int pid); =20 -int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, i= nt order); -void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); +void ionic_dev_cmd_discover_cmb(struct ionic_dev *idev); +void ionic_map_cmb(struct ionic *ionic); =20 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, struct ionic_intr_info *intr, diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/e= thernet/pensando/ionic/ionic_if.h index 77c3dc188264..47559c909c8b 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_if.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h @@ -56,6 +56,9 @@ enum ionic_cmd_opcode { IONIC_CMD_VF_SETATTR =3D 61, IONIC_CMD_VF_CTRL =3D 62, =20 + /* CMB command */ + IONIC_CMD_DISCOVER_CMB =3D 80, + /* QoS commands */ IONIC_CMD_QOS_CLASS_IDENTIFY =3D 240, IONIC_CMD_QOS_CLASS_INIT =3D 241, @@ -269,9 +272,11 @@ union ionic_drv_identity { /** * enum ionic_dev_capability - Device capabilities * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations + * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations */ enum ionic_dev_capability { IONIC_DEV_CAP_VF_CTRL =3D BIT(0), + IONIC_DEV_CAP_DISC_CMB =3D BIT(1), }; =20 /** @@ -395,6 +400,7 @@ enum ionic_logical_qtype { * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size + * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell */ enum ionic_q_feature { IONIC_QIDENT_F_CQ =3D BIT_ULL(0), @@ -407,6 +413,7 @@ enum ionic_q_feature { IONIC_Q_F_4X_DESC =3D BIT_ULL(7), IONIC_Q_F_4X_CQ_DESC =3D BIT_ULL(8), IONIC_Q_F_4X_SG_DESC =3D BIT_ULL(9), + IONIC_QIDENT_F_EXPDB =3D BIT_ULL(10), }; =20 /** @@ -2213,6 +2220,80 @@ struct ionic_vf_ctrl_comp { u8 rsvd[15]; }; =20 +/** + * struct ionic_discover_cmb_cmd - CMB discovery command + * @opcode: Opcode for the command + * @rsvd: Reserved bytes + */ +struct ionic_discover_cmb_cmd { + u8 opcode; + u8 rsvd[63]; +}; + +/** + * struct ionic_discover_cmb_comp - CMB discover command completion. + * @status: Status of the command (enum ionic_status_code) + * @rsvd: Reserved bytes + */ +struct ionic_discover_cmb_comp { + u8 status; + u8 rsvd[15]; +}; + +#define IONIC_MAX_CMB_REGIONS 16 +#define IONIC_CMB_SHIFT_64K 16 + +enum ionic_cmb_type { + IONIC_CMB_TYPE_DEVMEM =3D 0, + IONIC_CMB_TYPE_EXPDB64 =3D 1, + IONIC_CMB_TYPE_EXPDB128 =3D 2, + IONIC_CMB_TYPE_EXPDB256 =3D 3, + IONIC_CMB_TYPE_EXPDB512 =3D 4, +}; + +/** + * union ionic_cmb_region - Configuration for CMB region + * @bar_num: CMB mapping number from FW + * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type) + * @rsvd: Reserved + * @offset: Offset within BAR in 64KB pages + * @length: Length of the CMB region + * @words: 32-bit words for direct access to the entire region + */ +union ionic_cmb_region { + struct { + u8 bar_num; + u8 cmb_type; + u8 rsvd[6]; + __le32 offset; + __le32 length; + } __packed; + __le32 words[4]; +}; + +/** + * union ionic_discover_cmb_identity - CMB layout identity structure + * @num_regions: Number of CMB regions, up to 16 + * @flags: Feature and capability bits (0 for express + * doorbell, 1 for 4K alignment indicator, + * 31-24 for version information) + * @region: CMB mappings region, entry 0 for regular + * mapping, entries 1-7 for WQE sizes 64, + * 128, 256, 512, 1024, 2048 and 4096 bytes + * @words: Full union buffer size + */ +union ionic_discover_cmb_identity { + struct { + __le32 num_regions; +#define IONIC_CMB_FLAG_EXPDB BIT(0) +#define IONIC_CMB_FLAG_4KALIGN BIT(1) +#define IONIC_CMB_FLAG_VERSION 0xff000000 + __le32 flags; + union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS]; + }; + __le32 words[478]; +}; + /** * struct ionic_qos_identify_cmd - QoS identify command * @opcode: opcode @@ -3073,6 +3154,8 @@ union ionic_dev_cmd { struct ionic_vf_getattr_cmd vf_getattr; struct ionic_vf_ctrl_cmd vf_ctrl; =20 + struct ionic_discover_cmb_cmd discover_cmb; + struct ionic_lif_identify_cmd lif_identify; struct ionic_lif_init_cmd lif_init; struct ionic_lif_reset_cmd lif_reset; @@ -3112,6 +3195,8 @@ union ionic_dev_cmd_comp { struct ionic_vf_getattr_comp vf_getattr; struct ionic_vf_ctrl_comp vf_ctrl; =20 + struct ionic_discover_cmb_comp discover_cmb; + struct ionic_lif_identify_comp lif_identify; struct ionic_lif_init_comp lif_init; ionic_lif_reset_comp lif_reset; @@ -3253,6 +3338,9 @@ union ionic_adminq_comp { #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 + +/* BAR2 */ +#define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000 #define IONIC_DEV_CMD_DONE 0x00000001 =20 #define IONIC_ASIC_TYPE_NONE 0 @@ -3306,6 +3394,7 @@ struct ionic_identity { union ionic_port_identity port; union ionic_qos_identity qos; union ionic_q_identity txq; + union ionic_discover_cmb_identity cmb_layout; }; =20 #endif /* _IONIC_IF_H_ */ diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/= ethernet/pensando/ionic/ionic_lif.c index 276024002484..b28966ae50c2 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c @@ -673,7 +673,7 @@ static int ionic_qcq_alloc(struct ionic_lif *lif, unsig= ned int type, new->cmb_order =3D order_base_2(new->cmb_q_size / PAGE_SIZE); =20 err =3D ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa, - new->cmb_order); + new->cmb_order, 0, NULL); if (err) { netdev_err(lif->netdev, "Cannot allocate queue order %d from cmb: err %d\n", --=20 2.43.0