From nobody Fri Oct 3 08:49:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F3842D5410; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; cv=none; b=gfm0TD47eMQsX5wq8ssBnmQWuT8xZGAcdDsP8oGxYboaIji3Wk6/Jpw6MX/iQZyP34cpvOln3j/M7BC43CyGK+8WK5W9ENG+Tvm7GX98c3ncEDD8Ej77TH6082OZE3JhMcXHGDcYslDkb6fICg5Ip9je1UnMuic8F2CT3sgSp+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; c=relaxed/simple; bh=3Ho4dQOZpk+HfDT50JDRPnGFGqzr/4gvezzMHb1Uyn8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E3NXbg4Y3LMTMfkdfDBV1gQnWTCx4G9A8xT1vXRvK2n5L69UNRhd9g5YPULVQtvRMmFgc4XA6A7zY8Xa24SQlijcCaNldZuya353t8kpMsxzd60lRoqhqVB+vHhXeBToMs6+FWgEftUR2IOn9AZ5tbjo6P3lfL3OPbaI/rLNiWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NXm8pPW9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NXm8pPW9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 06260C4CEF4; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756927823; bh=3Ho4dQOZpk+HfDT50JDRPnGFGqzr/4gvezzMHb1Uyn8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NXm8pPW9AK2Kw0erK7SSLUxkp+sz18WP0XsB+mam3ia9+HF5FdTmpkF/0gU9eLUeu dmorJ68Dr6R+nPyagi0OeadDfqJvOEspip0Cz30cduGAE24Xp4wPj11cb+tDgIjUTt gEM+hVWyHFxJkehRuFsBrsy2h8mBB00gPXT9OQgDmyIakkblmcQnC08wEEqXED94UN qT9v+3bpriA7OTGR3wkE3AEKSdktvmzcK2nRJkquZ1R/Ecy5c13eGYDYi7fog+uVqi FYBvwSxk5PxC3BBnGIfMjdJ2xrrq4PeGbqqphoZU+DmQIXxauSjls+wCnVXsfrW7tJ hqqWjkK/1OLww== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED35ECA1014; Wed, 3 Sep 2025 19:30:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:30:17 -0500 Subject: [PATCH v2 2/4] soc: tegra: fuse: speedo-tegra210: Update speedo ids Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-tegra210-speedo-v2-2-89e6f86b8942@gmail.com> References: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756927822; l=2732; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=+rnEMK4ZcZWLWnEqy8xfvGYxMDKH6aqGlW/aWu1EMXw=; b=Rtw4En8Nol3b3Pqyu9BdJK0rwTTTt5os7DFLrd70wJVDMZn+cLzJ4pMTGtnLG2QIX3EIyXxZX OH5UL6xYH9NDsYsEC1n7Yz/o+OUdc3oGJttdKKm2NHAlahOQuhPPMbP X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs code supports 11 ids and nouveau supports 5. This aligns with what the downstream vendor kernel supports. Align skus with the downstream list. The Tegra210 CVB tables were added in the first referenced fixes commit. Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the supported devkits are only supposed to scale to 1.5 or 1.7 GHZ. Overclocking should not be the default state. Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano") Signed-off-by: Aaron Kling --- drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++------= ---- 1 file changed, 43 insertions(+), 19 deletions(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/f= use/speedo-tegra210.c index 695d0b7f9a8abe53c497155603147420cda40b63..60356159e00d2059e55eaacba27= b5ca63bf96c90 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -65,27 +65,51 @@ static void __init rev_sku_to_speedo_ids(struct tegra_s= ku_info *sku_info, sku_info->gpu_speedo_id =3D 0; *threshold =3D THRESHOLD_INDEX_0; =20 - switch (sku) { - case 0x00: /* Engineering SKU */ - case 0x01: /* Engineering SKU */ - case 0x07: - case 0x17: - case 0x27: - if (speedo_rev >=3D 2) + if (speedo_rev >=3D 2) { + switch (sku) { + case 0x00: /* Engineering SKU */ + case 0x01: /* Engineering SKU */ + case 0x13: + sku_info->cpu_speedo_id =3D 5; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x07: + case 0x17: + case 0x1F: + sku_info->cpu_speedo_id =3D 7; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x27: + sku_info->cpu_speedo_id =3D 1; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x83: + sku_info->cpu_speedo_id =3D 3; + sku_info->gpu_speedo_id =3D 3; + break; + + case 0x87: + sku_info->cpu_speedo_id =3D 2; sku_info->gpu_speedo_id =3D 1; - break; - - case 0x13: - if (speedo_rev >=3D 2) - sku_info->gpu_speedo_id =3D 1; - - sku_info->cpu_speedo_id =3D 1; - break; - - default: + break; + + case 0x8F: + sku_info->cpu_speedo_id =3D 9; + sku_info->gpu_speedo_id =3D 2; + break; + + default: + pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku); + /* Using the default for the error case */ + break; + } + } else if (sku =3D=3D 0x00 || sku =3D=3D 0x01 || sku =3D=3D 0x07 || sku = =3D=3D 0x13 || sku =3D=3D 0x17) { + sku_info->gpu_speedo_id =3D 1; + } else { pr_err("Tegra210: unknown SKU %#04x\n", sku); - /* Using the default for the error case */ - break; } } =20 --=20 2.50.1