From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F24C2C18A; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; cv=none; b=P3Xhpawf7G00K8cPqIweQEJ5UghK/zhPW9rs+zZnCn3anvjex0X1KfigsdnDRu3EeVt0J0Bs2uZq6oEo9LAq9cq8R1yPoVKp6etuQOIKfbwO5gEv40kdq3fpM2X2EwBBQmT/p5tQClZuf11VGJBnnZeLXgQq6YDVOV9tb3R9G84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; c=relaxed/simple; bh=azJJidwQGmkU3EAnsYHzQNhECcLwkhnufXPLFd5EkoY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ick90VhaOMumoK1l5IUyqAmxtuoa2I7YKWjsArr2JEcZ45TQYAFMyx6io9tH8/NswMxOLA9QHpjYxwzq8Q+BADyFEbCjaSYkfmxaOCukWjl6Bku9ZnjWO3NsRM+fb2xp4crj89EG2pg2PE/Rr0X77ebx+MClQ67F20YxiaNUE6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y6NoLQU2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y6NoLQU2" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3D6CC4CEF7; Wed, 3 Sep 2025 19:30:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756927823; bh=azJJidwQGmkU3EAnsYHzQNhECcLwkhnufXPLFd5EkoY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Y6NoLQU2vUF/wN07UHbDfQMC0h2gpNr+ap0txcRycyL4VYOi+P6N6BKQ9kUX+Yu/P 99R4iD+oNRe5+EcYxJSc7OykW3H1dMV2sR8OFbTU2sM2r1P89Xd1KAqrQiP4HzSu7R ogxRPn5TzXKxjsUoM0+adFqjf4++mBa93avbjbneabjlIQ0jX91U6pFl9L+2Geuse5 6gu9tZ+h0d7P33yQx9MZrCGHz8/AeOiTNLF4rNqn+S3xUyWleQvg40iMoTNolfTROn A2CATq0Y6O/faq7pWhMeHXPfXMocfLs4uhcRUK8mhIoJFjnW25d3p5boEESpnSz6fn D5/kJhsgZm71A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE948CA1009; Wed, 3 Sep 2025 19:30:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:30:16 -0500 Subject: [PATCH v2 1/4] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-tegra210-speedo-v2-1-89e6f86b8942@gmail.com> References: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756927822; l=1194; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=axF8VoKW1z4zF0BEmMzp42sD9+64WYeJh7/vhD2MdRk=; b=GFrHH9RpV8qd9w+3EfHF0coPiEC42v2Wpr+Ti33KTvOfyXPFojo6VwAuDz5QqhZ61O3hrwYom eSIF1u9ke9TAUtRBS6TbBOmUErspN5p7rIUcnz3VDv7vTTIPoIwYyNc X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling The dfll driver generates opp tables based on internal CVB tables instead of using dt opp tables. Some devices such as the Jetson Nano require limiting the max frequency even further than the corresponding CVB table allows in order to maintain thermal limits. Signed-off-by: Aaron Kling --- Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.t= xt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index f7d347385b5775ddd702ecbb9821acfc9d4b9ff2..8a049b684f962f2b06209a47866= 711b92c15c085 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -70,6 +70,9 @@ Required properties for PWM mode: - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. =20 +Optional properties for limiting frequency: +- nvidia,dfll-max-freq: Maximum scaling frequency in hertz. + Example for I2C: =20 clock@70110000 { --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F3842D5410; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; cv=none; b=gfm0TD47eMQsX5wq8ssBnmQWuT8xZGAcdDsP8oGxYboaIji3Wk6/Jpw6MX/iQZyP34cpvOln3j/M7BC43CyGK+8WK5W9ENG+Tvm7GX98c3ncEDD8Ej77TH6082OZE3JhMcXHGDcYslDkb6fICg5Ip9je1UnMuic8F2CT3sgSp+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927823; c=relaxed/simple; bh=3Ho4dQOZpk+HfDT50JDRPnGFGqzr/4gvezzMHb1Uyn8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E3NXbg4Y3LMTMfkdfDBV1gQnWTCx4G9A8xT1vXRvK2n5L69UNRhd9g5YPULVQtvRMmFgc4XA6A7zY8Xa24SQlijcCaNldZuya353t8kpMsxzd60lRoqhqVB+vHhXeBToMs6+FWgEftUR2IOn9AZ5tbjo6P3lfL3OPbaI/rLNiWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NXm8pPW9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NXm8pPW9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 06260C4CEF4; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756927823; bh=3Ho4dQOZpk+HfDT50JDRPnGFGqzr/4gvezzMHb1Uyn8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NXm8pPW9AK2Kw0erK7SSLUxkp+sz18WP0XsB+mam3ia9+HF5FdTmpkF/0gU9eLUeu dmorJ68Dr6R+nPyagi0OeadDfqJvOEspip0Cz30cduGAE24Xp4wPj11cb+tDgIjUTt gEM+hVWyHFxJkehRuFsBrsy2h8mBB00gPXT9OQgDmyIakkblmcQnC08wEEqXED94UN qT9v+3bpriA7OTGR3wkE3AEKSdktvmzcK2nRJkquZ1R/Ecy5c13eGYDYi7fog+uVqi FYBvwSxk5PxC3BBnGIfMjdJ2xrrq4PeGbqqphoZU+DmQIXxauSjls+wCnVXsfrW7tJ hqqWjkK/1OLww== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED35ECA1014; Wed, 3 Sep 2025 19:30:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:30:17 -0500 Subject: [PATCH v2 2/4] soc: tegra: fuse: speedo-tegra210: Update speedo ids Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-tegra210-speedo-v2-2-89e6f86b8942@gmail.com> References: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756927822; l=2732; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=+rnEMK4ZcZWLWnEqy8xfvGYxMDKH6aqGlW/aWu1EMXw=; b=Rtw4En8Nol3b3Pqyu9BdJK0rwTTTt5os7DFLrd70wJVDMZn+cLzJ4pMTGtnLG2QIX3EIyXxZX OH5UL6xYH9NDsYsEC1n7Yz/o+OUdc3oGJttdKKm2NHAlahOQuhPPMbP X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs code supports 11 ids and nouveau supports 5. This aligns with what the downstream vendor kernel supports. Align skus with the downstream list. The Tegra210 CVB tables were added in the first referenced fixes commit. Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the supported devkits are only supposed to scale to 1.5 or 1.7 GHZ. Overclocking should not be the default state. Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano") Signed-off-by: Aaron Kling --- drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++------= ---- 1 file changed, 43 insertions(+), 19 deletions(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/f= use/speedo-tegra210.c index 695d0b7f9a8abe53c497155603147420cda40b63..60356159e00d2059e55eaacba27= b5ca63bf96c90 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -65,27 +65,51 @@ static void __init rev_sku_to_speedo_ids(struct tegra_s= ku_info *sku_info, sku_info->gpu_speedo_id =3D 0; *threshold =3D THRESHOLD_INDEX_0; =20 - switch (sku) { - case 0x00: /* Engineering SKU */ - case 0x01: /* Engineering SKU */ - case 0x07: - case 0x17: - case 0x27: - if (speedo_rev >=3D 2) + if (speedo_rev >=3D 2) { + switch (sku) { + case 0x00: /* Engineering SKU */ + case 0x01: /* Engineering SKU */ + case 0x13: + sku_info->cpu_speedo_id =3D 5; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x07: + case 0x17: + case 0x1F: + sku_info->cpu_speedo_id =3D 7; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x27: + sku_info->cpu_speedo_id =3D 1; + sku_info->gpu_speedo_id =3D 2; + break; + + case 0x83: + sku_info->cpu_speedo_id =3D 3; + sku_info->gpu_speedo_id =3D 3; + break; + + case 0x87: + sku_info->cpu_speedo_id =3D 2; sku_info->gpu_speedo_id =3D 1; - break; - - case 0x13: - if (speedo_rev >=3D 2) - sku_info->gpu_speedo_id =3D 1; - - sku_info->cpu_speedo_id =3D 1; - break; - - default: + break; + + case 0x8F: + sku_info->cpu_speedo_id =3D 9; + sku_info->gpu_speedo_id =3D 2; + break; + + default: + pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku); + /* Using the default for the error case */ + break; + } + } else if (sku =3D=3D 0x00 || sku =3D=3D 0x01 || sku =3D=3D 0x07 || sku = =3D=3D 0x13 || sku =3D=3D 0x17) { + sku_info->gpu_speedo_id =3D 1; + } else { pr_err("Tegra210: unknown SKU %#04x\n", sku); - /* Using the default for the error case */ - break; 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Wed, 3 Sep 2025 19:30:23 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:30:18 -0500 Subject: [PATCH v2 3/4] clk: tegra: dfll: Support limiting max clock per device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-tegra210-speedo-v2-3-89e6f86b8942@gmail.com> References: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756927822; l=1454; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=HHRtvxWltZLOQ+/PSjEx/VXgJfA/2/uQ/lKhb4XDMgk=; b=AzsH+wmGolTg4V4dHGipf3kg2dmJoNVJ9qnBLjnDNA9iqyCI5SAu8/HjJ5D1MKfuU8+UVSvpK LZ1CiYib7u9CX6v8N7ZJkoB7HgYqdCYjUquMiONQIYIV0PGE3mLK8Vn X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Some devices like the Jetson Nano report a cpu speedo value that scales past the thermal limits of the device. This allows limiting the maximum scaling to a lower value within the table. Signed-off-by: Aaron Kling --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra= /clk-tegra124-dfll-fcpu.c index 0251618b82c8321724ba0aec7a5bd90b2c2ffaf2..0c84f7e85baaa96fee005a1c9a5= dd6afbd1875fa 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -556,6 +556,7 @@ static int tegra124_dfll_fcpu_probe(struct platform_dev= ice *pdev) struct tegra_dfll_soc_data *soc; const struct dfll_fcpu_data *fcpu_data; struct rail_alignment align; + u32 max_freq; =20 fcpu_data =3D of_device_get_match_data(&pdev->dev); if (!fcpu_data) @@ -589,7 +590,12 @@ static int tegra124_dfll_fcpu_probe(struct platform_de= vice *pdev) return err; } =20 - soc->max_freq =3D fcpu_data->cpu_max_freq_table[speedo_id]; + if (!of_property_read_u32(pdev->dev.of_node, + "nvidia,dfll-max-freq", + &max_freq)) + soc->max_freq =3D max_freq; + else + soc->max_freq =3D fcpu_data->cpu_max_freq_table[speedo_id]; =20 soc->cvb =3D tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, fcpu_data->cpu_cvb_tables_size, --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF84636C09C; Wed, 3 Sep 2025 19:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927825; cv=none; b=LsudME2PHmT+45XdjJcC7a5hpACEC3RZ5VJRgoVyvrCqCVxb7SDu8XDvKVyCNP5RiOoOFeWJdU+R+PILyxOm1EwKHOmmsDHE1ljVkW1a/SWjkXzskRUMiOnhljluTIkduN9O/284x73wFl9PUFUYgnCdarZvW583MDZvarnLS5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756927825; c=relaxed/simple; bh=+xzil/sVgMBAdiMnRT0qcaWqUHWEi1QVZ8JVT0hYILY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 3 Sep 2025 19:30:23 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:30:19 -0500 Subject: [PATCH v2 4/4] arm64: tegra: Limit max cpu frequency on P3450 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-tegra210-speedo-v2-4-89e6f86b8942@gmail.com> References: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756927822; l=1064; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=rvlN/VFiSk4fMaswOe6B/D7AZjiaIQvg0SL5D0yqtS0=; b=YkKq8lZfkehrpT3fO7C3dKV037r4tRTVI8oXjEx1ua8/9mSN1NhVlwjNRMnwpBkIDycwYZ3d9 H0GKjosoV7fDd8JW0ReeqlHCfNNvMUxzu1X/GfCgc8qW11lT6BD2eJP X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling P3450's cpu is rated for 1.5 GHz, but due to the passive cooling on the devkit, the maximum frequency needs limited to 1.4 GHz to maintain reasonable thermals. Ideally, the dfll driver would adjust based on temperature reporting, but in the absence of that, this will have to do. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm6= 4/boot/dts/nvidia/tegra210-p3450-0000.dts index ec0e84cb83ef9bf8f0e52e2958db33666813917c..10f878d3f50815d1f0297d15669= 048ab9cad73ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -594,6 +594,7 @@ clock@70110000 { nvidia,droop-ctrl =3D <0x00000f00>; nvidia,force-mode =3D <1>; nvidia,sample-rate =3D <25000>; + nvidia,dfll-max-freq =3D <1479000000>; =20 nvidia,pwm-min-microvolts =3D <708000>; nvidia,pwm-period-nanoseconds =3D <2500>; /* 2.5us */ --=20 2.50.1