From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A60B2DD5F0; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; cv=none; b=QFgfjXBKeIlK0WvO64m+YxOxVLs1OGOIMt309sgd8cZSom4dqzmiGMdUR3hmYQLhAi7QmH0GRtoG79gOVi/qgNMXGc2e2CGIJjnP3c0vVLQg1SX27MLBrDMnsJ0sYAi718FTBvy4x8nP29atvOtTbgUZtP25n4M5zQdSCoVWMa0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; c=relaxed/simple; bh=WvscYjNV7L8ZvTOF8eWp1hlu2vZN99N5LQ99hENMYGs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QP0NbsY74jFZozQYamQrmndOvn7e+UTtjtXCJxKKNr/2EJ9w8C5TSWCUUp8evpzXfMDz6QYsDvDfGbC75KCDF0fbmQjnDnQStywJida+Pl0Mire1ZoRm3g9rKycuD+fIV6HMOmIHq9cok76vwoXl+6pW3J31tpO/PBCtYUEFo84= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A6GZYylD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A6GZYylD" Received: by smtp.kernel.org (Postfix) with ESMTPS id E7196C4CEF4; Wed, 3 Sep 2025 19:51:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756929082; bh=WvscYjNV7L8ZvTOF8eWp1hlu2vZN99N5LQ99hENMYGs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A6GZYylD3bdjJCC6+NJY7WbXhr7gksG+VjvFiyj65disCEAHkwVZgf2K3w6p0dLRm gaPCkQ7tHH57laUQKrhf+s+mzqwKKfrXZ6zr0ABs8LPVNMxVPnhEvfZjbBQMq+D3Qo 1GHD6J4cU5HzZMXeUcP1+xOKbyqWr/WJ56A3dwLOG0/FK3rD1vwc0pnlhYyfy1sceU Iysm1VqQI3Ft1p1YG1kWOJr7ap0tUyEZDSwUQeSGgoCjFumW3SXonL7R73Lki/Iuy+ 4nlMiyYblO9xOrvnRmXy94fJaH7eaNpQICE3GrecmH7Jsz5rVuzkH5tNCnS627TAEg ssdQUf3twk0rw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2849CA1009; Wed, 3 Sep 2025 19:51:21 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:50:07 -0500 Subject: [PATCH v2 1/8] dt-bindings: memory: tegra210: Add memory client IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-1-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=2616; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=u4jz33x6Ez21364iFx09PcoppaXBOvLz3qVMpDfajQM=; b=jwCuxoaY3bOoo8wi4XjARXBSG/QkzkFM5CtaxIZHz+MOPAKmpnL3LAHrzhPLHPWcX020Nnxpk zledt4VNotnCt6ZZN/K2+TFgiAVHB4T91Crx4o4ltK6kIY4MLsqFqyq X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Each memory client has unique hardware ID, add these IDs. Signed-off-by: Aaron Kling --- include/dt-bindings/memory/tegra210-mc.h | 58 ++++++++++++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings= /memory/tegra210-mc.h index 5e082547f1794cba1f72872782e04d8747863b6d..48474942a000e049142014e3bcc= 132b88bf1a92d 100644 --- a/include/dt-bindings/memory/tegra210-mc.h +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -75,4 +75,62 @@ #define TEGRA210_MC_RESET_ETR 28 #define TEGRA210_MC_RESET_TSECB 29 =20 +#define TEGRA210_MC_PTCR 0 +#define TEGRA210_MC_DISPLAY0A 1 +#define TEGRA210_MC_DISPLAY0AB 2 +#define TEGRA210_MC_DISPLAY0B 3 +#define TEGRA210_MC_DISPLAY0BB 4 +#define TEGRA210_MC_DISPLAY0C 5 +#define TEGRA210_MC_DISPLAY0CB 6 +#define TEGRA210_MC_AFIR 14 +#define TEGRA210_MC_AVPCARM7R 15 +#define TEGRA210_MC_DISPLAYHC 16 +#define TEGRA210_MC_DISPLAYHCB 17 +#define TEGRA210_MC_HDAR 21 +#define TEGRA210_MC_HOST1XDMAR 22 +#define TEGRA210_MC_HOST1XR 23 +#define TEGRA210_MC_NVENCSRD 28 +#define TEGRA210_MC_PPCSAHBDMAR 29 +#define TEGRA210_MC_PPCSAHBSLVR 30 +#define TEGRA210_MC_SATAR 31 +#define TEGRA210_MC_MPCORER 39 +#define TEGRA210_MC_NVENCSWR 43 +#define TEGRA210_MC_AFIW 49 +#define TEGRA210_MC_AVPCARM7W 50 +#define TEGRA210_MC_HDAW 53 +#define TEGRA210_MC_HOST1XW 54 +#define TEGRA210_MC_MPCOREW 57 +#define TEGRA210_MC_PPCSAHBDMAW 59 +#define TEGRA210_MC_PPCSAHBSLVW 60 +#define TEGRA210_MC_SATAW 61 +#define TEGRA210_MC_ISPRA 68 +#define TEGRA210_MC_ISPWA 70 +#define TEGRA210_MC_ISPWB 71 +#define TEGRA210_MC_XUSB_HOSTR 74 +#define TEGRA210_MC_XUSB_HOSTW 75 +#define TEGRA210_MC_XUSB_DEVR 76 +#define TEGRA210_MC_XUSB_DEVW 77 +#define TEGRA210_MC_ISPRAB 78 +#define TEGRA210_MC_ISPWAB 80 +#define TEGRA210_MC_ISPWBB 81 +#define TEGRA210_MC_TSECSRD 84 +#define TEGRA210_MC_TSECSWR 85 +#define TEGRA210_MC_A9AVPSCR 86 +#define TEGRA210_MC_A9AVPSCW 87 +#define TEGRA210_MC_GPUSRD 88 +#define TEGRA210_MC_GPUSWR 89 +#define TEGRA210_MC_DISPLAYT 90 +#define TEGRA210_MC_SDMMCRA 96 +#define TEGRA210_MC_SDMMCRAA 97 +#define TEGRA210_MC_SDMMCR 98 +#define TEGRA210_MC_SDMMCRAB 99 +#define TEGRA210_MC_SDMMCWA 100 +#define TEGRA210_MC_SDMMCWAA 101 +#define TEGRA210_MC_SDMMCW 102 +#define TEGRA210_MC_SDMMCWAB 103 +#define TEGRA210_MC_VICSRD 108 +#define TEGRA210_MC_VICSWR 109 +#define TEGRA210_MC_VIW 114 +#define TEGRA210_MC_DISPLAYD 115 + #endif --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A67F302756; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-2-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=1201; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=xdS30eId+rCA7n/+A0teGQz4FyQXYRBMZykKI3Thnc0=; b=Mfq5tSzd+j2FvPyNwhUIkTI/PvaRw7O8B4wo2p+Aw9v1Yu8h6kgspGVtqQIOf6sobt1uTkJ2J ruq7/jed9gGD3uoKIrbH/NPY/vdjdJ7a0v0k3jQAdTCXuN3LjwKfYcV X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling The Tegra210 actmon is compatible with the existing Tegra124 driver. Describe the compatibles as such. Signed-off-by: Aaron Kling Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml | 13 ++++++++-= ---- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmo= n.yaml b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.ya= ml index e3379d1067283e36d1bee303187c0205b410f610..ea1dc86bc31f635f91a0e36f908= f5c0c4f9a804c 100644 --- a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml +++ b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml @@ -19,11 +19,14 @@ description: | =20 properties: compatible: - enum: - - nvidia,tegra30-actmon - - nvidia,tegra114-actmon - - nvidia,tegra124-actmon - - nvidia,tegra210-actmon + oneOf: + - enum: + - nvidia,tegra30-actmon + - nvidia,tegra114-actmon + - nvidia,tegra124-actmon + - items: + - const: nvidia,tegra210-actmon + - const: nvidia,tegra124-actmon =20 reg: maxItems: 1 --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4872529D0E; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; cv=none; b=ZDEE9ygRJEMzhQo71rCvl7W4zi9706GzOWTK8hGVLcZT634lbUZZmDiLSi2RUIn2WjFMqiyhPwzGLskw+P+c6S2ScKNkAcX52HsjqKv2Mf6AQd5qE/sNyBTM2V7kxFyHA0/WYZdI9Pkuw/+zlrRDQ+ksxScot/s5mNzFjfW4B2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; c=relaxed/simple; bh=ZrwUlWy03isuqvxOKByHbLLf2ZTO8JbgUT7l+eh/EMs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YVWfrUa2ywCq18glUHWQj1mEd1hacBIwFUubDX8yAieTHmEpF2RQpQDkL2KH3m3KmwQtgJr7odYzGl0nLuefvPNmzarL6NzSes2rIE7zhF1Cd6ratVruysYOJdNuYXWYvShTP9KaSGurr0I9icIMIlsGjOJxbsUtk3yO+ES0LtY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eGVvQtKS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eGVvQtKS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0EF7DC4CEF8; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756929082; bh=ZrwUlWy03isuqvxOKByHbLLf2ZTO8JbgUT7l+eh/EMs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eGVvQtKSS9kq+xKK46dWUv4K2mbKg38OYZ7PP/hYsQi3O2XwZNhVOa9PMMpYI3yvc 2Rz2vo7BJUQNRZV50Kbts+rg7NhlOMZLATWi0ncMavOO4ScWj14AgMkRyFO3qrhtLv u/srz+EUpZmxT+RXGkdEjrqDucLf6enr56hd2yXap00UsPueUGVN+qpDok2cSJNjSa SJNLJ9IBsrydUOzfSt3Nui6w99BOvjgJUPGHkKt9VInr71djPve7/tW9wJR2n+/2bI it3M6JRG4QAzbOvHws5AcPCsZbeS4cQUr5nsmbzQVALUuQv4i2A6DXk91bd3K4NlYF jYt/511dAZwTg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 016C6CA1012; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:50:09 -0500 Subject: [PATCH v2 3/8] dt-bindings: memory: tegra210: emc: Document OPP table and interconnect Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-3-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=1636; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=K2FiUX5RaQ8JIyiwJYROz1L0fIFkHw1QV6kZZgZpZpE=; b=a3XwoxVKj3KIyN1sfx6WAt8dO8deBXsuTH5RUBeN0rOiebE0O1Zz2wuV/4gKo49fXFAUf5JWN 2x/8w2pD+N/CQYstWrDslVvNpu4CAJJWftTSeahU49I0yG4VKGcG2nK X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling These are needed for dynamic frequency scaling of the EMC controller. Signed-off-by: Aaron Kling --- .../bindings/memory-controllers/nvidia,tegra210-emc.yaml | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvid= ia,tegra210-emc.yaml index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535= c1ff918bcdb2a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-= emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-= emc.yaml @@ -33,6 +33,9 @@ properties: items: - description: EMC general interrupt =20 + "#interconnect-cells": + const: 0 + memory-region: maxItems: 1 description: @@ -44,12 +47,19 @@ properties: description: phandle of the memory controller node =20 + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, whi= ch + is a bitfield indicating SoC speedo ID mask. + required: - compatible - reg - clocks - clock-names + - "#interconnect-cells" - nvidia,memory-controller + - operating-points-v2 =20 additionalProperties: false =20 @@ -79,4 +89,7 @@ examples: interrupts =3D ; memory-region =3D <&emc_table>; nvidia,memory-controller =3D <&mc>; + operating-points-v2 =3D <&dvfs_opp_table>; + + #interconnect-cells =3D <0>; }; --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 584BD2D375D; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; cv=none; b=pBv5M3HolIRjNpE96zRLqH1J7lQU4HsmaO7nXK8McIQqUfv3hUs/5g/khJYN+z6fZS97HJmNCU90P5KPVPlZEzC7JQQ0SxGgOHqg1QB3b5eyQQkb5JJsV1SUFuIUYcb64K2tKwbim5Ug4UGrOjq3H+H9ly6gfajIseXekMSYMvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; c=relaxed/simple; bh=QE+tJk1zGwmAgzpewZ2cpQB2QWRaftfJfeA1AtKdsDQ=; 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Wed, 3 Sep 2025 19:51:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:50:10 -0500 Subject: [PATCH v2 4/8] soc: tegra: fuse: speedo-tegra210: Add soc speedo 2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-4-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=904; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=IRRKZEiLQdonkqHTuobp6JolP/SAC2dsrByPD6yqKl4=; b=UgUDh8BGqyCC4bvag8hU2oislyDKSzclNPKEAvoLqqi8Y4SMtP8slXqeNp3TpYwtt5msVhOqC jZ44x5QcxmKBKqpW692D8qfVo58xKa9tlaMvOPyUh3598ga1tCUqhJ5 X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling The Jetson Nano series of modules only have 2 emc table entries, different from other soc sku's. As the emc driver uses the soc speedo to populate the emc opp tables, add a new speedo id to uniquely identify this. Signed-off-by: Aaron Kling --- drivers/soc/tegra/fuse/speedo-tegra210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/f= use/speedo-tegra210.c index 60356159e00d2059e55eaacba27b5ca63bf96c90..c310bdabcfd06ea8f23facb4eaa= f209f183dc4eb 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -97,6 +97,7 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku= _info *sku_info, break; =20 case 0x8F: + sku_info->soc_speedo_id =3D 2; sku_info->cpu_speedo_id =3D 9; sku_info->gpu_speedo_id =3D 2; break; --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1035369988; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; cv=none; b=oQ7kXHW/MBu6raS3BvSQNc34mc3WUIZteKmMFH12CWujIztzNNPfLliwLxqSo9TWP0uE+jMLpqGzSELUDHpFQ6q52Hi2dHzCzw04Qp3Q8HmBPoaw1MM43tI14UjpNBDVNyNhHQOp9liVSExogvQQeDgqIk4DiDxctpZ8X9gs38Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; c=relaxed/simple; bh=Z6XSGha9VP9RydAR4SXzgMBp212P+2NBFsjXPt32XqU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KwILqZB02vcr8c0+Vb8+hta0SKRm+MCmpaDfZVAaza7VIIJTFZVPb29ILgwiW5jdtwcGhb0ydfaW4+0CYZOQAy8j3se15MdEzRlitRnhOZ1NMXuA55gGwHNtsaH3ju+4xRej2rxgnvzoJJUureZiZH//MzujCachcmu+PI72jDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oZoZiQqt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oZoZiQqt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2BCE5C113CF; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756929082; bh=Z6XSGha9VP9RydAR4SXzgMBp212P+2NBFsjXPt32XqU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oZoZiQqtA2Q0eMyaf4gE/bQp54qDGalG/4N9IZzARiQPGGld+uQi//TRaAv5z1bpS 0oxssXs+WdWMC22+CXyeciU9OQE2JM5/YSNci2mmzL8AoUWSut6y4j7tXE9ZThPF5s fkJ23QIdCd3/yXW5exS25ww6QuCkpeJ0NGHN7ZQsuOVJ1/dmpCGYGHxHgn8P4DjtkZ Bzyjr+t4ghmXpHyB/7255o2sZVyYKNkKbHdpyDMKtwdClmfd7Mbw7HxpGUWo9FQNEs wDaDGJ9Ex0ysSfPjgYblK6VnOgUOR+0y0tiIVB9WqPjr+9lmodHQaVZOB64KzU7Mul +W4FfNjNsVicA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 232D3CA1016; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:50:11 -0500 Subject: [PATCH v2 5/8] memory: tegra210: Support interconnect framework Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-5-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=14654; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=7mf8HIHaExe48hwUfk5YfEiinYyxf2FlYlNDUi4zoy8=; b=zD74c1+rIaQ6wZ74DRIUdWctXO/wDnQoYGiib2nHssEqyRWZrHLEtsxvWDIYSQj7FuMg3OBdZ /244AlMMtT3C6Kbou3pcG555ip/9fJMkuBRgyH+32UD96z+d4JZNrn/ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling This makes mc and emc interconnect providers and allows for dynamic memory clock scaling. Signed-off-by: Aaron Kling --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra210-emc-core.c | 274 +++++++++++++++++++++++++++= +++- drivers/memory/tegra/tegra210-emc.h | 23 +++ drivers/memory/tegra/tegra210.c | 81 +++++++++ 4 files changed, 377 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index fc5a277918267ee8240f9fb9efeb80275db4790b..2d0be29afe2b9ebf9a0630ef7fb= 6fb43ff359499 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -55,6 +55,7 @@ config TEGRA210_EMC tristate "NVIDIA Tegra210 External Memory Controller driver" depends on ARCH_TEGRA_210_SOC || COMPILE_TEST select TEGRA210_EMC_TABLE + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra210 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegr= a/tegra210-emc-core.c index e96ca4157d48182574310f8caf72687bed7cc16a..f12e60b47fa87d629505cde5731= 0d2bb68fc87f3 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1569,6 +1570,79 @@ static int tegra210_emc_set_rate(struct device *dev, return 0; } =20 +static void tegra_emc_rate_requests_init(struct tegra210_emc *emc) +{ + unsigned int i; + + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate =3D 0; + emc->requested_rate[i].max_rate =3D ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra210_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D emc->requested_rate; + unsigned long min_rate =3D 0, max_rate =3D ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i =3D=3D type) { + min_rate =3D max(new_min_rate, min_rate); + max_rate =3D min(new_max_rate, max_rate); + } else { + min_rate =3D max(req->min_rate, min_rate); + max_rate =3D min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + err =3D clk_set_rate(emc->clk, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate =3D new_min_rate; + emc->requested_rate[type].max_rate =3D new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra210_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra210_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -1641,7 +1715,7 @@ static int tegra210_emc_debug_min_rate_set(void *data= , u64 rate) if (!tegra210_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_min_rate(emc->clk, rate); + err =3D emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -1671,7 +1745,7 @@ static int tegra210_emc_debug_max_rate_set(void *data= , u64 rate) if (!tegra210_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_max_rate(emc->clk, rate); + err =3D emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -1758,6 +1832,193 @@ static void tegra210_emc_debugfs_init(struct tegra2= 10_emc *emc) &tegra210_emc_debug_temperature_fops); } =20 +static inline struct tegra210_emc * +to_tegra210_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra210_emc, icc_provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider =3D data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id !=3D TEGRA_ICC_EMEM) + continue; + + ndata =3D kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag =3D TEGRA_MC_ICC_TAG_ISO; + ndata->node =3D node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra210_emc *emc =3D to_tegra210_emc_provider(dst->provider); + unsigned long long peak_bw =3D icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw =3D icc_units_to_bps(dst->avg_bw); + unsigned long long rate =3D max(avg_bw, peak_bw); + const unsigned int ddr =3D 2; + int err; + + /* + * Tegra210 memory layout can be 1 channel at 64-bit or 2 channels + * at 32-bit each. Either way, the total bus width will always be + * 64-bit. + */ + const unsigned int dram_data_bus_width_bytes =3D 64 / 8; + + /* + * Tegra210 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + do_div(rate, ddr * dram_data_bus_width_bytes); + rate =3D min_t(u64, rate, U32_MAX); + + err =3D emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 = *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra210_emc *emc) +{ + const struct tegra_mc_soc *soc =3D emc->mc->soc; + struct icc_node *node; + int err; + + emc->icc_provider.dev =3D emc->dev; + emc->icc_provider.set =3D emc_icc_set; + emc->icc_provider.data =3D &emc->icc_provider; + emc->icc_provider.aggregate =3D soc->icc_ops->aggregate; + emc->icc_provider.xlate_extended =3D emc_of_icc_xlate_extended; + emc->icc_provider.get_bw =3D tegra_emc_icc_get_init_bw; + + icc_provider_init(&emc->icc_provider); + + /* create External Memory Controller node */ + node =3D icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err =3D PTR_ERR(node); + goto err_msg; + } + + node->name =3D "External Memory Controller"; + icc_node_add(node, &emc->icc_provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err =3D icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node =3D icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err =3D PTR_ERR(node); + goto remove_nodes; + } + + node->name =3D "External Memory (DRAM)"; + icc_node_add(node, &emc->icc_provider); + + err =3D icc_provider_register(&emc->icc_provider); + if (err) + goto remove_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->icc_provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra210_emc *emc) +{ + u32 hw_version =3D BIT(tegra_sku_info.soc_speedo_id); + struct dev_pm_opp *opp; + unsigned long rate; + int opp_token, err, max_opps, i; + + err =3D dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + if (err < 0) { + dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); + return err; + } + opp_token =3D err; + + err =3D dev_pm_opp_of_add_table(emc->dev); + if (err) { + if (err =3D=3D -ENODEV) + dev_err(emc->dev, "OPP table not found, please update your device tree\= n"); + else + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + + goto put_hw_table; + } + + max_opps =3D dev_pm_opp_get_opp_count(emc->dev); + if (max_opps <=3D 0) { + dev_err(emc->dev, "Failed to add OPPs\n"); + goto remove_table; + } + + if (emc->num_timings !=3D max_opps) { + dev_err(emc->dev, "OPP table does not match emc table\n"); + goto remove_table; + } + + for (i =3D 0; i < emc->num_timings; i++) { + rate =3D emc->timings[i].rate * 1000; + opp =3D dev_pm_opp_find_freq_exact(emc->dev, rate, true); + if (IS_ERR(opp)) { + dev_err(emc->dev, "Rate %lu not found in OPP table\n", rate); + goto remove_table; + } + + dev_pm_opp_put(opp); + } + + dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_hw_table: + dev_pm_opp_put_supported_hw(opp_token); + + return err; +} + static void tegra210_emc_detect(struct tegra210_emc *emc) { u32 value; @@ -1964,8 +2225,16 @@ static int tegra210_emc_probe(struct platform_device= *pdev) =20 timer_setup(&emc->training, tegra210_emc_train, 0); =20 + err =3D tegra_emc_opp_table_init(emc); + if (err) + return err; + + tegra_emc_rate_requests_init(emc); + tegra210_emc_debugfs_init(emc); =20 + tegra_emc_interconnect_init(emc); + cd =3D devm_thermal_of_cooling_device_register(emc->dev, np, "emc", emc, &tegra210_emc_cd_ops); if (IS_ERR(cd)) { @@ -2050,6 +2319,7 @@ static struct platform_driver tegra210_emc_driver =3D= { .name =3D "tegra210-emc", .of_match_table =3D tegra210_emc_of_match, .pm =3D &tegra210_emc_pm_ops, + .sync_state =3D icc_sync_state, }, .probe =3D tegra210_emc_probe, .remove =3D tegra210_emc_remove, diff --git a/drivers/memory/tegra/tegra210-emc.h b/drivers/memory/tegra/teg= ra210-emc.h index 8988bcf1529072a7bdc93b185ebe0d51d82c1763..3c9142bfd5ae5c57bbc139e69e6= 2c893b50ce40c 100644 --- a/drivers/memory/tegra/tegra210-emc.h +++ b/drivers/memory/tegra/tegra210-emc.h @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include =20 @@ -784,6 +785,17 @@ enum { #define TRIM_REGS_SIZE 138 #define BURST_REGS_SIZE 221 =20 +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra210_emc_per_channel_regs { u16 bank; u16 offset; @@ -932,6 +944,17 @@ struct tegra210_emc { } debugfs; =20 struct tegra210_clk_emc_provider provider; + + struct icc_provider icc_provider; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; =20 struct tegra210_emc_sequence { diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index 8ab6498dbe7d2f410d4eb262926c18b77edb0b3d..c5f079b60363f86b9b1382182e7= 1bfcea9e19829 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -3,6 +3,9 @@ * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved. */ =20 +#include +#include + #include =20 #include "mc.h" @@ -1273,6 +1276,83 @@ static const struct tegra_mc_reset tegra210_mc_reset= s[] =3D { TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13), }; =20 +static int tegra210_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* TODO: program PTSA */ + return 0; +} + +static int tegra210_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 a= vg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw =3D tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg +=3D avg_bw; + *agg_peak =3D max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra210_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void= *data) +{ + struct tegra_mc *mc =3D icc_provider_to_tegra_mc(data); + const struct tegra_mc_client *client; + unsigned int i, idx =3D spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id !=3D idx) + continue; + + ndata =3D kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + client =3D &mc->soc->clients[idx]; + ndata->node =3D node; + + switch (client->swgroup) { + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + case TEGRA_SWGROUP_PTC: + case TEGRA_SWGROUP_VI: + /* these clients are isochronous by default */ + ndata->tag =3D TEGRA_MC_ICC_TAG_ISO; + break; + + default: + ndata->tag =3D TEGRA_MC_ICC_TAG_DEFAULT; + break; + } + + return ndata; + } + + for (i =3D 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id =3D=3D idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra210_mc_icc_ops =3D { + .xlate_extended =3D tegra210_mc_of_icc_xlate_extended, + .aggregate =3D tegra210_mc_icc_aggregate, + .set =3D tegra210_mc_icc_set, +}; + const struct tegra_mc_soc tegra210_mc_soc =3D { .clients =3D tegra210_mc_clients, .num_clients =3D ARRAY_SIZE(tegra210_mc_clients), @@ -1286,5 +1366,6 @@ const struct tegra_mc_soc tegra210_mc_soc =3D { .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra210_mc_resets, .num_resets =3D ARRAY_SIZE(tegra210_mc_resets), + .icc_ops =3D &tegra210_mc_icc_ops, .ops =3D &tegra30_mc_ops, }; --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F939369986; 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Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index 402b0ede1472af625d9d9e811f5af306d436cc98..6da10db893add44a98fde1666c3= 82511212fd43c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -485,6 +485,18 @@ flow-controller@60007000 { reg =3D <0x0 0x60007000 0x0 0x1000>; }; =20 + actmon@6000c800 { + compatible =3D "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; + reg =3D <0x0 0x6000c800 0x0 0x400>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA210_CLK_ACTMON>, + <&tegra_car TEGRA210_CLK_EMC>; + clock-names =3D "actmon", "emc"; + resets =3D <&tegra_car 119>; + reset-names =3D "actmon"; + #cooling-cells =3D <2>; + }; + gpio: gpio@6000d000 { compatible =3D "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg =3D <0x0 0x6000d000 0x0 0x1000>; --=20 2.50.1 From nobody Fri Oct 3 07:40:19 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEEAB369993; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; cv=none; b=LinZh8EC++U1bdLVc+XTDk/yPNOvW+4Nxr4WzGX/mTUJK6dKfdwP/2XEioBxFBuQITLWigOoq39+oO0SizHwpwZji/vvFWUDO9D/2mOsUwI9Qv9kQ/e/RMhmlpN73QwwktSeTKAnR31aJ8RzuXVlnI74opEK56/qaAhx//TyUxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756929082; c=relaxed/simple; bh=gosAl1zQ0z5viYliFA0S6p65O6ADdSW+IUkYdiR08BU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=buQNbYMndUJInLqmkAliWC0n60DX8jL/u68H8LVoaTHtRyO8BUk3L6mQM6zBLcCGyy5KDatax2iMHfRs+N6wZmjwWzaVVvIrwyJMQpMowcRTD+I9oC44ocvW75MHJd/OH9ilNa6ExIr95ooU79y9ugq9ktys/jmXz4z82GFWFUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=grannp+t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="grannp+t" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4911DC4CEF9; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756929082; bh=gosAl1zQ0z5viYliFA0S6p65O6ADdSW+IUkYdiR08BU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=grannp+tQCTQDMgXylmxFoh0XeyE9JFwhC+91GvvcH741TvKLpVQEn5/2dSiDLnyf c07AaDEO8yt4v34ZKlrbDdKlzJ0sAYV3K1fN2toC+Xj7Wq9hgLb7X3doTgRNDhPf3q gGZh4vY+JRcVvWTStYG8WhH0iC8zYu3EkkFEEoYxAisG1K6WM4LYWuA1MwDJJER/QT QOMEFgelhwr9+izlG9v/Aaw78hVt03SUcqOXKJ+dUvDZENuoSdzT1zXL1gsZVXdnk1 NJpVAoRIR0nrV/OFQguFRuj86kh25T6jJ0b7XfiIgqVsHv9W0xcf/F+vf8XrhYtFZ6 ATpJyV2MKAwAg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F33ACA1015; Wed, 3 Sep 2025 19:51:22 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 03 Sep 2025 14:50:13 -0500 Subject: [PATCH v2 7/8] arm64: tegra: Add interconnect properties to Tegra210 device-tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-7-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=2042; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=dV5rTm0DsZp/CMwTv4aBWDsgqy68fQx2GO3uvjxraWo=; b=8KJrmH7vWHUUfCAjtvitM9AHQNN1+mEHjvJngDdk8ep6XUBYc2UNFXjXWYNnnl3uWchMEJHUv kFpJ7toCSUMD3c0Ar9qaNBYe+3j6/6jnSdAy++/90eQtXqLp4zQmRBE X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index 6da10db893add44a98fde1666c382511212fd43c..2fcc7a28690f7100d49e8b93c4f= b77de7947b002 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -202,6 +202,19 @@ dc@54200000 { =20 nvidia,outputs =3D <&dsia &dsib &sor0 &sor1>; nvidia,head =3D <0>; + + interconnects =3D <&mc TEGRA210_MC_DISPLAY0A &emc>, + <&mc TEGRA210_MC_DISPLAY0B &emc>, + <&mc TEGRA210_MC_DISPLAY0C &emc>, + <&mc TEGRA210_MC_DISPLAYHC &emc>, + <&mc TEGRA210_MC_DISPLAYD &emc>, + <&mc TEGRA210_MC_DISPLAYT &emc>; + interconnect-names =3D "wina", + "winb", + "winc", + "cursor", + "wind", + "wint"; }; =20 dc@54240000 { @@ -217,6 +230,15 @@ dc@54240000 { =20 nvidia,outputs =3D <&dsia &dsib &sor0 &sor1>; nvidia,head =3D <1>; + + interconnects =3D <&mc TEGRA210_MC_DISPLAY0AB &emc>, + <&mc TEGRA210_MC_DISPLAY0BB &emc>, + <&mc TEGRA210_MC_DISPLAY0CB &emc>, + <&mc TEGRA210_MC_DISPLAYHCB &emc>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-t210-actmon-v2-8-e0d534d4f8ea@gmail.com> References: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> In-Reply-To: <20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756929080; l=4992; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=BuMztMnAqa18LOpanMPfXZmvaUGQqA9O6CgvPF/UAwU=; b=miTCqaJTF7Z6CMFpHfUX7yUg4mXsyzbJAYSjxF4Colc94wdeub5zc7nIuqQBh8TBv7fuKrRHS B40PCiHuQGcDlv7RmpO46VYQSWn+Nbel3/7HOepGjOtLjL+RUuDNw7Q X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling This adds OPP tables for actmon and emc, enabling dynamic frequency scaling for ram. Signed-off-by: Aaron Kling --- .../boot/dts/nvidia/tegra210-peripherals-opp.dtsi | 135 +++++++++++++++++= ++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 ++ 2 files changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi b/arc= h/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..bf2527d737932a1f41aa83d61f4= 4d87ba52b0519 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible =3D "operating-points-v2"; + + opp-40800000-800 { + opp-microvolt =3D <800000 800000 1150000>; + opp-hz =3D /bits/ 64 <40800000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-68000000-800 { + opp-microvolt =3D <800000 800000 1150000>; + opp-hz =3D /bits/ 64 <68000000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-102000000-800 { + opp-microvolt =3D <800000 800000 1150000>; + opp-hz =3D /bits/ 64 <102000000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-204000000-800 { + opp-microvolt =3D <800000 800000 1150000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x0007>; + opp-suspend; + }; + + opp-408000000-812 { + opp-microvolt =3D <812000 812000 1150000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-665600000-825 { + opp-microvolt =3D <825000 825000 1150000>; + opp-hz =3D /bits/ 64 <665600000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-800000000-825 { + opp-microvolt =3D <825000 825000 1150000>; + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-1065600000-837 { + opp-microvolt =3D <837000 837000 1150000>; + opp-hz =3D /bits/ 64 <1065600000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-1331200000-850 { + opp-microvolt =3D <850000 850000 1150000>; + opp-hz =3D /bits/ 64 <1331200000>; + opp-supported-hw =3D <0x0003>; + }; + + opp-1600000000-887 { + opp-microvolt =3D <887000 887000 1150000>; + opp-hz =3D /bits/ 64 <1600000000>; + opp-supported-hw =3D <0x0007>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible =3D "operating-points-v2"; + + opp-40800000 { + opp-hz =3D /bits/ 64 <40800000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <652800>; + }; + + opp-68000000 { + opp-hz =3D /bits/ 64 <68000000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <1088000>; + }; + + opp-102000000 { + opp-hz =3D /bits/ 64 <102000000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <1632000>; + }; + + opp-204000000 { + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x0007>; + opp-peak-kBps =3D <3264000>; + opp-suspend; + }; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <6528000>; + }; + + opp-665600000 { + opp-hz =3D /bits/ 64 <665600000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <10649600>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x001F>; + opp-peak-kBps =3D <12800000>; + }; + + opp-1065600000 { + opp-hz =3D /bits/ 64 <1065600000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <17049600>; + }; + + opp-1331200000 { + opp-hz =3D /bits/ 64 <1331200000>; + opp-supported-hw =3D <0x0003>; + opp-peak-kBps =3D <21299200>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-supported-hw =3D <0x0007>; + opp-peak-kBps =3D <25600000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index 2fcc7a28690f7100d49e8b93c4fb77de7947b002..f2961c9e12db1cf91254b753897= 79955f2a0956d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -9,6 +9,8 @@ #include #include =20 +#include "tegra210-peripherals-opp.dtsi" + / { compatible =3D "nvidia,tegra210"; interrupt-parent =3D <&lic>; @@ -516,6 +518,9 @@ actmon@6000c800 { clock-names =3D "actmon", "emc"; resets =3D <&tegra_car 119>; reset-names =3D "actmon"; + operating-points-v2 =3D <&emc_bw_dfs_opp_table>; + interconnects =3D <&mc TEGRA210_MC_MPCORER &emc>; + interconnect-names =3D "cpu-read"; #cooling-cells =3D <2>; }; =20 @@ -1024,6 +1029,8 @@ emc: external-memory-controller@7001b000 { clock-names =3D "emc"; interrupts =3D ; nvidia,memory-controller =3D <&mc>; + operating-points-v2 =3D <&emc_icc_dvfs_opp_table>; + #interconnect-cells =3D <0>; #cooling-cells =3D <2>; }; --=20 2.50.1