From nobody Fri Oct 3 08:50:39 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 691A2320CB6 for ; Wed, 3 Sep 2025 18:51:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925501; cv=none; b=cB5usAYb74QEY8ew5kwk6F3GJW+W7EKEsh4BASo08KPtEMm08PUvWzuZqdcY90akgIik8D2xRFusyIf/i+NzgxCldr18xIB6Z9qmIDwSG5ueIJFCqIp/znvwiwXiRAgE1d9+tY2HFhxbmXzgUQktmDcE1e1ySW8MoBOCqrJwqEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925501; c=relaxed/simple; bh=P16GWZ5xMUMdCjEEjMnPh5ZFPrJLj34FT+iME57x8eU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s2QG4BEQfQ7y3FU+aPHOGaTbt40EP69rKeB0OdZa52AduLzI3S7BAocgy6LBOohmeTdWR4/+Yr4uQvYnydfLiWL7EHLbpvyS1n7DFzB0kce/3lCF2jAy5t1XdDvYnWJuG/g16VBBnKF6cSkBz9SKGpHechOsnahL6Q9+Qi4Q954= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=BkUYsbGt; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="BkUYsbGt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756925497; bh=P16GWZ5xMUMdCjEEjMnPh5ZFPrJLj34FT+iME57x8eU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BkUYsbGtp2rYAc5YwKpVGlVaA4k2enidF4Dus0SXDGCsPTckpmlFMh/SONVST9sMj 4KwU51jIXDp1ZcWLj46Q193fcwjNjMdabJht3Xa397oS9EPV+2EAlt46twm98wUCop SPPgROV/cn/hwHHOLZowE5vJStTxB1rrpmokAMZaAnyQnW5zJmFokx//AyVpeVnp5p HQs1olCnaPle8XOkhINAohc2B1ZY6JAcXyTvTVNbMilejpbPUu40xRBjdp8UXLB39d VNfxdBgLN/AF7UVKUuDKwJzN22s3UHOTI0EtcLlRy5DAo7Z+IJDSmgsaHl+Q2ASRLs QaPolybIPY8vw== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 7F62317E129F; Wed, 3 Sep 2025 20:51:37 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:00 +0300 Subject: [PATCH v4 2/6] drm/bridge: dw-hdmi-qp: Fixup timer base setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-2-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate that shall be provided by the platform driver. Otherwise fallback to the vendor default. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 12 +++++++++--- include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index fc98953672b6fb388d05201e280d24b8f214498a..4ba7b339eff62592aa748429a3b= fca82494679d1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -161,6 +161,7 @@ struct dw_hdmi_qp { void *data; } phy; =20 + unsigned long ref_clk_rate; struct regmap *regm; =20 unsigned long tmds_char_rate; @@ -1210,13 +1211,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *h= dmi) { dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); =20 /* Software reset */ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); - dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); - dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); =20 /* Clear DONE and ERROR interrupts */ @@ -1262,6 +1261,13 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->phy.ops =3D plat_data->phy_ops; hdmi->phy.data =3D plat_data->phy_data; =20 + if (plat_data->ref_clk_rate) { + hdmi->ref_clk_rate =3D plat_data->ref_clk_rate; + } else { + hdmi->ref_clk_rate =3D 428571429; + dev_warn(dev, "Set ref_clk_rate to vendor default\n"); + } + dw_hdmi_qp_init_hw(hdmi); =20 ret =3D devm_request_threaded_irq(dev, plat_data->main_irq, diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce= 9eab8695e26b5 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { void *phy_data; int main_irq; int cec_irq; + unsigned long ref_clk_rate; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.51.0