From nobody Fri Oct 3 07:44:22 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A861031AF2A for ; Wed, 3 Sep 2025 18:51:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925500; cv=none; b=AkD2v6rJEPDASkgIvmjHOpjfs3CK3nHex4jGaZUnMd2KdXK9zNaj2tbOA3yQqWnrV7G2eu603mcqLdt1vJwnFYlBZTvTIThIZ/i2Svh/hDoC6xqs4UFm2cfUxZSG0RJjHPIhiHupo4KSbJApT0MmhAz93B9EUfEjZVQPFbidcnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925500; c=relaxed/simple; bh=JTakCWBMnue0yJE0wueanLWL2rtrs+mBYoySJTNPnOo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hWEoEg/cx48v//lgF1JFStJgSf++Bw0LEBtXg0SeCPfHMNKwxIluTjzB3OlR0n2qrXCV4Zoj92shouC09vnXhzmEbUjzgoi2PtygyQwxjnv2B5r2hN/aVgv7LSlNuDjMkbjlN3Db3beALVjlERE6kH0+lSjxHIk5LT/h5gyqfIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ImZ5dnc2; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ImZ5dnc2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756925496; bh=JTakCWBMnue0yJE0wueanLWL2rtrs+mBYoySJTNPnOo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ImZ5dnc2yHbitEfz+qX+gR2XfaIEm0n1tfswn/OSD9EMLVcK30K4e4gnqxU/ZXpHQ VYAMSeAwCY/628KsJ7rHVDoPbsfj1xFrgCw2r9U3z2K3SuRzpcbcua0o21tApWIDgQ ujRi28d2bCpqVI7vg3T2q+2Oa6IrwOB0/2OqhyqmLvkB5yZQysMIpj/z84Klkf7h+I qUknfdvH9CZxnmQF7znZ74Uq87UpdPHv8Vyk5J+a66YeWrdZIAuD9oQy4AzhtjvoJV 9n5Lf4l/9XoLr+yPp3wVXOZua0x220NWuuyu027ZoLnVUFeWANc49vPxuRk+FU23uA Ynhyn4f3lSv1Q== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id B0B9B17E0FAD; Wed, 3 Sep 2025 20:51:36 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:50:59 +0300 Subject: [PATCH v4 1/6] drm/bridge: dw-hdmi-qp: Add CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-1-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Algea Cao , Derek Foreman X-Mailer: b4 0.14.2 Add support for the CEC interface of the Synopsys DesignWare HDMI QP TX controller. This is based on the downstream implementation, but rewritten on top of the CEC helpers added recently to the DRM HDMI connector framework. Also note struct dw_hdmi_qp_plat_data has been extended to include the CEC IRQ number to be provided by the platform driver. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Co-developed-by: Derek Foreman Signed-off-by: Derek Foreman Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/Kconfig | 8 + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 212 +++++++++++++++++++++++= ++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 14 ++ include/drm/bridge/dw_hdmi_qp.h | 1 + 4 files changed, 235 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/brid= ge/synopsys/Kconfig index 2c5e532410de9ef024f13d44502c4fcb5f36ba66..a46df7583bcf907a38e34a1babb= 02ce8c8be69be 100644 --- a/drivers/gpu/drm/bridge/synopsys/Kconfig +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig @@ -61,6 +61,14 @@ config DRM_DW_HDMI_QP select DRM_KMS_HELPER select REGMAP_MMIO =20 +config DRM_DW_HDMI_QP_CEC + bool "Synopsis Designware QP CEC interface" + depends on DRM_DW_HDMI_QP + select DRM_DISPLAY_HDMI_CEC_HELPER + help + Support the CEC interface which is part of the Synopsys + Designware HDMI QP block. + config DRM_DW_MIPI_DSI tristate select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 39332c57f2c54296f39e27612544f4fbf923863f..fc98953672b6fb388d05201e280= d24b8f214498a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -18,6 +18,7 @@ =20 #include #include +#include #include #include #include @@ -26,6 +27,8 @@ #include #include =20 +#include + #include =20 #include "dw-hdmi-qp.h" @@ -131,12 +134,28 @@ struct dw_hdmi_qp_i2c { bool is_segment; }; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +struct dw_hdmi_qp_cec { + struct drm_connector *connector; + int irq; + u32 addresses; + struct cec_msg rx_msg; + u8 tx_status; + bool tx_done; + bool rx_done; +}; +#endif + struct dw_hdmi_qp { struct drm_bridge bridge; =20 struct device *dev; struct dw_hdmi_qp_i2c *i2c; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + struct dw_hdmi_qp_cec *cec; +#endif + struct { const struct dw_hdmi_qp_phy_ops *ops; void *data; @@ -965,6 +984,179 @@ static int dw_hdmi_qp_bridge_write_infoframe(struct d= rm_bridge *bridge, } } =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + irqreturn_t ret =3D IRQ_HANDLED; + u32 stat; + + stat =3D dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); + if (stat =3D=3D 0) + return IRQ_NONE; + + dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); + + if (stat & CEC_STAT_LINE_ERR) { + cec->tx_status =3D CEC_TX_STATUS_ERROR; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { + cec->tx_status =3D CEC_TX_STATUS_OK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_NACK) { + cec->tx_status =3D CEC_TX_STATUS_NACK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { + unsigned int len, i, val; + + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); + len =3D (val & 0xf) + 1; + + if (len > sizeof(cec->rx_msg.msg)) + len =3D sizeof(cec->rx_msg.msg); + + for (i =3D 0; i < 4; i++) { + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); + cec->rx_msg.msg[i * 4] =3D val & 0xff; + cec->rx_msg.msg[i * 4 + 1] =3D (val >> 8) & 0xff; + cec->rx_msg.msg[i * 4 + 2] =3D (val >> 16) & 0xff; + cec->rx_msg.msg[i * 4 + 3] =3D (val >> 24) & 0xff; + } + + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + cec->rx_msg.len =3D len; + cec->rx_done =3D true; + + ret =3D IRQ_WAKE_THREAD; + } + + return ret; +} + +static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (cec->tx_done) { + cec->tx_done =3D false; + drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, + cec->tx_status); + } + + if (cec->rx_done) { + cec->rx_done =3D false; + drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); + } + + return IRQ_HANDLED; +} + +static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + cec->connector =3D connector; + + dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + + return devm_request_threaded_irq(hdmi->dev, cec->irq, + dw_hdmi_qp_cec_hardirq, + dw_hdmi_qp_cec_thread, IRQF_SHARED, + dev_name(hdmi->dev), hdmi); +} + +static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_a= ddr) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (logical_addr =3D=3D CEC_LOG_ADDR_INVALID) + cec->addresses =3D 0; + else + cec->addresses |=3D BIT(logical_addr) | CEC_ADDR_BROADCAST; + + dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); + + return 0; +} + +static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int irqs; + u32 swdisable; + + if (!enable) { + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable | CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + } else { + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable & ~CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); + + irqs =3D CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | + CEC_STAT_DONE; + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); + } + + return 0; +} + +static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int i; + u32 val; + + for (i =3D 0; i < msg->len; i++) { + if (!(i % 4)) + val =3D msg->msg[i]; + if ((i % 4) =3D=3D 1) + val |=3D msg->msg[i] << 8; + if ((i % 4) =3D=3D 2) + val |=3D msg->msg[i] << 16; + if ((i % 4) =3D=3D 3) + val |=3D msg->msg[i] << 24; + + if (i =3D=3D (msg->len - 1) || (i % 4) =3D=3D 3) + dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); + } + + dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); + + return 0; +} +#else +#define dw_hdmi_qp_cec_init NULL +#define dw_hdmi_qp_cec_enable NULL +#define dw_hdmi_qp_cec_log_addr NULL +#define dw_hdmi_qp_cec_transmit NULL +#endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ + static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -979,6 +1171,10 @@ static const struct drm_bridge_funcs dw_hdmi_qp_bridg= e_funcs =3D { .hdmi_audio_startup =3D dw_hdmi_qp_audio_enable, .hdmi_audio_shutdown =3D dw_hdmi_qp_audio_disable, .hdmi_audio_prepare =3D dw_hdmi_qp_audio_prepare, + .hdmi_cec_init =3D dw_hdmi_qp_cec_init, + .hdmi_cec_enable =3D dw_hdmi_qp_cec_enable, + .hdmi_cec_log_addr =3D dw_hdmi_qp_cec_log_addr, + .hdmi_cec_transmit =3D dw_hdmi_qp_cec_transmit, }; =20 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) @@ -1093,6 +1289,22 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->bridge.hdmi_audio_dev =3D dev; hdmi->bridge.hdmi_audio_dai_port =3D 1; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + if (plat_data->cec_irq) { + hdmi->bridge.ops |=3D DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; + hdmi->bridge.hdmi_cec_dev =3D dev; + hdmi->bridge.hdmi_cec_adapter_name =3D dev_name(dev); + + hdmi->cec =3D devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); + if (!hdmi->cec) + return ERR_PTR(-ENOMEM); + + hdmi->cec->irq =3D plat_data->cec_irq; + } else { + dev_warn(dev, "Disabled CEC support due to missing IRQ\n"); + } +#endif + ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.h index 72987e6c468928f2b998099697a6f32726411557..91a15f82e32acc32eef58f11ec5= ca958337ebb9a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h @@ -488,9 +488,23 @@ #define AUDPKT_VBIT_OVR0 0xf24 /* CEC Registers */ #define CEC_TX_CONTROL 0x1000 +#define CEC_CTRL_CLEAR BIT(0) +#define CEC_CTRL_START BIT(0) #define CEC_STATUS 0x1004 +#define CEC_STAT_DONE BIT(0) +#define CEC_STAT_NACK BIT(1) +#define CEC_STAT_ARBLOST BIT(2) +#define CEC_STAT_LINE_ERR BIT(3) +#define CEC_STAT_RETRANS_FAIL BIT(4) +#define CEC_STAT_DISCARD BIT(5) +#define CEC_STAT_TX_BUSY BIT(8) +#define CEC_STAT_RX_BUSY BIT(9) +#define CEC_STAT_DRIVE_ERR BIT(10) +#define CEC_STAT_EOM BIT(11) +#define CEC_STAT_NOTIFY_ERR BIT(12) #define CEC_CONFIG 0x1008 #define CEC_ADDR 0x100c +#define CEC_ADDR_BROADCAST BIT(15) #define CEC_TX_COUNT 0x1020 #define CEC_TX_DATA3_0 0x1024 #define CEC_TX_DATA7_4 0x1028 diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index e9be6d507ad9cdc55f5c7d6d3ef37eba41f1ce74..b4a9b739734ec7b67013b683fe6= 017551aa19172 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -23,6 +23,7 @@ struct dw_hdmi_qp_plat_data { const struct dw_hdmi_qp_phy_ops *phy_ops; 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Wed, 3 Sep 2025 20:51:37 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:00 +0300 Subject: [PATCH v4 2/6] drm/bridge: dw-hdmi-qp: Fixup timer base setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-2-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate that shall be provided by the platform driver. Otherwise fallback to the vendor default. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 12 +++++++++--- include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index fc98953672b6fb388d05201e280d24b8f214498a..4ba7b339eff62592aa748429a3b= fca82494679d1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -161,6 +161,7 @@ struct dw_hdmi_qp { void *data; } phy; =20 + unsigned long ref_clk_rate; struct regmap *regm; =20 unsigned long tmds_char_rate; @@ -1210,13 +1211,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *h= dmi) { dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); =20 /* Software reset */ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); - dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); - dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); =20 /* Clear DONE and ERROR interrupts */ @@ -1262,6 +1261,13 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->phy.ops =3D plat_data->phy_ops; hdmi->phy.data =3D plat_data->phy_data; =20 + if (plat_data->ref_clk_rate) { + hdmi->ref_clk_rate =3D plat_data->ref_clk_rate; + } else { + hdmi->ref_clk_rate =3D 428571429; + dev_warn(dev, "Set ref_clk_rate to vendor default\n"); + } + dw_hdmi_qp_init_hw(hdmi); =20 ret =3D devm_request_threaded_irq(dev, plat_data->main_irq, diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce= 9eab8695e26b5 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { void *phy_data; int main_irq; int cec_irq; + unsigned long ref_clk_rate; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.51.0 From nobody Fri Oct 3 07:44:22 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BD2B368097 for ; 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Wed, 3 Sep 2025 20:51:38 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:01 +0300 Subject: [PATCH v4 3/6] drm/rockchip: dw_hdmi_qp: Improve error handling with dev_err_probe() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-3-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.2 The error handling in dw_hdmi_qp_rockchip_bind() is quite inconsistent, i.e. in some cases the error code is not included in the message, while in some other cases there is no check for -EPROBE_DEFER. Since this is part of the probe path, address the aforementioned issues by switching to dev_err_probe(), which also reduces the code a bit. Reviewed-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 62 ++++++++++------------= ---- 1 file changed, 24 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index ed6e8f036f4b3d76425725c130394cedf039acd0..a775d89f20fc20e9103ecbac0dc= f3db10ba9984f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -455,10 +455,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, return -ENODEV; =20 if (!cfg->ctrl_ops || !cfg->ctrl_ops->io_init || - !cfg->ctrl_ops->irq_callback || !cfg->ctrl_ops->hardirq_callback) { - dev_err(dev, "Missing platform ctrl ops\n"); - return -ENODEV; - } + !cfg->ctrl_ops->irq_callback || !cfg->ctrl_ops->hardirq_callback) + return dev_err_probe(dev, -ENODEV, "Missing platform ctrl ops\n"); =20 hdmi->ctrl_ops =3D cfg->ctrl_ops; hdmi->dev =3D &pdev->dev; @@ -471,10 +469,9 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, break; } } - if (hdmi->port_id < 0) { - dev_err(hdmi->dev, "Failed to match HDMI port ID\n"); - return hdmi->port_id; - } + if (hdmi->port_id < 0) + return dev_err_probe(hdmi->dev, hdmi->port_id, + "Failed to match HDMI port ID\n"); =20 plat_data.phy_ops =3D cfg->phy_ops; plat_data.phy_data =3D hdmi; @@ -495,39 +492,30 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, =20 hdmi->regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); - if (IS_ERR(hdmi->regmap)) { - dev_err(hdmi->dev, "Unable to get rockchip,grf\n"); - return PTR_ERR(hdmi->regmap); - } + if (IS_ERR(hdmi->regmap)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->regmap), + "Unable to get rockchip,grf\n"); =20 hdmi->vo_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo-grf"); - if (IS_ERR(hdmi->vo_regmap)) { - dev_err(hdmi->dev, "Unable to get rockchip,vo-grf\n"); - return PTR_ERR(hdmi->vo_regmap); - } + if (IS_ERR(hdmi->vo_regmap)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->vo_regmap), + "Unable to get rockchip,vo-grf\n"); =20 ret =3D devm_clk_bulk_get_all_enabled(hdmi->dev, &clks); - if (ret < 0) { - dev_err(hdmi->dev, "Failed to get clocks: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n"); =20 hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); - if (IS_ERR(hdmi->enable_gpio)) { - ret =3D PTR_ERR(hdmi->enable_gpio); - dev_err(hdmi->dev, "Failed to request enable GPIO: %d\n", ret); - return ret; - } + if (IS_ERR(hdmi->enable_gpio)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->enable_gpio), + "Failed to request enable GPIO\n"); =20 hdmi->phy =3D devm_of_phy_get_by_index(dev, dev->of_node, 0); - if (IS_ERR(hdmi->phy)) { - ret =3D PTR_ERR(hdmi->phy); - if (ret !=3D -EPROBE_DEFER) - dev_err(hdmi->dev, "failed to get phy: %d\n", ret); - return ret; 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Wed, 3 Sep 2025 20:51:38 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:02 +0300 Subject: [PATCH v4 4/6] drm/rockchip: dw_hdmi_qp: Provide CEC IRQ in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-4-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.2 In order to support the CEC interface of the DesignWare HDMI QP IP block, setup platform data to include the required IRQ number. Reviewed-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index a775d89f20fc20e9103ecbac0dcf3db10ba9984f..9191a74a568fb38c2b2ff7ead1e= 703b3af9addc9 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -525,6 +525,10 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (plat_data.main_irq < 0) return plat_data.main_irq; =20 + plat_data.cec_irq =3D platform_get_irq_byname(pdev, "cec"); + if (plat_data.cec_irq < 0) + return plat_data.cec_irq; + irq =3D platform_get_irq_byname(pdev, "hpd"); if (irq < 0) return irq; --=20 2.51.0 From nobody Fri Oct 3 07:44:22 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4A8E36932A for ; Wed, 3 Sep 2025 18:51:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925503; cv=none; b=Z5CfXoVOOXo5V9skFF3LyBEJkxohSjC61niCWWz2NQBtvCTI8fjwR5mGbpkVEkKqOqi6UT6oTsakIGtDga5hOb5tL4kUMPsmq4zwrsgCyL9DZbSm4ABqxCnBUyJbeUP5wgjQTw86z5MMdLOWVnuVGNdgdPMuq1KrlTBbHliz7F8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756925503; c=relaxed/simple; bh=8Z8mjCF+FKwKBL8hPeIwVkjMamf3nUzQplfzpBne/CE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qJfpzBEKm25Ky3Iwl9ZOu9X9UCh91+Loa89mFuv2PF1zHagO5SRvp9vPjyQ/QMZPRk5o3cqzEwEcFlpChltn8KVLlI0O2Wb2zd8mFvyj7jnO6wjXfssbDJW8rY5tg5Wk2qjgMmZQQt48d25ZNyxo+V626rodp8+mAhjaM8CQwwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ogaUlsET; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ogaUlsET" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756925499; bh=8Z8mjCF+FKwKBL8hPeIwVkjMamf3nUzQplfzpBne/CE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ogaUlsETyB/vRASIhDvfh/x6+jJBP5hPQGTx0DYVvQ4mRIrm4jU0gH60WpvZDUIZq OF50cIb234o8oz6cbEcqPVEqOPjDWwevlElQJo08aqFRHk1AwiT3XiCWCpDcoJNsYP /6eRjbTnxuZjm1KrtpjPMpaZnhWthAGc0lY+ZPzlNzRCaWbt0QxtbEstJOXpd/meap aJ7n4OW9YuWM5aQlsWFqa+Si3sg631K3aMNbNerqtU71l6y2gUho4lg+q5MLUODIhM a3IDkZ+4NizZxXal1/p466MADhZilVaQMKvPjeIXE4fQ0wVbD5WNIwZIPFUQIv5pHW UnNjTWtJKqdxQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id B84AB17E1382; Wed, 3 Sep 2025 20:51:39 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:03 +0300 Subject: [PATCH v4 5/6] drm/rockchip: dw_hdmi_qp: Provide ref clock rate in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-5-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Stone X-Mailer: b4 0.14.2 In order to support correct initialization of the timer base in the HDMI QP IP block, setup platform data to include the required reference clock rate. While at it, ensure plat_data is zero-initialized in dw_hdmi_qp_rockchip_bind(). Reviewed-by: Daniel Stone Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 9191a74a568fb38c2b2ff7ead1e703b3af9addc9..931343b072adc05877db9ae867e= 31a3cd1134e6c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -429,14 +429,15 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, void *data) { struct platform_device *pdev =3D to_platform_device(dev); + struct dw_hdmi_qp_plat_data plat_data =3D {}; const struct rockchip_hdmi_qp_cfg *cfg; - struct dw_hdmi_qp_plat_data plat_data; struct drm_device *drm =3D data; struct drm_connector *connector; struct drm_encoder *encoder; struct rockchip_hdmi_qp *hdmi; struct resource *res; struct clk_bulk_data *clks; + struct clk *ref_clk; int ret, irq, i; =20 if (!pdev->dev.of_node) @@ -506,6 +507,14 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (ret < 0) return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n"); =20 + ref_clk =3D clk_get(hdmi->dev, "ref"); + if (IS_ERR(ref_clk)) + return dev_err_probe(hdmi->dev, PTR_ERR(ref_clk), + "Failed to get ref clock\n"); + + plat_data.ref_clk_rate =3D clk_get_rate(ref_clk); + clk_put(ref_clk); + hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); if (IS_ERR(hdmi->enable_gpio)) --=20 2.51.0 From nobody Fri Oct 3 07:44:22 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9BF36933B for ; Wed, 3 Sep 2025 18:51:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Wed, 3 Sep 2025 20:51:40 +0200 (CEST) From: Cristian Ciocaltea Date: Wed, 03 Sep 2025 21:51:04 +0300 Subject: [PATCH v4 6/6] arm64: defconfig: Enable DW HDMI QP CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-rk3588-hdmi-cec-v4-6-fa25163c4b08@collabora.com> References: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> In-Reply-To: <20250903-rk3588-hdmi-cec-v4-0-fa25163c4b08@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Enable support for the CEC interface of the Synopsys DesignWare HDMI QP IP block. This is used by all boards based on RK3588 & RK3576 SoCs. Signed-off-by: Cristian Ciocaltea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index acb6807d3461384929e84f4c939fcd00c4b509ae..346ef79c1ddd0a317f0b9a8056c= 680c29a4e0baf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -966,6 +966,7 @@ CONFIG_DRM_CDNS_MHDP8546=3Dm CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm +CONFIG_DRM_DW_HDMI_QP_CEC=3Dy CONFIG_DRM_IMX_DCSS=3Dm CONFIG_DRM_V3D=3Dm CONFIG_DRM_VC4=3Dm --=20 2.51.0