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Wed, 03 Sep 2025 01:00:24 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:08 +0200 Subject: [PATCH 04/12] gpio: blzp1600: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-4-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5038; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=F68ayGcj6tukamf2TyWlBtvd60fsol9kVvTSarVzm3w=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBot/WRHkgVPwU1jO6DA6F5jZ9sztCHx1zF51/sn JLDQOuTfCeJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaLf1kQAKCRARpy6gFHHX chBRD/9PYRGoH3ZtNfKbqvOXMxEhMI+o65yuL3AwbTwEpq4lypxB8b3XWDAwhJLBjQXZjGG47v7 rVyij2wcwFSsh68pJoARwoVsFmW60fSwm8Pdv4pvkSCM3GsgB/JqBoQlH9dET6Z7CYlRYDTdlXd vUOtLGYjdIMR852oqlgIDjLOPlMqj9nkCstPsc0qf4HDUcUfeyrlYtsQweG8sJFZVHuj7T8okuJ P6fSl1aJhBU33TPwu/IdOoMQBbaHqDGisjim3gIpOvpIKw86F/3UeWsESd6+50jCNDl16kdS5PW IsJ/QaVFuY8/3agB8KeOH9rvcjNVL4FXVOQbW6jiSMF7OXBLEjnQnuLkJLm5WTe3ZDaEqXjhLo8 aiRnVEs4dAUtPFCtAfDiDPOsOnLTHrNYF+2w8Ul++kmhlzOF2/mQpjkgRvuTbhXQzgE/y0GgqhX tAaK82tybg8qE+JSbpw1ckq9gOccyiN+MzhSk4rCfaI9opC9odeqzfjBlPRrJIpqUyn+WdDj8q4 lUuqszf5aoD/s64KdSEJ5OYTnVEqkzdyFXCpkD55NJ0TnzPr0MoqvHTpeS/6II7egFMB7O+esSM XCkaVN65+5/e79zJXTElrA72n/lp5PMHxIK1sprqBrfOm1P9q1nr98SLLh38znf3J4MqiSJYtYI 2ZuBKYegz9uas2w== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-blzp1600.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-blzp1600.c b/drivers/gpio/gpio-blzp1600.c index 055cb296ae54758cdc206d36aa1df7b8377d32ec..bfb35d59fa561c43889b186fdfb= 8d9184b750a53 100644 --- a/drivers/gpio/gpio-blzp1600.c +++ b/drivers/gpio/gpio-blzp1600.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -36,7 +37,7 @@ =20 struct blzp1600_gpio { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; int irq; }; =20 @@ -76,7 +77,7 @@ static void blzp1600_gpio_irq_mask(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1); } =20 @@ -84,7 +85,7 @@ static void blzp1600_gpio_irq_unmask(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0); } =20 @@ -99,9 +100,9 @@ static void blzp1600_gpio_irq_enable(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d)); + gpiochip_enable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0); blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1); } @@ -110,9 +111,9 @@ static void blzp1600_gpio_irq_disable(struct irq_data *= d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0); - gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d)); + gpiochip_disable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); } =20 static int blzp1600_gpio_irq_set_type(struct irq_data *d, u32 type) @@ -121,7 +122,7 @@ static int blzp1600_gpio_irq_set_type(struct irq_data *= d, u32 type) u32 edge_level, single_both, fall_rise; int mask =3D BIT(d->hwirq); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); edge_level =3D blzp1600_gpio_read(chip, GPIO_IS_REG); single_both =3D blzp1600_gpio_read(chip, GPIO_IBE_REG); fall_rise =3D blzp1600_gpio_read(chip, GPIO_IEV_REG); @@ -186,8 +187,8 @@ static void blzp1600_gpio_irqhandler(struct irq_desc *d= esc) =20 chained_irq_enter(irqchip, desc); irq_status =3D blzp1600_gpio_read(gpio, GPIO_RIS_REG); - for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio) - generic_handle_domain_irq(gpio->gc.irq.domain, hwirq); + for_each_set_bit(hwirq, &irq_status, gpio->gen_gc.gc.ngpio) + generic_handle_domain_irq(gpio->gen_gc.gc.irq.domain, hwirq); =20 chained_irq_exit(irqchip, desc); } @@ -197,7 +198,7 @@ static int blzp1600_gpio_set_debounce(struct gpio_chip = *gc, unsigned int offset, { struct blzp1600_gpio *chip =3D gpiochip_get_data(gc); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce); =20 return 0; @@ -216,6 +217,7 @@ static int blzp1600_gpio_set_config(struct gpio_chip *g= c, unsigned int offset, u =20 static int blzp1600_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct blzp1600_gpio *chip; struct gpio_chip *gc; int ret; @@ -228,14 +230,21 @@ static int blzp1600_gpio_probe(struct platform_device= *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); =20 - ret =3D bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG, - chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG, - chip->base + GPIO_DIR_REG, NULL, 0); + config =3D (typeof(config)){ + .dev =3D &pdev->dev, + .sz =3D 4, + .dat =3D chip->base + GPIO_IDATA_REG, + .set =3D chip->base + GPIO_SET_REG, + .clr =3D chip->base + GPIO_CLR_REG, + .dirout =3D chip->base + GPIO_DIR_REG, + }; + + ret =3D gpio_generic_chip_init(&chip->gen_gc, &config); if (ret) return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n= "); =20 /* configure the gpio chip */ - gc =3D &chip->gc; + gc =3D &chip->gen_gc.gc; gc->set_config =3D blzp1600_gpio_set_config; =20 if (device_property_present(&pdev->dev, "interrupt-controller")) { --=20 2.48.1