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Wed, 03 Sep 2025 01:00:21 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:06 +0200 Subject: [PATCH 02/12] gpio: ixp4xx: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-2-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5144; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=52EZXtNYov0BPLgttyxaJIp6rvW0YbePoZxCVvveYbw=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBot/WQe9Je1QrsE3U9X8Asr57GXatF/xD2gPO3D 13D3NWIwNuJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaLf1kAAKCRARpy6gFHHX cuxuD/9pktxCxNM7u1Czg04I8wRpvbWv2USp2CvXmd6W6wJ6bWt+JGRLYmYMta05xJnv2s68Ha5 kgDzRGqsja0QynNa2DPQQh4oLhfoJMrefmnEmj0e/9T6MfJ7o+XgwYmV6nZLcHohdMf9NGgkIv1 34TFqylt2rt/uSavy2mGDjgKyFDoi1eetiSCKDilF1mFPJ6KPrVrC5zFToU9JbcZu6XKeiuz5fC PgpHhwh/ZHA0a+/kk34wNf4h0NebQRFE1sW04hHee8M2XBux8+TLmWnT0jdKjyRT/TULiGRbORv Msc7SDUCFWsAxsX1caajyKP5EXEeLjh+NDFOUw8SaCvNgtHQcUZVQrjBZUFf+195OppF1+GPjh+ YUO2qJZmmDIj5zzppuRJKMqp8xjWi2H5tRIU2aoILn0jU8thEvSMpOWOcg0tilgLW/UQsc6rLjV xD7mhj5Eu1yKRsvavLw1KOEekyEqClE9VIl8rNhIa6grKNsP9//6laoJajvOR4ghk+4rs8wwi9f 1AovvWbfIWFvkUoF8+9bAztsacjXM9HUijDLGpSmbOY8DmHQiQrg1QOJUpoe4WtjWgdgE4klpWl Pi+eflQ0Jsmz9B7e7g6w6PFso92KVLVg6CRmixZhPtAXMvLGLeqWClIvA0l5BrotMIx7ehI9snN T3yYx0Gxa+8tokw== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-ixp4xx.c | 70 ++++++++++++++++++++++++------------------= ---- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index 28a8a6a8f05feec4188467693591e36dbf04ccdc..0cf10d0ba16ef7f45ac114c3446= 8bc263442ccca 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -53,14 +54,14 @@ =20 /** * struct ixp4xx_gpio - IXP4 GPIO state container + * @chip: generic GPIO chip for this instance * @dev: containing device for this instance - * @gc: gpiochip for this instance * @base: remapped I/O-memory base * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, * 0: level triggered */ struct ixp4xx_gpio { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct device *dev; void __iomem *base; unsigned long long irq_edge; @@ -100,7 +101,6 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d,= unsigned int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ixp4xx_gpio *g =3D gpiochip_get_data(gc); int line =3D d->hwirq; - unsigned long flags; u32 int_style; u32 int_reg; u32 val; @@ -144,26 +144,24 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *= d, unsigned int type) int_reg =3D IXP4XX_REG_GPIT1; } =20 - raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &g->chip) { + /* Clear the style for the appropriate pin */ + val =3D __raw_readl(g->base + int_reg); + val &=3D ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); + __raw_writel(val, g->base + int_reg); =20 - /* Clear the style for the appropriate pin */ - val =3D __raw_readl(g->base + int_reg); - val &=3D ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); - __raw_writel(val, g->base + int_reg); + __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); =20 - __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); + /* Set the new style */ + val =3D __raw_readl(g->base + int_reg); + val |=3D (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); + __raw_writel(val, g->base + int_reg); =20 - /* Set the new style */ - val =3D __raw_readl(g->base + int_reg); - val |=3D (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); - __raw_writel(val, g->base + int_reg); - - /* Force-configure this line as an input */ - val =3D __raw_readl(g->base + IXP4XX_REG_GPOE); - val |=3D BIT(d->hwirq); - __raw_writel(val, g->base + IXP4XX_REG_GPOE); - - raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); + /* Force-configure this line as an input */ + val =3D __raw_readl(g->base + IXP4XX_REG_GPOE); + val |=3D BIT(d->hwirq); + __raw_writel(val, g->base + IXP4XX_REG_GPOE); + } =20 /* This parent only accept level high (asserted) */ return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); @@ -206,6 +204,7 @@ static int ixp4xx_gpio_child_to_parent_hwirq(struct gpi= o_chip *gc, =20 static int ixp4xx_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; unsigned long flags; struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -295,30 +294,33 @@ static int ixp4xx_gpio_probe(struct platform_device *= pdev) flags =3D 0; #endif =20 + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D g->base + IXP4XX_REG_GPIN, + .set =3D g->base + IXP4XX_REG_GPOUT, + .dirin =3D g->base + IXP4XX_REG_GPOE, + .flags =3D flags, + }; + /* Populate and register gpio chip */ - ret =3D bgpio_init(&g->gc, dev, 4, - g->base + IXP4XX_REG_GPIN, - g->base + IXP4XX_REG_GPOUT, - NULL, - NULL, - g->base + IXP4XX_REG_GPOE, - flags); + ret =3D gpio_generic_chip_init(&g->chip, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; } - g->gc.ngpio =3D 16; - g->gc.label =3D "IXP4XX_GPIO_CHIP"; + g->chip.gc.ngpio =3D 16; + g->chip.gc.label =3D "IXP4XX_GPIO_CHIP"; /* * TODO: when we have migrated to device tree and all GPIOs * are fetched using phandles, set this to -1 to get rid of * the fixed gpiochip base. */ - g->gc.base =3D 0; - g->gc.parent =3D &pdev->dev; - g->gc.owner =3D THIS_MODULE; + g->chip.gc.base =3D 0; + g->chip.gc.parent =3D &pdev->dev; + g->chip.gc.owner =3D THIS_MODULE; =20 - girq =3D &g->gc.irq; + girq =3D &g->chip.gc.irq; gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip); girq->fwnode =3D dev_fwnode(dev); girq->parent_domain =3D parent; @@ -326,7 +328,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pd= ev) girq->handler =3D handle_bad_irq; girq->default_type =3D IRQ_TYPE_NONE; =20 - ret =3D devm_gpiochip_add_data(dev, &g->gc, g); + ret =3D devm_gpiochip_add_data(dev, &g->chip.gc, g); if (ret) { dev_err(dev, "failed to add SoC gpiochip\n"); return ret; --=20 2.48.1