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Wed, 03 Sep 2025 01:00:34 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:16 +0200 Subject: [PATCH 12/12] gpio: mlxbf3: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-12-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7400; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=hreJZv0kQOpgsrXN7wXnSdTeNguQrIV3lN+FwAv5MqE=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBot/WT2EPw3eqpxhBtsDB4pgWSrqiehVVLjbIrV DhdGgmFt1qJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaLf1kwAKCRARpy6gFHHX ciLxD/9R8A7ngJXfHhBrONYbDrf3Hoj7lOUBXZBkWMAngCDlXZS7YvxLp+xIvuAKlB8fWw3kPnD v7Ac2NUlGPjM4xeXp2zaAYCWGwLUC41NEywxjZ2/6rGN0UUnMqrYly/Zrlr8lXCBhTqyVx5lJwA GDn8uY42SkEvkurNVhy6kLR2Hf5um0eav1hKPFIwcvYgfVkYwaEMKgyDBlOW6UaWBZoeJ72SUD8 RUBwroocq6322Hq/E8kosbZ0agHR7+CHcQY9Elx2tbLXUNhij7lRjM2cFj6sDZrFXqU1iw77ehz L6xumXUAhAhZa3yBOuyzOTi1o1oqVreoQ4l05EPDLLcIe5+YAvB6nBUMJCo8FKteDOM5SsEjlbF D20+uHchK62MPzFb/9ZN1hULtTUn/J8u3vdrXDaF7hYoOyNEMCS8LLXDvDQhR4htup9pF4wY+Aj Qu71MwrqHFlQwLM+fQARgQSgJi+INGI+L0Q5isYK6eg7z7tVR9LncptxfTgBWkQUz+W9Pf5IO9W dH0DyaSWhZs9msSY19u6M8Yc2N6XvBqERFuixL4dHtMY9DyjaPnD4PIvbiERwDy6fmMXE6C8IVu lJy9MaE78FdFcFTbTYfC+sk4TwIsnuwyfDeqgGLOGgcXX/OO4mrxiX/I/RSfASw3HbiTwzg4XvY JUVmHWRQS2y6hIg== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-mlxbf3.c | 101 +++++++++++++++++++++++------------------= ---- 1 file changed, 52 insertions(+), 49 deletions(-) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index ed29b07d16c19030675994b51a0613b022af131b..c812011bdbe65a9ee793ae1a5bf= c656b523ab8ed 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -42,7 +43,7 @@ #define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0) =20 struct mlxbf3_gpio_context { - struct gpio_chip gc; + struct gpio_generic_chip chip; =20 /* YU GPIO block address */ void __iomem *gpio_set_io; @@ -58,18 +59,17 @@ static void mlxbf3_gpio_irq_enable(struct irq_data *irq= d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 gpiochip_enable_irq(gc, offset); =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&gs->chip); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); =20 val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); val |=3D BIT(offset); writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } =20 static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) @@ -77,16 +77,15 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *ir= qd) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); - val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); - val &=3D ~BIT(offset); - writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { + val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val &=3D ~BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); =20 - writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + } =20 gpiochip_disable_irq(gc, offset); } @@ -94,7 +93,7 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) { struct mlxbf3_gpio_context *gs =3D ptr; - struct gpio_chip *gc =3D &gs->gc; + struct gpio_chip *gc =3D &gs->chip.gc; unsigned long pending; u32 level; =20 @@ -113,37 +112,33 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsig= ned int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_BOTH: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - break; - case IRQ_TYPE_EDGE_RISING: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - break; - case IRQ_TYPE_EDGE_FALLING: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - break; - default: - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); - return -EINVAL; + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_RISING: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_FALLING: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + break; + default: + return -EINVAL; + } } =20 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); - irq_set_handler_locked(irqd, handle_edge_irq); =20 return 0; @@ -186,6 +181,7 @@ static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip = *chip) =20 static int mlxbf3_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct mlxbf3_gpio_context *gs; struct gpio_irq_chip *girq; @@ -211,16 +207,23 @@ static int mlxbf3_gpio_probe(struct platform_device *= pdev) gs->gpio_clr_io =3D devm_platform_ioremap_resource(pdev, 3); if (IS_ERR(gs->gpio_clr_io)) return PTR_ERR(gs->gpio_clr_io); - gc =3D &gs->gc; + gc =3D &gs->chip.gc; =20 - ret =3D bgpio_init(gc, dev, 4, - gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, - gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, - gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, - gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, - gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, + .set =3D gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, + .clr =3D gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, + .dirout =3D gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, + .dirin =3D gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, + }; + + ret =3D gpio_generic_chip_init(&gs->chip, &config); if (ret) - return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__); + return dev_err_probe(dev, ret, + "%s: failed to initialize the generic GPIO chip", + __func__); =20 gc->request =3D gpiochip_generic_request; gc->free =3D gpiochip_generic_free; @@ -229,7 +232,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) =20 irq =3D platform_get_irq_optional(pdev, 0); if (irq >=3D 0) { - girq =3D &gs->gc.irq; + girq =3D &gs->chip.gc.irq; gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip); girq->default_type =3D IRQ_TYPE_NONE; /* This will let us handle the parent IRQ in the driver */ @@ -250,7 +253,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) =20 platform_set_drvdata(pdev, gs); =20 - ret =3D devm_gpiochip_add_data(dev, &gs->gc, gs); + ret =3D devm_gpiochip_add_data(dev, gc, gs); if (ret) dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); =20 --=20 2.48.1