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Wed, 03 Sep 2025 01:00:20 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:05 +0200 Subject: [PATCH 01/12] gpio: ixp4xx: allow building the module with COMPILE_TEST enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-1-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=732; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 6fd904e29c3e744acf599c75147a25a01a3a2cc2..0fd5b09c499ac8468269b62a306= f9ec03c3f7a9b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -408,8 +408,7 @@ config GPIO_IMX_SCU =20 config GPIO_IXP4XX bool "Intel IXP4xx GPIO" - depends on ARCH_IXP4XX - depends on OF + depends on (ARCH_IXP4XX && OF) || COMPILE_TEST select GPIO_GENERIC select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY --=20 2.48.1 From nobody Fri Oct 3 08:48:18 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BB102E62BF for ; Wed, 3 Sep 2025 08:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ixp4xx.c | 70 ++++++++++++++++++++++++------------------= ---- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index 28a8a6a8f05feec4188467693591e36dbf04ccdc..0cf10d0ba16ef7f45ac114c3446= 8bc263442ccca 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -53,14 +54,14 @@ =20 /** * struct ixp4xx_gpio - IXP4 GPIO state container + * @chip: generic GPIO chip for this instance * @dev: containing device for this instance - * @gc: gpiochip for this instance * @base: remapped I/O-memory base * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, * 0: level triggered */ struct ixp4xx_gpio { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct device *dev; void __iomem *base; unsigned long long irq_edge; @@ -100,7 +101,6 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d,= unsigned int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ixp4xx_gpio *g =3D gpiochip_get_data(gc); int line =3D d->hwirq; - unsigned long flags; u32 int_style; u32 int_reg; u32 val; @@ -144,26 +144,24 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *= d, unsigned int type) int_reg =3D IXP4XX_REG_GPIT1; } =20 - raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &g->chip) { + /* Clear the style for the appropriate pin */ + val =3D __raw_readl(g->base + int_reg); + val &=3D ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); + __raw_writel(val, g->base + int_reg); =20 - /* Clear the style for the appropriate pin */ - val =3D __raw_readl(g->base + int_reg); - val &=3D ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); - __raw_writel(val, g->base + int_reg); + __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); =20 - __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); + /* Set the new style */ + val =3D __raw_readl(g->base + int_reg); + val |=3D (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); + __raw_writel(val, g->base + int_reg); =20 - /* Set the new style */ - val =3D __raw_readl(g->base + int_reg); - val |=3D (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); - __raw_writel(val, g->base + int_reg); - - /* Force-configure this line as an input */ - val =3D __raw_readl(g->base + IXP4XX_REG_GPOE); - val |=3D BIT(d->hwirq); - __raw_writel(val, g->base + IXP4XX_REG_GPOE); - - raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); + /* Force-configure this line as an input */ + val =3D __raw_readl(g->base + IXP4XX_REG_GPOE); + val |=3D BIT(d->hwirq); + __raw_writel(val, g->base + IXP4XX_REG_GPOE); + } =20 /* This parent only accept level high (asserted) */ return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); @@ -206,6 +204,7 @@ static int ixp4xx_gpio_child_to_parent_hwirq(struct gpi= o_chip *gc, =20 static int ixp4xx_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; unsigned long flags; struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -295,30 +294,33 @@ static int ixp4xx_gpio_probe(struct platform_device *= pdev) flags =3D 0; #endif =20 + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D g->base + IXP4XX_REG_GPIN, + .set =3D g->base + IXP4XX_REG_GPOUT, + .dirin =3D g->base + IXP4XX_REG_GPOE, + .flags =3D flags, + }; + /* Populate and register gpio chip */ - ret =3D bgpio_init(&g->gc, dev, 4, - g->base + IXP4XX_REG_GPIN, - g->base + IXP4XX_REG_GPOUT, - NULL, - NULL, - g->base + IXP4XX_REG_GPOE, - flags); + ret =3D gpio_generic_chip_init(&g->chip, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; } - g->gc.ngpio =3D 16; - g->gc.label =3D "IXP4XX_GPIO_CHIP"; + g->chip.gc.ngpio =3D 16; + g->chip.gc.label =3D "IXP4XX_GPIO_CHIP"; /* * TODO: when we have migrated to device tree and all GPIOs * are fetched using phandles, set this to -1 to get rid of * the fixed gpiochip base. */ - g->gc.base =3D 0; - g->gc.parent =3D &pdev->dev; - g->gc.owner =3D THIS_MODULE; + g->chip.gc.base =3D 0; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-idt3243x.c | 45 ++++++++++++++++++++++------------------= ---- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpio/gpio-idt3243x.c b/drivers/gpio/gpio-idt3243x.c index 535f255144556ecb71c5e3f8756f9f4a8bd9ca3d..232a621ba086ef66b2d2f0d4713= 88c77ac5caa5b 100644 --- a/drivers/gpio/gpio-idt3243x.c +++ b/drivers/gpio/gpio-idt3243x.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include #include #include @@ -18,7 +19,7 @@ #define IDT_GPIO_ISTAT 0x0C =20 struct idt_gpio_ctrl { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *pic; void __iomem *gpio; u32 mask_cache; @@ -50,14 +51,13 @@ static int idt_gpio_irq_set_type(struct irq_data *d, un= signed int flow_type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct idt_gpio_ctrl *ctrl =3D gpiochip_get_data(gc); unsigned int sense =3D flow_type & IRQ_TYPE_SENSE_MASK; - unsigned long flags; u32 ilevel; =20 /* hardware only supports level triggered */ if (sense =3D=3D IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH)) return -EINVAL; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); =20 ilevel =3D readl(ctrl->gpio + IDT_GPIO_ILEVEL); if (sense & IRQ_TYPE_LEVEL_HIGH) @@ -68,7 +68,6 @@ static int idt_gpio_irq_set_type(struct irq_data *d, unsi= gned int flow_type) writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL); irq_set_handler_locked(d, handle_level_irq); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); return 0; } =20 @@ -84,14 +83,11 @@ static void idt_gpio_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct idt_gpio_ctrl *ctrl =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - - ctrl->mask_cache |=3D BIT(d->hwirq); - writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); - - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { + ctrl->mask_cache |=3D BIT(d->hwirq); + writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); + } =20 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } @@ -100,15 +96,13 @@ static void idt_gpio_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct idt_gpio_ctrl *ctrl =3D gpiochip_get_data(gc); - unsigned long flags; =20 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + + guard(gpio_generic_lock_irqsave)(&ctrl->chip); =20 ctrl->mask_cache &=3D ~BIT(d->hwirq); writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); - - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static int idt_gpio_irq_init_hw(struct gpio_chip *gc) @@ -134,6 +128,7 @@ static const struct irq_chip idt_gpio_irqchip =3D { =20 static int idt_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; struct idt_gpio_ctrl *ctrl; @@ -150,18 +145,24 @@ static int idt_gpio_probe(struct platform_device *pde= v) if (IS_ERR(ctrl->gpio)) return PTR_ERR(ctrl->gpio); =20 - ctrl->gc.parent =3D dev; + ctrl->chip.gc.parent =3D dev; =20 - ret =3D bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA, - NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0); + config =3D (typeof(config)){ + .dev =3D &pdev->dev, + .sz =3D 4, + .dat =3D ctrl->gpio + IDT_GPIO_DATA, + .dirout =3D ctrl->gpio + IDT_GPIO_DIR, + }; + + ret =3D gpio_generic_chip_init(&ctrl->chip, &config); if (ret) { - dev_err(dev, "bgpio_init failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return ret; } =20 ret =3D device_property_read_u32(dev, "ngpios", &ngpios); if (!ret) - ctrl->gc.ngpio =3D ngpios; + ctrl->chip.gc.ngpio =3D ngpios; =20 if (device_property_read_bool(dev, "interrupt-controller")) { ctrl->pic =3D devm_platform_ioremap_resource_byname(pdev, "pic"); @@ -172,7 +173,7 @@ static int idt_gpio_probe(struct platform_device *pdev) if (parent_irq < 0) return parent_irq; =20 - girq =3D &ctrl->gc.irq; + girq =3D &ctrl->chip.gc.irq; gpio_irq_chip_set_chip(girq, &idt_gpio_irqchip); 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Wed, 03 Sep 2025 01:00:24 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:2f8b:4799:6bd6:35df]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b83e954b7sm113331635e9.1.2025.09.03.01.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 01:00:24 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:08 +0200 Subject: [PATCH 04/12] gpio: blzp1600: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-4-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-blzp1600.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-blzp1600.c b/drivers/gpio/gpio-blzp1600.c index 055cb296ae54758cdc206d36aa1df7b8377d32ec..bfb35d59fa561c43889b186fdfb= 8d9184b750a53 100644 --- a/drivers/gpio/gpio-blzp1600.c +++ b/drivers/gpio/gpio-blzp1600.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -36,7 +37,7 @@ =20 struct blzp1600_gpio { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; int irq; }; =20 @@ -76,7 +77,7 @@ static void blzp1600_gpio_irq_mask(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1); } =20 @@ -84,7 +85,7 @@ static void blzp1600_gpio_irq_unmask(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0); } =20 @@ -99,9 +100,9 @@ static void blzp1600_gpio_irq_enable(struct irq_data *d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d)); + gpiochip_enable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0); blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1); } @@ -110,9 +111,9 @@ static void blzp1600_gpio_irq_disable(struct irq_data *= d) { struct blzp1600_gpio *chip =3D get_blzp1600_gpio_from_irq_data(d); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0); - gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d)); + gpiochip_disable_irq(&chip->gen_gc.gc, irqd_to_hwirq(d)); } =20 static int blzp1600_gpio_irq_set_type(struct irq_data *d, u32 type) @@ -121,7 +122,7 @@ static int blzp1600_gpio_irq_set_type(struct irq_data *= d, u32 type) u32 edge_level, single_both, fall_rise; int mask =3D BIT(d->hwirq); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); edge_level =3D blzp1600_gpio_read(chip, GPIO_IS_REG); single_both =3D blzp1600_gpio_read(chip, GPIO_IBE_REG); fall_rise =3D blzp1600_gpio_read(chip, GPIO_IEV_REG); @@ -186,8 +187,8 @@ static void blzp1600_gpio_irqhandler(struct irq_desc *d= esc) =20 chained_irq_enter(irqchip, desc); irq_status =3D blzp1600_gpio_read(gpio, GPIO_RIS_REG); - for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio) - generic_handle_domain_irq(gpio->gc.irq.domain, hwirq); + for_each_set_bit(hwirq, &irq_status, gpio->gen_gc.gc.ngpio) + generic_handle_domain_irq(gpio->gen_gc.gc.irq.domain, hwirq); =20 chained_irq_exit(irqchip, desc); } @@ -197,7 +198,7 @@ static int blzp1600_gpio_set_debounce(struct gpio_chip = *gc, unsigned int offset, { struct blzp1600_gpio *chip =3D gpiochip_get_data(gc); =20 - guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); blzp1600_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce); =20 return 0; @@ -216,6 +217,7 @@ static int blzp1600_gpio_set_config(struct gpio_chip *g= c, unsigned int offset, u =20 static int blzp1600_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct blzp1600_gpio *chip; struct gpio_chip *gc; int ret; @@ -228,14 +230,21 @@ static int blzp1600_gpio_probe(struct platform_device= *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); =20 - ret =3D bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG, - chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG, - chip->base + GPIO_DIR_REG, NULL, 0); + config =3D (typeof(config)){ + .dev =3D &pdev->dev, + .sz =3D 4, + .dat =3D chip->base + GPIO_IDATA_REG, + .set =3D chip->base + GPIO_SET_REG, + .clr =3D chip->base + GPIO_CLR_REG, + .dirout =3D chip->base + GPIO_DIR_REG, + }; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski For better readability and easier maintenance, order the includes alphabetically. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tb10x.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index 1869ee7f9423efb31045a3394343e404db102faf..356d0a82e25f29f60c43801cee6= c6803ea7a22c2 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -7,20 +7,20 @@ * Christian Ruppert */ =20 -#include -#include -#include +#include #include -#include -#include -#include #include #include +#include +#include +#include +#include #include #include -#include -#include #include +#include +#include +#include =20 #define TB10X_GPIO_DIR_IN (0x00000000) #define TB10X_GPIO_DIR_OUT (0x00000001) --=20 2.48.1 From nobody Fri Oct 3 08:48:18 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013EC2E9755 for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Increase build coverage by allowing the module to be built with COMPILE_TEST=3Dy. We need an actual prompt entry in this case so add it. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0fd5b09c499ac8468269b62a306f9ec03c3f7a9b..2fb77eff3b1f2e862a81eb77f2d= 4d8f14c27873d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -734,7 +734,8 @@ config GPIO_TANGIER If built as a module its name will be gpio-tangier. =20 config GPIO_TB10X - bool + bool "Abilis Systems TB10x GPIO controller" + depends on ARC_PLAT_TB10X || COMPILE_TEST select GPIO_GENERIC select GENERIC_IRQ_CHIP select OF_GPIO --=20 2.48.1 From nobody Fri Oct 3 08:48:18 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FF961DF270 for ; Wed, 3 Sep 2025 08:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tb10x.c | 60 +++++++++++++++++++++++--------------------= ---- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index 356d0a82e25f29f60c43801cee6c6803ea7a22c2..f20b6654b865555579bb356a336= 308e23b0e5af6 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -20,7 +21,6 @@ #include #include #include -#include =20 #define TB10X_GPIO_DIR_IN (0x00000000) #define TB10X_GPIO_DIR_OUT (0x00000001) @@ -36,13 +36,13 @@ * @base: register base address * @domain: IRQ domain of GPIO generated interrupts managed by this contro= ller * @irq: Interrupt line of parent interrupt controller - * @gc: gpio_chip structure associated to this GPIO controller + * @chip: Generic GPIO chip structure associated with this GPIO controller */ struct tb10x_gpio { void __iomem *base; struct irq_domain *domain; int irq; - struct gpio_chip gc; + struct gpio_generic_chip chip; }; =20 static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int off= s) @@ -60,16 +60,13 @@ static inline void tb10x_set_bits(struct tb10x_gpio *gp= io, unsigned int offs, u32 mask, u32 val) { u32 r; - unsigned long flags; =20 - raw_spin_lock_irqsave(&gpio->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&gpio->chip); =20 r =3D tb10x_reg_read(gpio, offs); r =3D (r & ~mask) | (val & mask); =20 tb10x_reg_write(gpio, offs, r); - - raw_spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags); } =20 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset) @@ -107,6 +104,7 @@ static irqreturn_t tb10x_gpio_irq_cascade(int irq, void= *data) =20 static int tb10x_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct tb10x_gpio *tb10x_gpio; struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -127,9 +125,9 @@ static int tb10x_gpio_probe(struct platform_device *pde= v) if (IS_ERR(tb10x_gpio->base)) return PTR_ERR(tb10x_gpio->base); =20 - tb10x_gpio->gc.label =3D + tb10x_gpio->chip.gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node); - if (!tb10x_gpio->gc.label) + if (!tb10x_gpio->chip.gc.label) return -ENOMEM; =20 /* @@ -137,29 +135,30 @@ static int tb10x_gpio_probe(struct platform_device *p= dev) * the lines, no special set or clear registers and a data direction regi= ster * wher 1 means "output". */ - ret =3D bgpio_init(&tb10x_gpio->gc, dev, 4, - tb10x_gpio->base + OFFSET_TO_REG_DATA, - NULL, - NULL, - tb10x_gpio->base + OFFSET_TO_REG_DDR, - NULL, - 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D tb10x_gpio->base + OFFSET_TO_REG_DATA, + .dirout =3D tb10x_gpio->base + OFFSET_TO_REG_DDR, + }; + + ret =3D gpio_generic_chip_init(&tb10x_gpio->chip, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; } - tb10x_gpio->gc.base =3D -1; - tb10x_gpio->gc.parent =3D dev; - tb10x_gpio->gc.owner =3D THIS_MODULE; + tb10x_gpio->chip.gc.base =3D -1; + tb10x_gpio->chip.gc.parent =3D dev; + tb10x_gpio->chip.gc.owner =3D THIS_MODULE; /* - * ngpio is set by bgpio_init() but we override it, this .request() - * callback also overrides the one set up by generic GPIO. + * ngpio is set by gpio_generic_chip_init() but we override it, this + * .request() callback also overrides the one set up by generic GPIO. */ - tb10x_gpio->gc.ngpio =3D ngpio; - tb10x_gpio->gc.request =3D gpiochip_generic_request; - tb10x_gpio->gc.free =3D gpiochip_generic_free; + tb10x_gpio->chip.gc.ngpio =3D ngpio; + tb10x_gpio->chip.gc.request =3D gpiochip_generic_request; + tb10x_gpio->chip.gc.free =3D gpiochip_generic_free; =20 - ret =3D devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio); + ret =3D devm_gpiochip_add_data(dev, &tb10x_gpio->chip.gc, tb10x_gpio); if (ret < 0) { dev_err(dev, "Could not add gpiochip.\n"); return ret; @@ -174,7 +173,7 @@ static int tb10x_gpio_probe(struct platform_device *pde= v) if (ret < 0) return ret; =20 - tb10x_gpio->gc.to_irq =3D tb10x_gpio_to_irq; + tb10x_gpio->chip.gc.to_irq =3D tb10x_gpio_to_irq; tb10x_gpio->irq =3D ret; =20 ret =3D devm_request_irq(dev, ret, tb10x_gpio_irq_cascade, @@ -183,14 +182,15 @@ static int tb10x_gpio_probe(struct platform_device *p= dev) if (ret !=3D 0) return ret; =20 - tb10x_gpio->domain =3D irq_domain_create_linear(dev_fwnode(dev), tb10x_g= pio->gc.ngpio, + tb10x_gpio->domain =3D irq_domain_create_linear(dev_fwnode(dev), + tb10x_gpio->chip.gc.ngpio, &irq_generic_chip_ops, NULL); if (!tb10x_gpio->domain) { return -ENOMEM; } =20 ret =3D irq_alloc_domain_generic_chips(tb10x_gpio->domain, - tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label, + tb10x_gpio->chip.gc.ngpio, 1, tb10x_gpio->chip.gc.label, handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE, IRQ_GC_INIT_MASK_CACHE); if (ret) @@ -218,9 +218,9 @@ static void tb10x_gpio_remove(struct platform_device *p= dev) { struct tb10x_gpio *tb10x_gpio =3D platform_get_drvdata(pdev); =20 - if (tb10x_gpio->gc.to_irq) { + if (tb10x_gpio->chip.gc.to_irq) { irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0], - BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0); 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Wed, 03 Sep 2025 01:00:28 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 03 Sep 2025 10:00:12 +0200 Subject: [PATCH 08/12] gpio: mlxbf: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-gpio-mmio-gpio-conv-part3-v1-8-ff346509f408@linaro.org> References: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> In-Reply-To: <20250903-gpio-mmio-gpio-conv-part3-v1-0-ff346509f408@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Linus Walleij , Imre Kaloz , James Cowgill , Matt Redfearn , Neil Jones , Nikolaos Pasaloukos Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2146; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mlxbf.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpio/gpio-mlxbf.c b/drivers/gpio/gpio-mlxbf.c index 1fa9973f55b96a4b517b5864ffb92fbbf8626053..843f40496be7b723c300b3ea2f1= 9fc698a56abba 100644 --- a/drivers/gpio/gpio-mlxbf.c +++ b/drivers/gpio/gpio-mlxbf.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,7 @@ struct mlxbf_gpio_context_save_regs { =20 /* Device state structure. */ struct mlxbf_gpio_state { - struct gpio_chip gc; + struct gpio_generic_chip chip; =20 /* Memory Address */ void __iomem *base; @@ -49,6 +50,7 @@ struct mlxbf_gpio_state { =20 static int mlxbf_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct mlxbf_gpio_state *gs; struct device *dev =3D &pdev->dev; struct gpio_chip *gc; @@ -62,21 +64,24 @@ static int mlxbf_gpio_probe(struct platform_device *pde= v) if (IS_ERR(gs->base)) return PTR_ERR(gs->base); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Increase build coverage by allowing the module to be built with COMPILE_TEST=3Dy. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2fb77eff3b1f2e862a81eb77f2d4d8f14c27873d..08e1fc13195452bda347f81a355= 2614d8e603bd0 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -303,7 +303,7 @@ config GPIO_EN7523 =20 config GPIO_EP93XX def_bool y - depends on ARCH_EP93XX + depends on ARCH_EP93XX || COMPILE_TEST select GPIO_GENERIC select GPIOLIB_IRQCHIP =20 --=20 2.48.1 From nobody Fri Oct 3 08:48:18 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7EA72EB5DE for ; Wed, 3 Sep 2025 08:00:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski For better readability and easier maintenance, order the includes alphabetically. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 58d2464c07bc360137f3100de4e4147030bb121c..08e5ae8bf4d1a80ca26680a3c7b= ff0b8039fa41a 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -9,16 +9,16 @@ * linux/arch/arm/mach-ep93xx/core.c */ =20 +#include +#include #include -#include -#include #include #include #include -#include -#include -#include +#include +#include #include +#include =20 struct ep93xx_gpio_irq_chip { void __iomem *base; --=20 2.48.1 From nobody Fri Oct 3 08:48:18 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8163B2EBB83 for ; Wed, 3 Sep 2025 08:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 08e5ae8bf4d1a80ca26680a3c7bff0b8039fa41a..c6c8170813331be567048980710= 226792b4b2a02 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -31,11 +32,14 @@ struct ep93xx_gpio_irq_chip { =20 struct ep93xx_gpio_chip { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip chip; struct ep93xx_gpio_irq_chip *eic; }; =20 -#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) +static struct ep93xx_gpio_chip *to_ep93xx_gpio_chip(struct gpio_chip *gc) +{ + return container_of(to_gpio_generic_chip(gc), struct ep93xx_gpio_chip, ch= ip); +} =20 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) { @@ -267,7 +271,7 @@ static const struct irq_chip gpio_eic_irq_chip =3D { static int ep93xx_setup_irqs(struct platform_device *pdev, struct ep93xx_gpio_chip *egc) { - struct gpio_chip *gc =3D &egc->gc; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mlxbf3.c | 101 +++++++++++++++++++++++------------------= ---- 1 file changed, 52 insertions(+), 49 deletions(-) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index ed29b07d16c19030675994b51a0613b022af131b..c812011bdbe65a9ee793ae1a5bf= c656b523ab8ed 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -42,7 +43,7 @@ #define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0) =20 struct mlxbf3_gpio_context { - struct gpio_chip gc; + struct gpio_generic_chip chip; =20 /* YU GPIO block address */ void __iomem *gpio_set_io; @@ -58,18 +59,17 @@ static void mlxbf3_gpio_irq_enable(struct irq_data *irq= d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 gpiochip_enable_irq(gc, offset); =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&gs->chip); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); =20 val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); val |=3D BIT(offset); writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } =20 static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) @@ -77,16 +77,15 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *ir= qd) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); - val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); - val &=3D ~BIT(offset); - writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { + val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val &=3D ~BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); =20 - writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + } =20 gpiochip_disable_irq(gc, offset); } @@ -94,7 +93,7 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) { struct mlxbf3_gpio_context *gs =3D ptr; - struct gpio_chip *gc =3D &gs->gc; + struct gpio_chip *gc =3D &gs->chip.gc; unsigned long pending; u32 level; =20 @@ -113,37 +112,33 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsig= ned int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); struct mlxbf3_gpio_context *gs =3D gpiochip_get_data(gc); irq_hw_number_t offset =3D irqd_to_hwirq(irqd); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_BOTH: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - break; - case IRQ_TYPE_EDGE_RISING: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); - break; - case IRQ_TYPE_EDGE_FALLING: - val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - val |=3D BIT(offset); - writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); - break; - default: - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); - return -EINVAL; + scoped_guard(gpio_generic_lock_irqsave, &gs->chip) { + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_RISING: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_FALLING: + val =3D readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + break; + default: + return -EINVAL; + } } =20 - raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); - irq_set_handler_locked(irqd, handle_edge_irq); =20 return 0; @@ -186,6 +181,7 @@ static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip = *chip) =20 static int mlxbf3_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct mlxbf3_gpio_context *gs; struct gpio_irq_chip *girq; @@ -211,16 +207,23 @@ static int mlxbf3_gpio_probe(struct platform_device *= pdev) gs->gpio_clr_io =3D devm_platform_ioremap_resource(pdev, 3); if (IS_ERR(gs->gpio_clr_io)) return PTR_ERR(gs->gpio_clr_io); - gc =3D &gs->gc; + gc =3D &gs->chip.gc; =20 - ret =3D bgpio_init(gc, dev, 4, - gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, - gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, - gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, - gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, - gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, + .set =3D gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, + .clr =3D gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, + .dirout =3D gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, + .dirin =3D gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, + }; + + ret =3D gpio_generic_chip_init(&gs->chip, &config); if (ret) - return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__); + return dev_err_probe(dev, ret, + "%s: failed to initialize the generic GPIO chip", + __func__); =20 gc->request =3D gpiochip_generic_request; gc->free =3D gpiochip_generic_free; @@ -229,7 +232,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) =20 irq =3D platform_get_irq_optional(pdev, 0); if (irq >=3D 0) { - girq =3D &gs->gc.irq; + girq =3D &gs->chip.gc.irq; gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip); girq->default_type =3D IRQ_TYPE_NONE; /* This will let us handle the parent IRQ in the driver */ @@ -250,7 +253,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) =20 platform_set_drvdata(pdev, gs); =20 - ret =3D devm_gpiochip_add_data(dev, &gs->gc, gs); + ret =3D devm_gpiochip_add_data(dev, gc, gs); if (ret) dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); =20 --=20 2.48.1