From nobody Fri Oct 3 07:40:22 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B650D2FCBEB for ; Wed, 3 Sep 2025 11:58:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900706; cv=none; b=YXoHxDsGevLf7gLxQD5kQEQRA7ccZyYaQhmGbTm132SFV1UW1qHlq1pL0gKdR9YM0Qd96ZzuxgEm7WKmWRJdn1FI7nJcp+LIpMxwcqxoE38WXdz3Gq2Cp+eXJUKFfKUaKkcuofJv/YVTqHPWg9Vi5h2E6pCZQDyR5+J2vTc8xVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900706; c=relaxed/simple; bh=Mg8cF8dtHa8FBVVXmu7mhjOEv6I2lafX52Q7aTfQdic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nroKkH+PzoNvPm4de8KXqZLDXK8WCNl1fFPCAmP9HPZr8JtzcdBYy3SHH6rGHUaecqLVaQ422MrvXYot0gMHFhSJb8nnH5FbGGvu/sSj9C3BiciQcGxIdmaOWfeGnacd6tx+0Rxbea+dkb9EAakXHrmY8szLK+0VVQaXnuWD7F8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=EQLw1s6V; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="EQLw1s6V" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEqBL013914 for ; Wed, 3 Sep 2025 11:58:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 7m1HwxzI8G7RL+o2tt5C5+jDIvVaSDVT2O8wP58iCTY=; b=EQLw1s6Vwpk5KUvn 5mZpuQBSCeTg5U8GFQ+9ZgzJWEGiCA20lsbVlPYYRjkrX+FI7mE8sJxxpVb2D25e Il7Z34ZyKv9EjK6ql9sU0nUj6hc0v24sbSduEET7DAlgsGBNTe4j7Xsr9UFTKs77 xfNZJkFuf9rFvD6alQn5blSKbhUtClMf4QcXhIzYMglXYLuL3N0SjT334Dpb5IFx aG4tD1KoUouTCmzYteSayI4R5U+NLTKyQJgXixUlscJNEReZyhVKXt3mpGv3Kaht H20pT9yd3VjSA5sC5UEUVoSILHg1eHFgAd8Ub51Lmlory96VHhRbT8A8LzpT8Ae3 GjQG6g== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48w8wy7dx0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:23 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-70dfd87a495so116737936d6.3 for ; Wed, 03 Sep 2025 04:58:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900703; x=1757505503; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7m1HwxzI8G7RL+o2tt5C5+jDIvVaSDVT2O8wP58iCTY=; b=DMfeaofDZgp5V5q9GOnaAfuUIfc5fllv/s0gziGHO4tnVa9g7a7A8jnD+6J8aTjKYs 20DKZSUFD1hJGu3udGS6QlDrUWq79yAFZ1D2FB5OcUct6SygM9BLcNRIKjuqruOGgy1B Gp7XGdYYF2YV85zfLRQj6yXDwduFNAe4kpdPOqrZqEOyJ/jv1ZAffOdwwp2/OsD+Nsmw 5zSb12WihVIin9lptKoOFqA6okMv04xjOMWYzJeCe0+WpselppcKvkoMd3GGjIlRBQA0 OxjLoqBC6VKu6XT9DxCMCjvV2EDqVPUzjutXvuxoMC5rQbiykPv3xpPDBWhyReMNdXdK bQWg== X-Forwarded-Encrypted: i=1; AJvYcCX5Z1yeXgq8B9a6PEn8MUrViaM+rPVjBG/+kf2iso+Ke1TEp9hUhKGqJwewTdKA6Ic2PwglXcl4LZVo//U=@vger.kernel.org X-Gm-Message-State: AOJu0YxlEMNcaQ90WGGKA0ENsMvPTzCNN99ReKGKDWhB3RycZ6qYQwZ7 DCaqIzJnu+9E9sSDBH97NSDzLFATHO0TykzA3gXz2mor2P2aLXOV/cSGeb1xL/Iz23GZ52TFmxO T/Q+A6fHSS/s5EVGgVV/MEKFvKnuI3p66DNAufmgGvr4b0ZI/3m4xy6qDZlC17U1QOUY= X-Gm-Gg: ASbGnctvMPLvNFBavj/Z/78tvB7TaFtk/GA9ey2KQBnVkmThSBtRW5aVGYKU9Iyo6pH RKHeRBSjjG7RhMNdgBIHyB5ReIpn/KN/5z1JWeCIYTeuScLdmprxn5aVxAQInGXzwZ22RXRCdTA 2LncaEyqFezc5Iv78oFIrQZC480o6wKoFm9E262Z9maix9RtaY9qCgeGFTOer/hpnG1SrSo/a32 FcJauEyAASgY08Wy8YEnB2H5FHTbUy3b/oTJkUdf2LZ4Q6N8kLnavbO69pJFLgrIQky84AyPUw+ 07V0oYZL0CSwQ/qgn04yhgxeydq1AYrD62OCF8hJy/e0NRJDc8rFlXlELPK9db/FP4BCObCz747 OeyDaeT6HPlWu08IwitlmBM6bMC1SNYdzAeVhP77C6DNaiksIvCEY X-Received: by 2002:a05:6214:234c:b0:70d:c901:64fe with SMTP id 6a1803df08f44-70fac883ce1mr176720486d6.41.1756900702738; Wed, 03 Sep 2025 04:58:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHj9hZcrJ+8S42PCt+RrOt1ShsvO+BYl52eMjU0T3wyJA35RFJjzM/AJCRPGUZH3504p2FyKQ== X-Received: by 2002:a05:6214:234c:b0:70d:c901:64fe with SMTP id 6a1803df08f44-70fac883ce1mr176720126d6.41.1756900702249; Wed, 03 Sep 2025 04:58:22 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:20 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:12 +0300 Subject: [PATCH v8 1/9] dt-bindings: display/msm: dp-controller: allow eDP for SA8775P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-1-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1543; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Mg8cF8dtHa8FBVVXmu7mhjOEv6I2lafX52Q7aTfQdic=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1W1p9ibzzCWoQUIQX0KfzGSz/kKXFwqoffX NJj3hOGz9mJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtVgAKCRCLPIo+Aiko 1XT3CACu1B8wHPkuKcAXGFd3QruC31bXNY0THTielGdmOfrW1fAonzUr3Uu2fYxVH5s7ghwg9k8 68pHE89tztuW4b4bNgWVshbnNrINXf70tUF0y70xHDMIJ6b+EHPogOndk3qAcJUholeTSK9swx7 PS0bFEobZk+VbXsh0QiVlHl5RZRmoSflDwsGA88Vs580Cch8RFs+b1d52zmEYfEbrB9siCkWGu6 wRWaOfCtn/+iTtNQIvEdvLazeBoi5MsCrAu1KAgKEmvSuV3ObzYNpprUKesg1vr1uW49Fhj2U2L YLQv8p0o35kFJsMsvDISYVh8N1pcKQuVXLc6KYInBJ9Km+g7 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b82d5f cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=iBDq5nSyD7x731avtJAA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: uk7Kzbfb_6_xe7ctYxHwIY0TUtsOKuot X-Proofpoint-ORIG-GUID: uk7Kzbfb_6_xe7ctYxHwIY0TUtsOKuot X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfX3on2Jg50jG1H YTeft3XofistNT3y2ZDNqdTDHkraiuTjXi2R6Y1BiuOfyB3ZPlg+1YEdIEAYKxGRT5dGJGNHd/Z Jc2/kCCje/0+OzymJC96JPeyyPs/9L1tReQUXfDCY+55PzhdqmbQ7xxYna0hS5C0Eq3ab2yuJ+Q 6SIzM7YGq+miWf+JSmb7kshkkNfqNpQPiPMrOqWXfOfbm/lOK9SPpMHsGZ6sBERnvvn6QgJzlKl vWRr5KZ9HwPFqrShtyZeBdeibG01h2AOVu1BeF5Em9/ReaE4KzmQfzkUQYNvLUmToJSS2FxV9Q4 CZAFopVazrcPPhd6rjkmsjprdeAJsifzlo2bdwjJKSv9tRZbinw9mdsAiBFLteFYmUjd19vdFHJ nod1S9uP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 On Qualcomm SA8775P the DP controller might be driving either a DisplayPort or a eDP sink (depending on the PHY that is tied to the controller). Reflect that in the schema. Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dp-controller.yaml | 25 ++++++++++++++++--= ---- 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9923b065323bbab99de5079b674a0317f3074373..aed3bafa67e3c24d2a876acd296= 60378b367603a 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -174,12 +174,25 @@ allOf: properties: "#sound-dai-cells": false else: - properties: - aux-bus: false - reg: - minItems: 5 - required: - - "#sound-dai-cells" + if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + then: + oneOf: + - required: + - aux-bus + - required: + - "#sound-dai-cells" + else: + properties: + aux-bus: false + reg: + minItems: 5 + required: + - "#sound-dai-cells" =20 additionalProperties: false =20 --=20 2.47.2 From nobody Fri Oct 3 07:40:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9FD02FCC04 for ; Wed, 3 Sep 2025 11:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900708; cv=none; b=WucQe/zAA6+f1nh7CC+mqusC4hDXeNvI6f7tM+btf1n7thebL0Ex37p410I3aJgjnB68NzCx5mDn8nUChwhkF3QSFlHBvJRA2naLWy2sWg7+/oHdnKpB/0rir6hgn9UALD51G5nh05EWbJNB+92mviTiLfXnNQa0n11GfqixlRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900708; c=relaxed/simple; bh=RDcsC0Xk/SeTiAYs2PrzT5y7v3tCHnCk8IS1ckk2ayU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q5Wjm7qT5fsncZtxGAKE2Pszlrk+NxmYvc9j1KQySdYWo3keBfKAwwJKRnvztbzluknlCF9Ve98muZFIRAxGHrZBgmc8BjUpBhVQjHxxm8PP+XTxit8dD2SC6M4T3t8PiO2LI3UT8EQjlCm0pUYyFQVscvZYv5aLmqhGN9mYt9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=chd3mvzi; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="chd3mvzi" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEogd020226 for ; Wed, 3 Sep 2025 11:58:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +B6J/aB/tids3HBfaJNu1z9KCUM3gjNbHkRd/sTehYk=; b=chd3mvziinkIxnri 4Epm3Xc98e2TrW/406+Usjs+Zmx6c4bOUZtzeqPFGZp2xrZs1u/ceKVeuWM2JGk1 4ZKMAwLc4wBgzptRYoNMZ3/6o2TBwhWp9cYAxlDi/zYR7wCnS1Tmo5SEKa9QGwpz T9ZOBgr1iyY/agT8fS3JzDggHcNaaqv0boRjaCAUhDMfrMdHhnOenlWIbEF1Io/l o5pT51LDltjawdRmjBwmm2q38rFqimZvkGvA6w4uO3OoZ3A0K+Qrik5Eb6dXKrsj zlwDiC1CuiCAZKrIvYRw4PpOEwFo5Tlb+sTmFnTrkVPtdLrzQTS4TvN5jF81tG0t 6Hjk6A== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48utk93aw5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:26 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-4b30cb3c705so58117611cf.3 for ; Wed, 03 Sep 2025 04:58:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900705; x=1757505505; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+B6J/aB/tids3HBfaJNu1z9KCUM3gjNbHkRd/sTehYk=; b=b6/T4fB5UHNBaNsd+PnjtG3VwDfUIpH6GS9XZWR/WGVYwg4SwrJ56ebO0sT+PKnAav pr/hEvEizm/OnQRrKYdlxe88Mj8mXP8tzFRspwdR/4R+QgK0yxIgseGXXGFqsqz9Zqtr /tk2dzcq1MAyknszzio2ItT9JYeELcdy9iHvAF2u4u3/H1nb8bDL6K5mK2GZmczUCE0n el3GABseZlvxPkfQfpElcrdnzT3ONkJWwgodeIwnkXLB8keEtTMn4c9kVDjZKqEr+cFC BEWG+9P9NX9oio0traiPeajv66K5QgOpoJThK79Y2VjX9EYPgBEfHdapSBuAy0u4Swop fngg== X-Forwarded-Encrypted: i=1; AJvYcCUwlI7+6/wOYKx7VLJtNYZzpyg5BxKjQPF2CwI+zrEMJvW5l22QnSC/5KDUoPmUk5uwQV5607wzbMFLKa4=@vger.kernel.org X-Gm-Message-State: AOJu0Yzv4YBr+thYEVwTZZCrV06ygRdkYWFPBrzO9mrEeTGcjVfwnLGx Zb8Dnhho9PWQgfHdunZ8/PgdQ7VhbegA1mST967TNlXnfq3P2qPBOoowZ2IRpjebsIXwbAXyao2 bXX5jTn0MIMC2f0H/3jj/qCypjCQ59ilCA5PIkIjVgVgyZVDwiWeK0hR+nqZE43zfzms= X-Gm-Gg: ASbGnctxNiZqOa+O7N8siD4k7fJlE2ZBXXfVnaWpWxwXKjX8+ps8bzyd4JiA3U7a8IB q5YlnQtT8OeyLLye52PtI4SXju2G4eE5ZkTy5nyuF/zfycZejMp+KgeGOq6jZjR1lSXv0XP/O1C UUftlroKfLEyrCtY7R7T/BVbSHwxa4xFrdZxknw1WtLEH1T4kHQ6K2jtwk0kiojpK61UZED9XmG +hRftNpNKfgCcWUxL27xFK+ERLlazQ1LxMLkG9Iaw/8d0CwbGIMNX+BFwfDiNd8XdKf+fhoKWcd 6HerpHYHr+RVNtJ+vPgzn+pptaoX+bGWIgZ+eLUAuKqHTc86L1eCGd+KqWAmxSwVRJyJqidQsnH AvDXVck34NFegiIUxM57+wFl8OkqEO9LsXSz4/auRmgwS6CxyS6W8 X-Received: by 2002:a05:622a:1f09:b0:4b4:94e7:7305 with SMTP id d75a77b69052e-4b494e779admr14573941cf.66.1756900704594; Wed, 03 Sep 2025 04:58:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEec6pipCsiN4bgRNHEInH7xKrhFe7yfQxq516iB19wHmpDvTtGnLGWlQH0T9+x/MPrYZLrfw== X-Received: by 2002:a05:622a:1f09:b0:4b4:94e7:7305 with SMTP id d75a77b69052e-4b494e779admr14573491cf.66.1756900704030; Wed, 03 Sep 2025 04:58:24 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:22 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:13 +0300 Subject: [PATCH v8 2/9] dt-bindings: display/msm: dp-controller: fix fallback for SM6350 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-2-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1997; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=RDcsC0Xk/SeTiAYs2PrzT5y7v3tCHnCk8IS1ckk2ayU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1XhQYwJ1lOW5eV5P1HT18WaT4m7LdhmkXLt BA9hlGisnWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtVwAKCRCLPIo+Aiko 1VtwB/9dctctbqAzqdpymh47D1RY5EIKq+TYeq9nhWHT7IdEdFJVWIW9yFkpZcx/9Hvp2H2c1Uy /ms2Xrcw9raK5q3K70hPRtXSh+dmaHZBhxzYzyV/XfsA3kgNthtuyUBJxz71CF3EYvmttDalY2/ LXl6G2ErP7DwIbQnWOcYGkofktJLZKbviC4IGwyjQiGdlosNItNsbjuzxncmKgJ7smR4MxUsJy1 eu1OPmvBqp5CNd1PjEY0yTacTJGkDpormvV/p83MkvKRCwo6muNWM3w0ef7IT2qeTI7Cp4AMQRU kHCX9fF87Yw7hguGeHRMXQSxczp6mNgRqCHuahhTkOev3bln X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: jVb5jpkLJImyfA6Aqn5oIKIErkm9D0eK X-Proofpoint-ORIG-GUID: jVb5jpkLJImyfA6Aqn5oIKIErkm9D0eK X-Authority-Analysis: v=2.4 cv=ccnSrmDM c=1 sm=1 tr=0 ts=68b82d62 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=M9OWzbDgh-7tm28R-yYA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDA0MiBTYWx0ZWRfXz8rdLnKfmJgq +sB6gMIBjgkBrgU8OFT2JcCATOAdS8Q0S6CVKV8x2M/5cJrqSbfJ3cVBFUxlCJHJqE/cLj+GSRJ SdNshwymc670YYzyUdhU1zgdaga3LOCoqpRAJWw94V4+L2rw1ShYnT9UF2bky1Dky+XXrt+liew OdXOkT3NRj7H2E97gAuOfw+gAV4qYjjAQur860/0a+soZPfk1OY1PmiMYZdpLUtdbCXipVnAGka NHaTWtgQpl1WUpL8pDpnWsB1+9+EBsvThcwKAyp075Jsj+hJMhXcschIYrbiMNfjSW2x8nZE8mZ V3ZxVmvLDiIa0fbZX7Ujr7GC3Ni5srrfc+ZHbvoWD1cVK4hrfX2ixQm8/aNmcFAMwYU+3RNzhHP YS0/VBJa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300042 Currently SM6350 uses qcom,sm8350-dp as a fallback compatible entry. This works, but adding DP MST support will reveal that this SoC is not fully compatible with SM8350 platform: the former one doesn't provide MST support, while the latter one will get it. DT schema for SM8350 is going to demand MST-related clocks which SM6350 doesn't provide. Add new entry for SM6350 with fallback to SC7180 (which belongs to the same generation and also doesn't have MST support). SC7180 has been supported by the Linux kernel long ago (and long before SM8350 support was added). Fixes: 39086151593a ("dt-bindings: display: msm: dp-controller: document SM= 6350 compatible") Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/display/msm/dp-controller.yaml | 14 ++++++++++= +++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index aed3bafa67e3c24d2a876acd29660378b367603a..0f814aa6f51406fdbdd7386027f= 88dfbacb24392 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -31,13 +31,25 @@ properties: - qcom,sm8650-dp - items: - enum: - - qcom,sar2130p-dp - qcom,sm6350-dp + - const: qcom,sc7180-dp + + # deprecated entry for compatibility with old DT + - items: + - enum: + - qcom,sm6350-dp + - const: qcom,sm8350-dp + deprecated: true + + - items: + - enum: + - qcom,sar2130p-dp - qcom,sm8150-dp - qcom,sm8250-dp - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: - enum: - qcom,sm8750-dp --=20 2.47.2 From nobody Fri Oct 3 07:40:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91C342FDC27 for ; Wed, 3 Sep 2025 11:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900711; cv=none; b=pBrk69mecbSbW7c0ZI/i0cQf+pj4vkOMq4M8nhPC/pElugvf6vEdtRdkO3dUBXjtx+lu3MUJnrPNBXFWBY7XU0UXRWPf8bYtsl1RdKSAiaDDTYUO9iTbwerDPbUgIlsUfDwWKBXaO6YFBFd+abbgewnnnGcI6ftimtcMhLAAkj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900711; c=relaxed/simple; bh=7SN93yAhsVlIHhAjv83yfgqh9HpWqOytsXh6bquwkv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MEO1QXw6dRBl1M1j0aK7DSO6CSc3391im+CUiMzrDVWZIaQ4G0DelebAYMV2Hyc50PO0Vg3gmmGRhwQiETpS3LReerQ7h3855siOjmNpFptneTj2meM7Nsn0n4h+gsWoBJgnwA45rnwd/HjZKQhpPZ8bwJBHhLjx6EjqyR8BUjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JyskRiBb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JyskRiBb" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEwtB000792 for ; Wed, 3 Sep 2025 11:58:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= atpsxElvXgCLWEtnfNMUFNLYSDL18dufzTm3oOR6c98=; b=JyskRiBbpjmESb46 EDPO31Z1EZ6yvegcHcH5dnSFNCxtWKQweEDJiHgII5QuNkgrqz+jiyEukqN5+ZZg ODBPnlNl0Q9itxQvhstV5cVyfsurT9JDf+Ql5+L2VmbrSLjCQRY9ILs3m052p5y0 xcOe31KxSvXy9T8oQfx9f3XlR0Ikc5H8uzUqNw8gBlJllJOjRsumjxgW+AphYR0g 3hl/KaGrvk8E9kf9WO5BCX3lRE6HRMSsYctWj7E1+FMr0IzH6sQKouRhBytHkF7c 4SrhuCfWG3+EHxuM18Xux1+Vm2tzcymxAditpe76q7TWDLXW2giX0PYqSY/H+SZV mxys4w== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48ush33d4p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:28 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-4b3349c2c38so76168121cf.2 for ; Wed, 03 Sep 2025 04:58:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900707; x=1757505507; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=atpsxElvXgCLWEtnfNMUFNLYSDL18dufzTm3oOR6c98=; b=qOOKx8mGQXALRyyGKKYjrzMceY8VRybqcWq3hjcAqm65qy2cAzPEN3RAZYoF8DlL/g sdCL8DENLGGS+/eCFimfhpguIQFSR+1W5YGQAY+QnfDtRZF9OVDnMFzlxmjYi1f7cf/0 WTvT1SJSYozJ0ohyW/WYN1uyQ83C1Ky3p6hwUGJpRCl9bEiXaLSGCCMhmiUTg72hko/N VBFKaJpiRMgbCzeLKfi9/OGWTU34lgwVSbd8O1lmfGB0oJgP8fpwc2E/eyrNjlw3ooAg shYmbh44dZe9HkhFsVdozqkBMBw9r140pTNwS4m4GOcr7w4KVDj0a6ZUxOnunA9N7Rpi z1Sw== X-Forwarded-Encrypted: i=1; AJvYcCWBq4FvkBd4d2U7a0Oc+Qs4INS0v5oP3WgIR7hvs8DVhaX7hvR12o7sSru75rTfVpNp+scxIati9+Pejcg=@vger.kernel.org X-Gm-Message-State: AOJu0YwDJwEyDcfCzQUJ21UXZxvXNJw6VSZPohqaGZCbYpakqGJ6iQ7O 0v0R03BG6EsPNAciuJrrVjj35G6MSoWHOtHmRuWCswO2Uc1CpD96I7K/33ouZjy0ulGJCnWrX3R UxRFTQLhJY4rmuxKHEQxFAi7lyd2gwcMSQ654GqneS+qKGf3WIaDW+muuXU07LOF3FBA= X-Gm-Gg: ASbGncud3XRyE4Cr3GRAMWCVH/Sd9LVFd2P+mV8T8wRB3sdMYN5umjXmydTFz17roS3 KTmyAsHRc62FLVCmq4deuAXh4sli0uE+rJOK0lgSGk6Sk4LgHYumyQiu+AFyS+EAyCIEieSktlY Zyla4SvZ6ZCXbSvAG1bUPj1TIHblaFZ9zkOjaisicKDOU0CEzjiw3n7MzCdGXvoJNHr6xg35hEa 3Cq2IOxFZoCH+hpjcJY/EL2mEMUJw9rcfCU3zpnmDaJvyfKCYv/jaugwXFJYmo0CRT005qkM849 ZGXV6+pRM/HvdiUI9AKlu5uX7rezE4JPwh8bhpflh3YxCbv16oJcVW/cdj1His4rrRdLvKY83fX Q86W3G9CX2heKe53sQDp9ZfyxlY4pVQEMQMRY2Ej33EWMp4pXqCaS X-Received: by 2002:ac8:7d03:0:b0:4b3:963:b3c7 with SMTP id d75a77b69052e-4b31dcddb9emr153033991cf.80.1756900707148; Wed, 03 Sep 2025 04:58:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEb+EMS2bgzjF+wonzL9M5BRn88S64ov/ovDLLFNBNiMqEsjMGSjj9Gp5N1zKTttlgvTkbhnQ== X-Received: by 2002:ac8:7d03:0:b0:4b3:963:b3c7 with SMTP id d75a77b69052e-4b31dcddb9emr153033731cf.80.1756900706608; Wed, 03 Sep 2025 04:58:26 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:25 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:14 +0300 Subject: [PATCH v8 3/9] dt-bindings: display/msm: dp-controller: document DP on SM7150 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-3-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2083; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=7SN93yAhsVlIHhAjv83yfgqh9HpWqOytsXh6bquwkv4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1XzNKs3KOvrfNw9T9A5PinobRn6+BUmHYpZ AbXYmzlA/2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtVwAKCRCLPIo+Aiko 1fDkB/0cdD4STyN4uofga6hg4Afg4alqCVv877OF09D2pr1z2nA5rdLzvmgnUcMuCfflk0wXjHJ bXsEEaz14lZtPp4J7G85o7G9VjPzwXeS+sUHRbWrm9NXR+wD2RcdMefCPMdcbueKkVTkQYgbgLf 1FJVNEdeUy3cTxX6eCsIthEtfOSBCKGU6DvSa8D3UYbrbIpb3au9HwSzcrQ136I4QrjjRc4qZlv 0hS9T6hv06o7YlXVEKtOOtgPd/PmvrYjHbiN1jnXrHriCAdu7gl5s564TQ8jmumSQFQB4GC74Go dV3x6hMYJ103JuT1RIOZFoae1XywiZB+ZJLIyFcu8cy2FZ/J X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzMiBTYWx0ZWRfX+se+vkQJBqIR ZWDAuotjtH4pVLbDZ2SaSc31GaV4zeOznB5Mng9UbaMzXriaNIQY3//K2lfmsDVtbkNx2jN8DEo vQGgMbBNCY8fxp0nDBh5hfjm85lTpwL3bPYlaEOE+CfVSzGH5PiHyR0MH7fiQmZ3FK2tLLxQ3MM ktPaccypGoAihg9FtM4YH2xCVWgRRoo8bAeYvHHJZRzhhFuZxZ5HVAYM0yw37y/bmcO/gZGEphd kTpLcvWvflWy530Zm4sxMpdjiZAV7//d42QktI/WiST+oEJH7rgC6NpzHFvOvM/UwE9lgPAbaeM 9QkNQH720ughCKBbTUruzlvUhJUEZyDU2PrpstoaHwOX4IkQJAUKO6dBIEcv8TYIiysFI+S6hK6 hitq+85X X-Proofpoint-ORIG-GUID: vMdwAto6eeoXTbhLuOkpz2g9WTmUdaNs X-Proofpoint-GUID: vMdwAto6eeoXTbhLuOkpz2g9WTmUdaNs X-Authority-Analysis: v=2.4 cv=M9NNKzws c=1 sm=1 tr=0 ts=68b82d64 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=QYKTPsKsHukT_2dPOMMA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300032 The qcom,sm7150-dp compatible is documented in schema. Mark DisplayPort controller as compatible with SM8350. Fixes: 726eded12dd7 ("dt-bindings: display/msm: Add SM7150 MDSS") Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml | 6 ++= ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 0f814aa6f51406fdbdd7386027f88dfbacb24392..a18183f7ec21ac0d09fecb86e8e= 77e3e4fffec12 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - qcom,sar2130p-dp + - qcom,sm7150-dp - qcom,sm8150-dp - qcom,sm8250-dp - qcom,sm8450-dp diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index 13c5d5ffabde9b0fc5af11aad1fcee860939c66f..c5d209019124da3127285f61bf5= a27d346a3d8a1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -61,7 +61,8 @@ patternProperties: additionalProperties: true properties: compatible: - const: qcom,sm7150-dp + contains: + const: qcom,sm7150-dp =20 "^dsi@[0-9a-f]+$": type: object @@ -378,7 +379,8 @@ examples: }; =20 displayport-controller@ae90000 { - compatible =3D "qcom,sm7150-dp"; + compatible =3D "qcom,sm7150-dp", + "qcom,sm8350-dp"; reg =3D <0xae90000 0x200>, <0xae90200 0x200>, <0xae90400 0xc00>, --=20 2.47.2 From nobody Fri Oct 3 07:40:22 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF332FDC3D for ; Wed, 3 Sep 2025 11:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900712; cv=none; b=aTAJcbEifmlY++a0yMht3EjBeEJGvWXCjRz5+HK0AlXArtEiuv+x4f10A4Zyeo6iB99mZCUwYzFQLB5go4e9J0tBcCL7+No7DhD6EkK2LTVTO/KKGjVAXRB2SL8E05Oj+I/9SWkPkN9FWrs+O2Rl08KtITf1xul+ZCeKtRSsa2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900712; c=relaxed/simple; bh=a8ke4j4Y6LPEDYk1jRjeU6q11tENi0EWXo++z7UB0Dk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mHCW65ErlmyIJrUKACN1QTuiL+6Z2CHcgt+2m2XjgsgWjM5NKQq6CGK5V8wxWKKOw5O/p6NFeZlSXVGDmEr6slme89MUubq8HCxRRdTPBZ7cqjSukIjZRDq4OqlHOQsrBWkvaA5sXloja9yYNooOh5NIj3PIc9iKMiwFabXWfsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=lLSwWccP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="lLSwWccP" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BFpA7012558 for ; Wed, 3 Sep 2025 11:58:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9CzfHCqMGwSglqPBGTXjDnFh1Uf1qA700EaDFGkGlqQ=; b=lLSwWccP/S8X0gGs /cG78VTf5BfHVkCrsLKglvpXJYWGlJVm6hGZ+2P6SL5LUHvGPYTeT+4n0jvqyYCf bCVetzjPN1mOQBbteGN4fTSfpY791tuEEV63CpEO3Bbxm9yuYmLw3LCYy4a/8qi/ Daq6/J88J64Z279Ta8hLhVsbtFmXmhmyIlb4XxT9eC3T3L19bUTgtVt2ZYhU9sI+ r0N1nIykjxUn90aBK5jZkmb8EnLKvGTQVN1BHrf+kZHpKqJ/qH8wQpZyWApHFRlk lo9gOF95G53aMS74mvc9POfiosXmkc3wr0Fm9deoUfNgPFszqxiZ4BVJ/mluI87G pkvsyw== Received: from mail-qv1-f72.google.com (mail-qv1-f72.google.com [209.85.219.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48urmjkfqq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:29 +0000 (GMT) Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-70faf8b375cso79540596d6.0 for ; Wed, 03 Sep 2025 04:58:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900709; x=1757505509; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9CzfHCqMGwSglqPBGTXjDnFh1Uf1qA700EaDFGkGlqQ=; b=xGQOx0PfvGsiRUswG1+KtMTy8kqKXozXOI/SvU7ASsetHuB0fRZsZHvCIsWJU6TIRL XN2lENtmjHQ+uIBSbH3Nl9t97WJ28S7Bk0kmuY8P9r/VBQXP6kPwkWSQNwJZDD4dZ8sr K8wLgyOwL3RNMx5eFxrYWy3f/UxAUM076FT4Knx9gvERoFC6lefExWsIc0qA3R+WY18D WyaUQnoR4qeus0ENcaIXl0etX6jh2BLeyOx5nT8NbecC6coXbps205RiNDBOGqLPJy8A LXcYj63jDIFkqS7jb6gtmbWYEzB+h+3DDXOgu7tpt1ZzYe5HlXBLnspZ5vXwOaewhNJn rF/w== X-Forwarded-Encrypted: i=1; AJvYcCVPJ+nEa3BeIktqOrgEaePWidsAeYF27p5ILFhn9NVMHiMy8gg9fWxLUkzwNgqsC9fFw1kfZt87cKBXc3Y=@vger.kernel.org X-Gm-Message-State: AOJu0YzFXULg8c+ldcy7lIAdQNc1Sw3OWaXVLk8/Dds7dDwGTMV4aNRH CifDPOMtKa6tQq4uUzzGZtkPertszvINayPT49a1zZ1gHQvGrvmeU/cXmdFF4SWQOp1bQUmcDp8 lzl8yMz2vqhKYZjhHfATTXz+iILAs68SB1DBZXeQVPiiQFWjQ2ObS5x1aV9CTOPh3/3o= X-Gm-Gg: ASbGncuqYQkUrH77R8WbhW46e4thzFx73D6MAfI5RFMWsRqC1WwAH5870kILGadUjsr EnS758a/cdNWWSePi7ixcbAvPypfiCDi7oFetyF5fnYMYvFTDbIBtkZIDKeRkk2XzDgq+r223mS 5U0RUD1q4bsLZlfd3M7HOkoIR4OSfRx3O/cpxbDEFXBt8gyeGvKL+KzP6Uf5vgRwwGdQ4n9Lb0R oMReej+3bMMBBBOgoKhppVqF3Luzw8YElNakV/qjiFflalylxeTIK4GTToLAZA/eIGYmdD8c53V Z9dVX7/8Es6NLvH3PaslSz70rYpw1TXlBjTsmgtSSn3UcanR+UgKpOFERhQ9dduNDtr9ehVz5Mi LIA5+KDA4NKrj0S5XgBfjkbABqbRa0U/JLvKDQo8022NIBKkEOfXs X-Received: by 2002:ad4:5d4a:0:b0:721:f7e3:b339 with SMTP id 6a1803df08f44-721f7f2f87bmr56508916d6.59.1756900708651; Wed, 03 Sep 2025 04:58:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOxz+WdI3lYa/0i/KAsvn3bz2F3oaUn75lIwMhkLzpHl6K7aeiGWJnGPQJrpg5cLSzZ7bzBA== X-Received: by 2002:ad4:5d4a:0:b0:721:f7e3:b339 with SMTP id 6a1803df08f44-721f7f2f87bmr56508616d6.59.1756900708191; Wed, 03 Sep 2025 04:58:28 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:27 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:15 +0300 Subject: [PATCH v8 4/9] dt-bindings: display/msm: qcom,x1e80100-mdss: correct DP addresses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-4-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1755; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=jGBROFXef1Ek+8wHh+Y3Ci+prYLBgIDZTxGb8ga6KTM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Xu+km2KutgPERGGGo2kmA5xB9BSqQJXCB3 M/GRKa1pVOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtVwAKCRCLPIo+Aiko 1UVLB/9YvA2KNMlz3x3H5+BzWFNN7BkMCqdYEVllZZdSqpy+8dpZskxN/+586UCbKEPZGR0bPZn 4rdUTsDG39PBRf3R9cGWP9e7Do/37ULaPUA+o4+nFcT/twphNVdMqEnAo2gkQqa5hTaxiVmICN1 TFmroiajto+0rDQ4o6RG2zC5CK4hHc7naZKZLLmmo/nRz+qgbXbPRIAJdJw37Gxy56us3l9wHQK arLxfpFM/chb466xs9VErsOjWEL6he67ag4MM6Nn9dZpv5JacZHqPxwqbKIydIXovMXjAtc/gwy qfeQbAL43bMZLtSmzet3FrhNh6lpd/0IQS+XaeiS7V+FY8QT X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=OemYDgTY c=1 sm=1 tr=0 ts=68b82d65 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fvGZ3mk3BhhUN7shqj8A:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: a8HgRGUXBjZ7w6oTOf7001Jg0gXaYU-3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNCBTYWx0ZWRfX4oZ9WBvQPi1m Nytfbp1OsnKS/0G4g3Fcig9e7NOKdvJK+fCq969cak00iDXa4UIkqpu3LRsX8HRfU9QczFlFTzo sgdwXeGd/WWXFlawJFIOYrL7farauQi8MLDLRPbn0XkBZjzhqd9ztlu8LYw+DMXrskHVFwlK+Pd mL+2S7U+RQyHdiPIZL58RB+yqiYssCxxKNPyeUf8uMb6Vpb5ZDBjkNKCg216dZ/vBrttLSxCcFI EsM6f9sA0kAu0my9KQHexFbGFN6b0fxv+5ipSk9XawgiSVi+ip3do90eICzcBM6YdqleGY0mZ5B ZKLj0uEsYaxnwdUSSEjRDzwzRQdySuFKwmn6BbMfrSV218s8onVwWiD848ao2IIH4QQPlIOI4fq cooX1DyG X-Proofpoint-ORIG-GUID: a8HgRGUXBjZ7w6oTOf7001Jg0gXaYU-3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300024 From: Abhinav Kumar Fix c&p error and correct example to use 32-bit addressing (as the rest of the example DT does) instead of 64-bit (as the platform does). It got unnoticed before since DP controller node wasn't validated against DT schema because of the missing compatible. Fixes: 81de267367d4 ("dt-bindings: display/msm: Document MDSS on X1E80100") Signed-off-by: Abhinav Kumar Reviewed-by: Rob Herring (Arm) Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml | 10 +++++-= ---- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.= yaml index 3b01a0e473332c331be36f7983fb8012652a8412..e35230a864379c195600ff67820= d6a39b6f73ef4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -170,11 +170,11 @@ examples: =20 displayport-controller@ae90000 { compatible =3D "qcom,x1e80100-dp"; - reg =3D <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg =3D <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0x600>, + <0xae91000 0x400>, + <0xae91400 0x400>; =20 interrupt-parent =3D <&mdss>; interrupts =3D <12>; --=20 2.47.2 From nobody Fri Oct 3 07:40:22 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C5A22FE072 for ; Wed, 3 Sep 2025 11:58:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900715; cv=none; b=sUHkpD/kZgAmALwjMQohmwL9pomLJxI9bU2jffrrkf6HmJBBpBNpKZ1ujri8Q8cKMd31e8tJaISfK2bMoHjDUBm6W5QtKaTARrkRweftAN8Io3frEoWPm/9ChInsVniSZBTklx4zEp+KFkoF7clRHOEVOrjAyYfRuCj28D59Izs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900715; c=relaxed/simple; bh=xYiJqMlXkF/RmUEDi8Jx/sYOhGWXsP+4BXARGjRG51Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LPQQ7rMJ7mT50E1Vw4rbHS+bNn5mfsPq0iJhKA9uY42z25d8ZstrQMQLZdrRDe927R3Koogn8jaIzR/AcakARNdc+xRd9RtQYg3Hs6gpRMyfjDPwo0U5+TcT7TgChkqrEfNThg36aQxt62Ksom2j9ThC910h7pzG4yfVziF//Xc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ntQiwgTd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ntQiwgTd" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEt5l001969 for ; Wed, 3 Sep 2025 11:58:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= DvS+pfSkiXK4ob+ewthYnY+XCoXOveBrZR1sStGKsLY=; b=ntQiwgTdufLpb0Zl mWz+4Kvk/qRELcJZblqrIFNw9oARFmbdNAN1dOvp4iHFwcNHaJJ2z9f8F+WCDXw3 DXnn2aImGRVi9gHSqOJ+NjnxSMqaxVgIuh0yKseq0MmE6Ty5Dg4yYGE1H0S+/jCM CfMtnxrN34psB9slJReltftm7v9gVyYqpmFF3CToIP1ozTCxo3ALyfd5GuuIE/V9 /gChH3SPNa45oH8BeLGvUsHBMcWZFuep9b9iL0gvZUKY7uJ58VAw5wtFBDK721lT fS40SjLjESLNk1AHpGvL1DT3+kqyaRj+3V4SxpetyTObR/N+Ui8Uc9/uMIlXiU6N oYnB5A== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48urw03k1r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:33 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-7131866cdceso82513196d6.1 for ; Wed, 03 Sep 2025 04:58:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900712; x=1757505512; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DvS+pfSkiXK4ob+ewthYnY+XCoXOveBrZR1sStGKsLY=; b=JRb8/RBwGmjlYlohdPt0Ri6iMb3xD4iKo6BHqNdwdiu7l9vmZ30GQpR4hyv+LLJki/ CsSFYGfJ8D1o5sx42pxaTL6iMf2tNl5zhved7ce6/+YhHzx6oKU3nLuSVieQLo8BwL9h pN25JzDR+CCrQhW/mkcuFSD0C6/g20Zuu7dRAdy5IeYXVkj2ySKKpX7rIyJBeefSANMn FYXhAZl/QkyKIhn91sBZHhEsKt5EmJHzC0YGpAJJ/oBzooEq1wA5yG2Gsb+kt7ZVhVFI AbA8b4dVNX+Ut/3thKkrC2RoSb3t1u5pPyvHmrBW40Hghuv3mDTlyINZ07Mb9VHy5Pki 8C+w== X-Forwarded-Encrypted: i=1; AJvYcCV40pY9uSSqBzOg4IyWJqaOd148VD/XkN9+G6eD5hTzTAlW3Xkf2/4d+FMMPGaDmD/nvWELEZin8OXlvzQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwbdOJWcUpd78vexDyU65Cf9xQCihwcl8oyBZR5cVAmXnRC9nVg M+p+6rJQ1GLROySKzDdgSdojy2ik/ueAzjIS2kn+EWExI0WvaCYTEIZvJh6WzwmrY7RuJq6Pqc6 0+x/kX0n5Ku2QwReS1m9vqn7Q4wXTlH/fu/RX0AZlabLygCX8JGqe+9AYfFatsAE5uoo= X-Gm-Gg: ASbGnctjR4sEs8UJ3mdiMfzPFswO38bOk4YXQ3wxAQq9hA1+0I+Kc4YBh3j37vh/IWM TJCDoUjVQJ8ylJUW4tfE07qhYv8DsLxBvpyqR89dqSfg8H/T6sgjY2yXuC4fLkmVGtsXKEjKOjh b78n3Cq+IrlMo3cxuOhWtbnkKf4quvqnxDfvmhfcWp4S4WqNxbqqdCwI2eExu5sG8aHZxJm5x6a 8L04tCiIVQTXaMy7djICpBGCUnplzYQzQ6yp7JNIKm8qvV0cQjFcagLjMCLSukaea/ckShb6GVR XKc1Xv1YEujb6sNQxiumeBn8lkxzYHks9qlIY5l6UAbVlr0k1Bbwtn8Q/FMOwekZWgYh6187h/j 0j258gPj87hufrZR6xYbiqggZ58z9UHLw1thWAOXWwlEwYq9Hi0Lj X-Received: by 2002:a05:6214:519e:b0:71b:af61:1348 with SMTP id 6a1803df08f44-71baf6114e9mr91601266d6.33.1756900712297; Wed, 03 Sep 2025 04:58:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHEi+tlLK0SmA7ZkkpLzHXvsKU3NqR3R6ubhnPBQsbOGPlcQRBLwWi+D2yJKn/0+PaaiwTqSA== X-Received: by 2002:a05:6214:519e:b0:71b:af61:1348 with SMTP id 6a1803df08f44-71baf6114e9mr91601056d6.33.1756900711843; Wed, 03 Sep 2025 04:58:31 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:29 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:16 +0300 Subject: [PATCH v8 5/9] dt-bindings: display/msm: dp-controller: add X1E80100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-5-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1325; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=UnKbj8oV/I2z2dmxNHPVYZHaNtQSEhlpqnpLKeNGplU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Y9YD1JgINpCccE59Jg3NJTVxUNq7VK3C9P zTiqZYhZvCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtWAAKCRCLPIo+Aiko 1elkB/0S26d6iuoLR5zz4fqpDYtQbGuszfgEB0ByWRteyw2h+acALJqub1jjv5QbeCJNQ+kn3qa iyAQB4n7rXkeh68FuZCRJVh3NfDY0uf942HEkaWzhRqly+FiZdyS4g9JsnYLpPxiYgVhGXxUn59 VWg6zT0Cey8UA0c2nLFTooGXgbbcvQMIWTJmCk8hilPlIZazmr+SFwREXXeGStgYLHo/wA1cp8k pIqt/QhC/zfyiIXxV2arNZ3BxHTkmYXpFl2+ywk4FF2cpRckJ1tilrSR0RZ1/bPob47o64is3gN LOGKezrr0bYlXp8b9yi+Zo6LVGTiqwHP4U67Yklt/McRGxF2 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 56N1re1ZECW8SVhgc64Xjv1hDnDUasFN X-Proofpoint-ORIG-GUID: 56N1re1ZECW8SVhgc64Xjv1hDnDUasFN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNyBTYWx0ZWRfXz/uPWNjG+rDL 2Yhyfg5CpG0VTVu92mKdh9D1VTGItwEXYaYmBER9g4EzyRJmgwcquz3YFuS5V28ePl0uezkGEjz 0jIeP3uL0zIwV/svLt+X8ns7xiewc8Qx4+eO8SG5iX+a3XjusAXKXWmgHinPTnJY9bM7e4T36FM lJbqoQShZogRjK346EoT7Fx+ZtTJCzz0WO452jZauDo5GdVXNYT30N3ai1sLsgHGVC8kQN4u7Jy o14rGF9IdAViklXMGzxfbEO/Ct1tZNwehbt8ZHiTc2o9OIZmUstkPCYQHgs/rFJ8ygid5ZR1lMs a30FjE14T36cQVZUqOXOgR4AK8arTTukHDAysS3EOfOHuGAG43k8a3Rb7wVWFftVRjXBjDFhjft ZjHLMtSo X-Authority-Analysis: v=2.4 cv=NrDRc9dJ c=1 sm=1 tr=0 ts=68b82d69 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=LXTjkAqqvG_e-hvHT3MA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300027 From: Abhinav Kumar Add X1E80100 to the dp-controller bindings, it has DisplayPort controller similar to other platforms, but it uses its own compatible string. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a18183f7ec21ac0d09fecb86e8e77e3e4fffec12..6316c929fd66588b83d3abaf01d= 83a6b49b35e80 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -29,6 +29,8 @@ properties: - qcom,sdm845-dp - qcom,sm8350-dp - qcom,sm8650-dp + - qcom,x1e80100-dp + - items: - enum: - qcom,sm6350-dp @@ -193,6 +195,7 @@ allOf: contains: enum: - qcom,sa8775p-dp + - qcom,x1e80100-dp then: oneOf: - required: --=20 2.47.2 From nobody Fri Oct 3 07:40:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B40A62FE59A for ; Wed, 3 Sep 2025 11:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900718; cv=none; b=Bpj8f8FGR+AafnAk/MT44BsZzy/vix5SY92SMaICzJUkc4+T4MsKZDVTL5EjnV5QKOFPUo3PvAdQwiVi0haE9D/nwIToTMr0r0G+TX+wm2EsrDPEBeSYI/jBWBLnnr9zqtJRf7+fP27vdU/24l0eQ2Edsmq3NUOPRHi4rYgzgvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900718; c=relaxed/simple; bh=lBevXKdHONx87FeX9ms0nioXAmeKW3/lJZ9j12ovv/o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=scOHxtecpO0t43zEmhSkRLpg7OaFT/QZCSaW4bbJaIL4SO689N7jTJIbfoUsdJv2q2gwIGMIZpKH1/QL9Yr1qVN2V+Q+xreA3sggfGGEVj2faqBslpgEXdg9XVG0u8k3baDVcdbc1NUDuebistQUCV9foK0O/BET9A/1/ZPYCp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PGCgS2Jx; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PGCgS2Jx" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEw2Q022414 for ; Wed, 3 Sep 2025 11:58:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= H010azYPB1dFkM9rbItrhry3MhtWqv6s9ueklIrUJck=; b=PGCgS2JxDn39MdJk Qmtczw8VuWP0yZlwY0GANOUIRW/IpSK81WY9Hp3T071cxMSqfZW46dT9bCHebih6 q/DITlPq5X1EpFSkdPUd1Mchz31GCkMxZpho0Nf/dFH9k48gCgwW/GE/3bm9byqR BZDu37Tl/TPaO6/yzZY2otYquvghond01k81FVmDg68g/y0N3CgFflo72Nhz7SK2 kPPcAzg5fePIKjrcy9V4ugQmjgs74vx5r1qleAsNgP/5OrAPjit6MkP0+6WltZ2P +DAgJpUOFZl2IcCMQ7qwN14GaPKzRFIWd3DMinaVKo4HbYEM+5pKPgQTcAQTTSYK SEscyg== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48ut2fkdx4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:35 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-4b339e7d107so56973581cf.0 for ; Wed, 03 Sep 2025 04:58:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900714; x=1757505514; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H010azYPB1dFkM9rbItrhry3MhtWqv6s9ueklIrUJck=; b=rY7AjO2THxvHDY272GLA3aoD+01+qznEyUvhmubOqic+5zVfYO1SkUHYb6Kb9xq1Si GY70G5yWsqKEdGRQ12I3MmccuGPMzVE6E8PGFNM0/quaoSMxBpVJj3ZZKxGSi6jZ8TqR SgJevtYkqagA7H99tk9Uhj9x6ZynQRysAfUFJ2CuzhNcK3RcZE8xLhtgGabjDWALAT/j fjW6tVQGpgRg4CcYLfuOqi2F3cx5eFmd7GYQvpMUyQVzUWyVo4sdxbOabc7h+ZgsdKOz FVhWona5QtbJfBjc6z3EUzz8zvdHYitgpuVNFVB85ZDfybA8021qmvriOg3iCdEezpBE reag== X-Forwarded-Encrypted: i=1; AJvYcCW9mJnk+AItWsOoMwzDVjImLNttTNEYGOtWTjQZch+S3u/5HMdo3NG4lDcrdFgKK0v/Ywmfx1wjh3kASyE=@vger.kernel.org X-Gm-Message-State: AOJu0Yzs7FfXB3haCCgLRf6OGVTUvJR5hfochzgLwZ1TMRiA0UJIdbeW E0yabarpAldVJ/+lZ0if8klARy7qcKjm0KVI5nZgb+8/+030SDrE+RAGig2CvWCz1rYnSkE1szA qM/90+bd0ckXZwNHRCRle2NLGowQLHzOhITprJy9k+L6orjhxz/ATFuWI9rA91svPnYo= X-Gm-Gg: ASbGnctg9aAWSOC/fDgtWPS5tkNxbIo6SGohDavVuljYSpDK4k7QFMm17JKEVKGsh/A 30wlarNEvoLkfjI57jrkHvj07HfTygq4w/CucKY5pfcPNO8wNTihUt9anbMi/FkPqVvoZgCfF9S oE5PEKCn2o/yL3a0p8ZN67R2kr2j8lbDWLk0wvMGMulx4NVMVJtBhhFpGX6jjdn3nh84p6TDk0+ If5mmhua0eKLOIvcidc2WwwTL+KBcZg42LiL4xXGeHTVBTqkLRwXO1+GBLJ1Vd56SFWKxEdzQlT KLWvuA9+6zBa81SgIR3b1M/m/YdGMzOa6ECG6rk7f7RxLt0dMKo+PawYwzQk/NR/Rocl7Osu6dO gJIrIwp53IyYI5MMlQv1TCt7kpnmImw5YxBkzlfgtJcPW1KnIO2RO X-Received: by 2002:ac8:5708:0:b0:4b2:a96b:11ca with SMTP id d75a77b69052e-4b31d8c03ffmr167861741cf.35.1756900714318; Wed, 03 Sep 2025 04:58:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkGGAS3RPAQRRlAhwEn7il9NRls7BjhMAjCYkS0WjfrgqegShhrJEbGNDK0zM3QZXpoVuOfQ== X-Received: by 2002:ac8:5708:0:b0:4b2:a96b:11ca with SMTP id d75a77b69052e-4b31d8c03ffmr167861381cf.35.1756900713772; Wed, 03 Sep 2025 04:58:33 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:32 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:17 +0300 Subject: [PATCH v8 6/9] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-6-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Abhinav Kumar , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1630; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=jRBkyHcr8xMj4BTwupyA6gCqxajStjyC+O9UZ5EGgLs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Y3hkuiW1SdkWdW290s9cpICY2nNpGq9u2+ ZHdafw7MJCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtWAAKCRCLPIo+Aiko 1RmYB/9/VcpHWh/T/oWqH9QlA/WdaWLvy2U1EC9r0ItZxVKnxhkQSnrH/R515kKz/bJkz0lBrxv 5rZpsAdlZAs7zfHNe7ImD79Y+IhvUWlWpILd/MT5GHjO/4Y6PusaYedg+kJ4cacVKecLb5FAlYS zEVK8LBwv5piuq8veplWWb6t05FnF2Zq2QuqRGR1iJw4i9kK4EzInHt3n2b+7pekkGf1wqffVZg veGoMDumdL01DUrZvJP5EjIKnj1g+MmXAqRzfMGmgQG0PXINDlVgzA2ct+f2T/4IIOqF3qy3Qvp FIb+7nKcGES5MeMPVPbNLVIPIQricUltNMD3derDF0Ou26eW X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzOCBTYWx0ZWRfXy94v4i6q2dPq 4lLqHZNM8OQe4xNFLuQsoUgW/3w7P0ja45VhALZsUnhT48lDLTGtVxplxp1J9rD3ES0bYe1JZm9 olybwHdxbdSR9gr0C/3s/i/Cg1IeKiQfY3AZlomqUQb8wEP++MbTrCg/wCdIIZaUBaiwLm078Yo kRVDaLbKaa6Ww+V/IlzY2gz4viAR7gEaLE5eS6gLXX4zqJAOWtW9mMnt2DOLHlGBoiiWDrdFHeh QPJROh3Ok8cxv9zqz4zBJ5T7Kw23PoOPILyMP28a/uTvNDQry8RKQBKgWILoWMl+JQxk+jQ8j58 EwQkH9R3yVmqH83gZvBksysf3v9avGag1mxNVne26mi9VORBVj6JS4i6I0csnTn+aN8Oll9RpVe owDYO8k4 X-Proofpoint-ORIG-GUID: CU5Do0O2lUu5js-L77xG5iYI5bGxAgka X-Proofpoint-GUID: CU5Do0O2lUu5js-L77xG5iYI5bGxAgka X-Authority-Analysis: v=2.4 cv=U7iSDfru c=1 sm=1 tr=0 ts=68b82d6b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=VjVaSBsDX57WhQYIrYsA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300038 From: Abhinav Kumar DP controller schema documents assigned-clocks and assigned-clock-parents. However these assignments should not be a part of the ABI: there are no actual requirements on the order of the assignments, MST cases require different number of clocks to be assigned, etc. Instead of fixing up the documentation, drop the assigned-clock-parents and assigned-clocks from the bindings. The generic clock/clock.yaml already covers these properties. Suggested-by: Krzysztof Kozlowski Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dp-controller.yaml | 10 ------= ---- 1 file changed, 10 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 6316c929fd66588b83d3abaf01d83a6b49b35e80..afe01332d66c3c2e6e5848ce3d8= 64079ce71f3cd 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -86,16 +86,6 @@ properties: - const: ctrl_link_iface - const: stream_pixel =20 - assigned-clocks: - items: - - description: link clock source - - description: pixel clock source - - assigned-clock-parents: - items: - - description: phy 0 parent - - description: phy 1 parent - phys: maxItems: 1 =20 --=20 2.47.2 From nobody Fri Oct 3 07:40:23 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00F512FF14D for ; Wed, 3 Sep 2025 11:58:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900719; cv=none; b=EIUyOw+aYAG5tIU+nBcDw0nPHdZMGLeNhsQOx0qgaLW7o/XZf/LwXMevrFGo+wb0P0maPCXtv9EZfmnGRvLVvyQcIunCn0FiB91x8aeAxUVRLMCvdlBCGnf1ZCXFfZDLED3Wi0FG9+sCsJZddsw6whe2Lu14SOYhqdmwEBBxfrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900719; c=relaxed/simple; bh=5oXZrt2T2gFfyaDe9xWcCMsl4Quh/ruqJlZjWXyzEmY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jf8eGfvQAmPBssjmE+9uRdbXydK+PCX4XOsySfYMSei3RlU3gH5cuhTOYkf4KzuUcQlXbrgYvFZ+MPqWD6updKpRX0AzYG+g0NiE23/biUeFGZzkBT6FrJVafloKGu17ckaQm92bzywsKpQAP7LTo/uqL4iw7T9d6Wqg0lIfnwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=M1LVA8zy; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="M1LVA8zy" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEnc5013895 for ; Wed, 3 Sep 2025 11:58:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= r0xPMPdjC1SNu6J74OSyptSDeIyByGI1ODski72XcQk=; b=M1LVA8zyE+wLXtXE kKRT1oFTP1GhLEyBQc8rWPCOopFXOjbYaHaTsZOzy7Fzcuu9GVUa/Ozd81KZ4i4T E8y3PBFEiGJPuvbVMWB2x6DzP8qx6Kyjsb25BzOjh2BR4owGhTvVLwRZ8TQInr65 rGSaC4Lnm4/08GYs70fxqyt78oDWqxtT7pdON+WwSQn37lv51vvLh351X7eKv0ay 6ecOUrAWph2k/FA7echL3RvPJaEJYvjmaZ/spyZa4lis+eIaevUACvP2xb7If4lF lFjYjN3r+1U/qV3GlJr5N6ts2i8kE5J/ruIIXbSZ0jxlYJqc/1JBkyUNfd83JGzE 1Udymw== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48w8wy7dy5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:36 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-7193fc78b47so40660136d6.2 for ; Wed, 03 Sep 2025 04:58:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900716; x=1757505516; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r0xPMPdjC1SNu6J74OSyptSDeIyByGI1ODski72XcQk=; b=kjnIGICm6I03Gstb/dV9VDqWIYGg1rcpdl64o6oEbWYT0C3cL2DOnN9f6ruPeKeWYF XwzaXkweEywpiVkoLi38+E5blNTpRUBd+7sMQ2fmu2XL9ZM4+u5gn1zWOcNPpAd6BK/B aZ6c+4nzTUajN+LeZDt+YTWWIZxsiWFL2yNIH0GGwV+uRxhQSW2A3RZS7RnWfitvhPgX 9Yb52j3lVoPkASqhxsh9izpdHY8VucmzXzNnaMpj57cgUdoc43pt59Goer8jLT0DxuiX M6BHuhcqUq+eK2C1UJCgonkT7ej6lwrOPwR5CazDrGtzk1QiT1yqUpFwznbptzjlcVaJ GPeA== X-Forwarded-Encrypted: i=1; AJvYcCXlqmVZ2Y7qJl6NKwpscGJStpH6tXS3R1wsB0sx6Gqb+kMLSrET4T13QYlKCZchpXjNMJ6CZmJ+3im5zOM=@vger.kernel.org X-Gm-Message-State: AOJu0Yyg3BiJ3sB4dnr3tuK2Gh7MCjoWg5c+5v/WIbitx3TDywbEzHbs RANDb8JcffrJ01pWC8p5DVhck/3f+qVPfigJABh0Qwovdq6NFlu09G47hZLbeBIqX6Gsj2Uyolp Yj4TYsRkhQoperh1KpVDZT6u2EED98khkHmUI5Il+BvqR+O3GxcYXkIJjRQFU3+qqMOc= X-Gm-Gg: ASbGncuyv/zfyaKxf8AG567T5VqCoqS7m3j38/nmUpXM9Rk0X48WluhowE3zgo9eLVQ rZhPJB0knlHQrz9fbqBjAcDGNP+f67Wn8yOwIp4m84IP9hpJcuTBcc6xtH2ekIiCzcnsfPYmlDl eXuZYqlp7XAKEDeZ/3rXeZWNUaeWrzqgh14rQZ24PbKhqWZT2b5yfK8LNw7/YYR5q6Yt3F1OD2X rkvFlAmjh7uWsopy8P0h6JCx6VOiBJbzm/e0fzTSD38Wk9UzVqCZyrAaCYcz6URQfcbCWvQvc+8 v/emx3flUzoCtXeH2t0K33GN1JOayFK1L7AG0oBtWUrV94CF/X/ayUyjf0fRhWKNBchc2dWyL5+ X+iRZmfxPNXcMkFvwVHu/bRET6aEXJs2wS8TlJoRjFX3vO8vbho20 X-Received: by 2002:a05:6214:d02:b0:70f:a15a:9262 with SMTP id 6a1803df08f44-70fac913518mr156788436d6.51.1756900715739; Wed, 03 Sep 2025 04:58:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF0SuucAVxarCRPLTRQqLCBZ9vgTwGAR38CNe/suqV5ZdIiT7GcfkR7BtO6JAAehjJ+4N8lVQ== X-Received: by 2002:a05:6214:d02:b0:70f:a15a:9262 with SMTP id 6a1803df08f44-70fac913518mr156788056d6.51.1756900715127; Wed, 03 Sep 2025 04:58:35 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:34 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:18 +0300 Subject: [PATCH v8 7/9] dt-bindings: display/msm: expand to support MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15159; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=mtHyzGTb9hrM/WTe1AikW5eypI0AzlUrgR71ld9KC4w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Y/Ov7hP+0RfhsbREPtQrI7EbtVDbgL2Mnb OfGf0ybedqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtWAAKCRCLPIo+Aiko 1XbICACH7tBodo+5AqLshUai3suEs3+I6C/qFG56DfxXrBFYVPzokXXb0BN9PXyh4d6R8Re8J1i 1aXhp9ky6a5KA/rWByQynQ4BRthTnqmKfWbvuLHy1DkUgFN0qQFB7bJDeO4VsVmwEELYKbgJEHR O3e75omP2lDcYuMiyoeSoeo+SF5Y04Xw3lDAMjHA1AqAod7x54LI2rIs2YdJ74tB2aHIK6EJCHT 6Y7OP7DhZqvdJ2NrJ//L8rzeR/Zta1PAwFy5Pxez+uiXy9XXv55Xh5iTnx8uJ+C9YFMmGWaYC5+ nADFdN9PUDG7KMERXf7B4Yva38dCRRhRvQtmJhqVFxtBW/a3 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b82d6c cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=uRafYTt1GBQvBzODlV0A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: KNFPQJ_Aqc-ZqZtMc0VxKr3IkXw5tiUL X-Proofpoint-ORIG-GUID: KNFPQJ_Aqc-ZqZtMc0VxKr3IkXw5tiUL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfX/vmkgJHBY1lZ tC2BIK/XGuotKbbdodvAkgxE7m6J1OGN1ZrUEblzSGhWEU2Nm2BoFcAmq7oo1h7PwXdoBgZwvWl lhKXPmx5HVxx2xiXdticRC/qZlfQKfI89o98saSy37jxaENijDktOoQOZwpr2p1eK+jzCshqexI NGRJR6hBc+dYUza7PwKCOTIOMQHauRdVaNjFJ59DwV3EJi1Nmixe9uUHHo3Q2y576nIICkWOXz0 J6qvHUN4YhuaTr6XOoJCpvUPY7hmBZg06k+VQZcFBaVgR0REbN4W0LpLZXFiiEeWlnRmArrQFYy +t5iXzr6MMJANkpAnLcvkd2pPiAUp0G49m/gE5aYIN9vmn090IaQ6R8geOZ4Fj+IQ5fkfI/xhR9 qqRrbLm2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 From: Abhinav Kumar On a vast majority of Qualcomm chipsets DisplayPort controller can support several MST streams (up to 4x). To support MST these chipsets use up to 4 stream pixel clocks for the DisplayPort controller and several extra register regions. Expand corresponding region and clock bindings for these platforms and fix example schema files to follow updated bindings. Note: On chipsets that support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) --- .../bindings/display/msm/dp-controller.yaml | 103 +++++++++++++++++= +++- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 26 +++++- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 10 +- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 3 +- .../bindings/display/msm/qcom,sm7150-mdss.yaml | 10 +- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 10 +- .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 10 +- 7 files changed, 150 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index afe01332d66c3c2e6e5848ce3d864079ce71f3cd..aeb4e4f36044a0ff1e78ad47b86= 7e232b21df509 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -66,25 +66,37 @@ properties: - description: link register block - description: p0 register block - description: p1 register block + - description: p2 register block + - description: p3 register block + - description: mst2link register block + - description: mst3link register block =20 interrupts: maxItems: 1 =20 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock + - description: Display Port stream 2 Pixel clock + - description: Display Port stream 3 Pixel clock =20 clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel + - const: stream_2_pixel + - const: stream_3_pixel =20 phys: maxItems: 1 @@ -166,7 +178,6 @@ required: allOf: # AUX BUS does not exist on DP controllers # Audio output also is present only on DP output - # p1 regions is present on DP, but not on eDP - if: properties: compatible: @@ -195,11 +206,95 @@ allOf: else: properties: aux-bus: false - reg: - minItems: 5 required: - "#sound-dai-cells" =20 + - if: + properties: + compatible: + contains: + enum: + # these platforms support SST only + - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp + - qcom,sc8180x-edp + - qcom,sc8280xp-edp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 5 + maxItems: 5 + clocks-names: + minItems: 5 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 2 streams MST on some interfaces, + # others are SST only + - qcom,sc8280xp-dp + - qcom,x1e80100-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 5 + maxItems: 6 + clocks-names: + minItems: 5 + maxItems: 6 + + - if: + properties: + compatible: + contains: + # 2 streams MST + enum: + - qcom,sc8180x-dp + - qcom,sdm845-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 6 + maxItems: 6 + clocks-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 4 stream MST on first DP, + # 2 streams MST on the second one. + - qcom,sa8775p-dp + then: + properties: + reg: + minItems: 9 + maxItems: 9 + clocks: + minItems: 6 + maxItems: 8 + clocks-names: + minItems: 6 + maxItems: 8 + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index 1053b3bc49086185d17c7c18d56fb4caf98c2eda..e2730a2f25cfb0496f47ad9f3f9= cbf69b1d4649f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -375,7 +375,11 @@ examples: <0xaf54200 0x0c0>, <0xaf55000 0x770>, <0xaf56000 0x09c>, - <0xaf57000 0x09c>; + <0xaf57000 0x09c>, + <0xaf58000 0x09c>, + <0xaf59000 0x09c>, + <0xaf5a000 0x23c>, + <0xaf5b000 0x23c>; =20 interrupt-parent =3D <&mdss0>; interrupts =3D <12>; @@ -384,16 +388,28 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>, + <&dispcc_dptx0_pixel2_clk>, + <&dispcc_dptx0_pixel3_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; =20 assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents =3D <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy= 1>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, + <&dispcc_mdss_dptx0_pixel2_clk_src>, + <&dispcc_mdss_dptx0_pixel3_clk_src>; + assigned-clock-parents =3D <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; =20 phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.= yaml index 870144b53cec9d3e0892276e14b49b745d021879..44c1bb9e41094197b2a6855c0d9= 92fda8c1240a4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -207,16 +207,20 @@ examples: <&dispcc_disp_cc_mdss_dptx0_aux_clk>, <&dispcc_disp_cc_mdss_dptx0_link_clk>, <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents =3D <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK= _CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DI= V_CLK>, <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DI= V_CLK>; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 2947f27e0585216ca0e1eab6a79afcb21323b201..b643d3adf66947095490b51625a= 03635c64c37c2 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -281,7 +281,8 @@ examples: reg =3D <0xaea0000 0x200>, <0xaea0200 0x200>, <0xaea0400 0xc00>, - <0xaea1000 0x400>; + <0xaea1000 0x400>, + <0xaea1400 0x400>; =20 interrupt-parent =3D <&mdss>; interrupts =3D <14>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index c5d209019124da3127285f61bf5a27d346a3d8a1..9b0621d88d508fb441f004261c4= 2c2473bea2bcb 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -394,16 +394,20 @@ examples: <&dispcc_mdss_dp_aux_clk>, <&dispcc_mdss_dp_link_clk>, <&dispcc_mdss_dp_link_intf_clk>, - <&dispcc_mdss_dp_pixel_clk>; + <&dispcc_mdss_dp_pixel_clk>, + <&dispcc_mdss_dp_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc_mdss_dp_link_clk_src>, - <&dispcc_mdss_dp_pixel_clk_src>; + <&dispcc_mdss_dp_pixel_clk_src>, + <&dispcc_mdss_dp_pixel1_clk_src>; assigned-clock-parents =3D <&dp_phy 0>, + <&dp_phy 1>, <&dp_phy 1>; =20 operating-points-v2 =3D <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index 72c70edc1fb01c61f8aad24fdb58bfb4f62a6e34..4151f475f3bc36a584493722db2= 07a3dd5f96eed 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -401,16 +401,20 @@ examples: <&disp_cc_mdss_dptx0_aux_clk>, <&disp_cc_mdss_dptx0_link_clk>, <&disp_cc_mdss_dptx0_link_intf_clk>, - <&disp_cc_mdss_dptx0_pixel0_clk>; + <&disp_cc_mdss_dptx0_pixel0_clk>, + <&disp_cc_mdss_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&disp_cc_mdss_dptx0_link_clk_src>, - <&disp_cc_mdss_dptx0_pixel0_clk_src>; + <&disp_cc_mdss_dptx0_pixel0_clk_src>, + <&disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_= LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VC= O_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VC= O_DIV_CLK>; =20 operating-points-v2 =3D <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.= yaml index e35230a864379c195600ff67820d6a39b6f73ef4..8d698a2e055a88b6485606d9708= e488e6bc82341 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -183,15 +183,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_L= INK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp0_opp_table>; --=20 2.47.2 From nobody Fri Oct 3 07:40:23 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FB9B2FF177 for ; Wed, 3 Sep 2025 11:58:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900722; cv=none; b=lKANhYNCLuxWHliIc56yROfGAbd4drXMQzFgw/dmMJ152BVs59fnemh8PO7H+C976kpIKTZSLn5pyiSNQO0z1+8PukWihf8mnwmjHK3ML4LYVQbenW5u6SljjQSYUvIfgWD2irNIGHumKehqSEdy6tShUI5aa1zQEowQVwCxs7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900722; c=relaxed/simple; bh=yuqF992JkLqD1kIJyjnt6Zn+nJH3RP1HSBd3vUxQH58=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HIwZb0R0F/cYS3LsSl9/emMW7e+ZVk47KsIWUUFlGhxk9Pb+Cc4dEwdvVhSncYqYX/7jzHol6HoubWdiqhO/tMxpHKvbqdbQ1M2qjx0TxW04tEI4Aa0w/7Iqv/O1ZWFgD3z0vybNnyze9JXFv8IzG/po6vYJ2x6sMZuWhxeKV0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=bzIUovPG; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="bzIUovPG" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BEve3014079 for ; Wed, 3 Sep 2025 11:58:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xQ0VgVzHDcE4uOAStGZ5b6EnRBy9KiNlbxxY6hsWIic=; b=bzIUovPG3BMXIJE3 naUIFc+2DyPMw2h+LczbgGu1jclHsoN8VCUQ+yFZNrezB3UtBKPEMf04Hv9R5mIp O6hYIF4y547t/h1UcoLdQDldYBLANhwlyo1Xp3edIhG39G7ryBbi/YbNX1Dg9fGu Gigro37yurymbGug5g5wlU6/aiMSVr80teukh+T2EQO23Iz4dlDNrXfxwoecRO0k D+Ob/lLffUstSgWCW2FBgrRZ6CMO0f1DKLu/sj9umM745FVI1hbslap0o3oQTWaU WRuqOvkDMnyKrIvFRSVtTKt0r7UdfwP6iZFcvoneIPCiv/kg4g1O0ZbggEMWgUK0 EQ91AA== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48w8wy7dyn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:40 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-71ffd145fa9so45173936d6.2 for ; Wed, 03 Sep 2025 04:58:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900719; x=1757505519; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xQ0VgVzHDcE4uOAStGZ5b6EnRBy9KiNlbxxY6hsWIic=; b=O18p0AGit3V6Gfyp4RDOnl1sFLJICl0eyIjcahNVCyvLtRRiAWXrywVYs/VCIDpWP0 KFn626CSJ+nhd0Ty7u+XD1SugGmPG72yFuCXt8mUho2nfA1QdQTyxsyKiBrvOCHxryQt exM/G7lsQsGrJ8gY4u4jXlHqN3Lakhonhi8xHjMXF65hovCaw4OvOizJxOBZR4JEImo2 cKRg6Ck9KBmFPqCLyT8htR3PvmP9ggQx62Z1irTS4g09Rh2N3GNdaD4f+sHAfkTVbhCb 5Yo/7IQeMuM9riqzAjnzW3YMG0zwHIWtHQ3UBylabFFKmZlrWoHZ894phC/2fYfHVDbQ pvYQ== X-Forwarded-Encrypted: i=1; AJvYcCVENI7aE08gqHTbEJKUHjEk+tPM2p0MxxfnVO3IByCu6/SozzvK73UoeW+tRQEzX/9VbIy9O+kq+lJVGqM=@vger.kernel.org X-Gm-Message-State: AOJu0YxHniUNxyLP4ltQBkCfpHjE6m6is9nx/wzZlAQwcSww5hxpK5xL T/mA8JnhJPEWy+3v8aIlatJAB09CoFQv3VVAr2wL2OBh+NrmMbXHN77F4tRIrPYAYuLJj4l5pSI N2U9HR7dws+qVNtWbqAarytZmxlYU80GDB/Z/61I4rVsJtUXH21r/kdgxiQY5d4lmmoc= X-Gm-Gg: ASbGncvdu8UxBuY9dqIzuasI2y84NJDS0kBl1bvR8djNENMYVA4gf/iKIYA6bAhlpXd JojORB5cbU09FPUUQvE0tKowc5HBP1TXFXjMeHiwluoov9nWw7VlyENqUKqGcBW1WkLzjXGtbUG 3qcVziT3lMpfOVwARTXLegzfxluG0LP9OisKHFmLEgI2vHqIwQrLQga6EnFXmLeWISRrCfhVIc0 Ip4Uy9Wv139hfqZ+zZxv1gsW4dE1bXIb7NKrnHv30T5OrFA1fvKF8dLi56K5lhW7mJbu0SXU6Ev hvIrLNEaT9ImUtHasISTCnPUQ+yqf6Nzgd3E7bdMdskWFzLH8pG38gPg0OD/kpQH8l4I9vL19Ll ARFbImoFOaEta+uYhm9hGLzzlUqUiC9XZkn9D2eVSmnA4x5GBJWWM X-Received: by 2002:a05:6214:1247:b0:70d:adb1:bf55 with SMTP id 6a1803df08f44-70fac8c859fmr134683396d6.49.1756900716948; Wed, 03 Sep 2025 04:58:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE/mtRqJfmERu7M9/61r/Pib5S1ya90D2+A5xz4iBPgz+esnd9B+FBxUWnhDBpOXm8CXSuJVg== X-Received: by 2002:a05:6214:1247:b0:70d:adb1:bf55 with SMTP id 6a1803df08f44-70fac8c859fmr134683066d6.49.1756900716415; Wed, 03 Sep 2025 04:58:36 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:35 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:19 +0300 Subject: [PATCH v8 8/9] arm64: dts: qcom: sm6350: correct DP compatibility strings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-8-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1329; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=yuqF992JkLqD1kIJyjnt6Zn+nJH3RP1HSBd3vUxQH58=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Z6lwJuo/b5AI8h777G/1hkQvXZ9IsEFm9k bhyfe5y3dWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtWQAKCRCLPIo+Aiko 1dYVCACUXNIiv7h7eyL5vYKr7mFPQgMkaSn7VDwtt0sBRf+f2in+SUE/FrMpVthcL/nSvFLbb8+ 7mkuNjq/wOhUXy+vGEMhzcyB0nU/L6BIFhJrNIikkKPqPLmAKzRnUkNKGDmSyvI2Wb5iWzzMi9k MYlRoNWHEoTCUhNV0pYhl/4smxY7U9xGhKarlcDcKgu4+Z3ufQPhzNp724HMk8YwkYuDDl2T3te k4KfUm98eINpKaB0FxMJiyMT1dfIzqQvZAYmYIq+lXIrP7RV0lZcUgPamnFUTXYff7Jm18uakkf ZEahvzkhOsHoHL97hCurVxOLYtYgAcdaGuUN4bgEeXOJhKB5 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b82d70 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=llJQ5I4GozCAaw4gE5wA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: 97BCMrYIBLvZ5s4eFAZPzLBndYW3_YZs X-Proofpoint-ORIG-GUID: 97BCMrYIBLvZ5s4eFAZPzLBndYW3_YZs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfX6EkEirwlI8cE qlTC9y+mmJu1ERjhHVrdCCoIXTkvQcziV3kup2M5Y0UiDeX95uayVS+t42qF/LxEdLvhZIDerRq 0bK92AFO1dIq715ZB5uwFSNJ0P5DQx3gRxPuOu/yUK9PIBLgr2FystZSlOBdJQ8NMhQ1hrQkUqQ /9jPz3xsovPvcJ/fnnjcsHRM8+9poKMIPZWIZ63fPP1vv2gp1hbN7Af6B/9MSfersgpUxqMlioM WtrMsh8D4rtRU0MOAzugzJSCQd+S9m3tKzFfTYe6qoACoGyS9MvC6GOhlppwVmqFFODiDTVMoSE kzEsZ8FToRiQZo582/EaEdy2PSrhCtZ2QcUuItY6fzqI/UBzFlSNZu9YCUk/p9qK4xct2m8raep j6sXJ9FU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 SM6350 doesn't have MST support, as such in DT schema it has been switched to use SC7180 as a fallback compatible. Make DT file implement this change. DisplayPort on SC7180 has been supported long ago (and long before we added support for DP on SM8350). The driver will continue to work with the old DTS (having qcom,sm8350-dp fallback compatible) as even after adding MST support the driver will have to support old SM8350 DTS which didn't have MST clocks. Fixes: 62f87a3cac4e ("arm64: dts: qcom: sm6350: Add DisplayPort controller") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 2493b9611dcb675f4c33794ecc0ee9e8823e24d4..8459b27cacc72a4827a2e289e66= 9163ad6250059 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2249,7 +2249,7 @@ opp-560000000 { }; =20 mdss_dp: displayport-controller@ae90000 { - compatible =3D "qcom,sm6350-dp", "qcom,sm8350-dp"; + compatible =3D "qcom,sm6350-dp", "qcom,sc7180-dp"; reg =3D <0x0 0xae90000 0x0 0x200>, <0x0 0xae90200 0x0 0x200>, <0x0 0xae90400 0x0 0x600>, --=20 2.47.2 From nobody Fri Oct 3 07:40:23 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3704D2FFDDE for ; Wed, 3 Sep 2025 11:58:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900725; cv=none; b=KQyMxJ8UAkbN7GbwWaI6MmRdadYsrxMM7aZHeApaHx7hhk/NeEXjrCm67RPijeV4AVz4vw7m4s8zcOuM+z8JyTAU+U3rJrK+H393UD/DkJTkUUcVbs0wKdCBhnLES3JjywNOVIK2s8IX7XiCZt3axpsYc2scbCcgmxmxrrBt09A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756900725; c=relaxed/simple; bh=CIM8TItYbokpNxQzxnu4aIUEp892yVk+eJ5zXzouulQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MbM5SmlG+Mc4EzEWjVFE0sQVda3VcqtBDHuMwDSKtAsZB6TpzxIpOHvYTRwvxFot6IgnV53/GRgPZ+1zeowEtn2PHmICCcC/u1c0XnZ+RjsFD78Trx46VdTHf/eLapr3bkB69r9xibxkextq+DJKSMSMgD/I6l4OpWGXemt4S7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Gbj7e54o; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Gbj7e54o" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 583BFJiD010422 for ; Wed, 3 Sep 2025 11:58:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gJ2EVCf2QkS2ikAW+cVgqkB2Bj5sGAucvM7aSGgJQTM=; b=Gbj7e54oz06djAQD TBYcIzdmjVV5fOrh8ihMH2p27HQEsOsga0rNDnRoIrCt7/kWkbUeq0xPvNBwePPD PBekFTDEyeQFJZP8w1cfaGJyaXR5PCl1N8DhfxwrPyRqcgHKJNlB8klzhekgyyZk AQ7ZMMYDzj70HbaV3iKxEdB23kVWvEMaTAzLt09TenI66SofGUgaWZ55Ab0a9gc1 u3tUY1+Na84H1kSbeAKOEVyisZ9MuTtLogh809Y20ciPEmBCS7Q7EZNfDk012XCn au3FyR+gQ5it0f4o2SvAeSknhx5Zrbn60vKd6XRKdNA22YEOHw9AOSqiIZwuO5EP bF6IRg== Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48ura8ufr8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 03 Sep 2025 11:58:41 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-70de52d2870so47757616d6.0 for ; Wed, 03 Sep 2025 04:58:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756900720; x=1757505520; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gJ2EVCf2QkS2ikAW+cVgqkB2Bj5sGAucvM7aSGgJQTM=; b=slfvpUty9DTB1aXhgipR+jhGHOfcDFSOe6dlzFUvayuRffmu0Y2WAtuAiNtATMnCFE IWfbwYlkmqV+nWOok089F2eINyR2QY7NoaX+RNqsG41lpPXcihSAUYR0IxagQo/dOJ2E mZZp20A5V9wtv6XsWIcUdynpmuqg7HLD+eRI0NDp9apjEbownsXsFG2uYjX6RjTaMHFj 9B8B/JaBVOwH7kTyeKonYqii8ZIM2jan3iaduPcSUxY4z2F8bJbm9e6S82MouJPuNAlI hpau7SSwCGwg8EST9Su49AU8znMWu8ImoM5A+84iMJdEZY3ZK/Z/bx4sYc86NUQovDKV vbCw== X-Forwarded-Encrypted: i=1; AJvYcCXJcbKPSpHpuTwKSWxoUhoQI4DXy4vXFAQ26hxutoMCa7nn1pbCJEuiYY2KPXb6lU7V1+ttod4cFD2vKew=@vger.kernel.org X-Gm-Message-State: AOJu0YwBPTFkL1qzAx7jUlozdCekrJv/nEjcDJ58e0s4it42D5efcMQN 6WQRkV7OnxKpOJ9xdNcd2wv1AewgjdAlvpU7VXCoXSN5yey8ZZ+rfggXiaWfBHk7TPBrjJ+OvFo 2Ngn3bP/sp/1fVxNivTa6wk4Nzbs5FUupeFvaCcwqv8zVYAYJ8NsbM2gpjBdj1Rx2UD0= X-Gm-Gg: ASbGncvYmSbgraI8KhHAyrIbseVmnS3mxjPRI9rCEQNil01r45VvqEbj5B6Hbj9XLSS BZxyNMpYADRNMSPhW1kOSRwKDoL9PUB84xR4LI1+lIjYN1bjgqg2jpU/4QUIOuq4/ecF1kuhq3w I6p2tu31CnFPdTCQ4TsHWz631PBf6rixWcdXtI7MN4p97sFjOMq7HmIkHqGxC5d2WlNYBGVdKr1 j5xtPzzG36fgkugjvFe8HBQ6OEVHu2TKN0vPiF7I65cg8oceSm7hgmXTXjEnn8JuLv1DvW/hV7k Mx7mBByRb1jXt/TNrZjy3mE4lAcsZBPnQpYrm5vtliZj3znvNstc09/Lya98S/4hvwNCLuDhlcv QBGBNcZj+a/+O/hKA2t4SMx32c8CuaeSpkJxWxroKptYKLIfXEjjD X-Received: by 2002:a05:6214:5281:b0:71a:ccf0:7201 with SMTP id 6a1803df08f44-71accf07438mr106431536d6.38.1756900719763; Wed, 03 Sep 2025 04:58:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEo9FJLndt1SvkCxwFLolu0o7BJylhejD8hoUcwbpqBmrR2YY2gSQTMBJUVj20xF+IibNLHCQ== X-Received: by 2002:a05:6214:5281:b0:71a:ccf0:7201 with SMTP id 6a1803df08f44-71accf07438mr106430926d6.38.1756900718957; Wed, 03 Sep 2025 04:58:38 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f50d30b0sm9891421fa.67.2025.09.03.04.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 04:58:36 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 03 Sep 2025 14:58:20 +0300 Subject: [PATCH v8 9/9] arm64: dts: qcom: Add MST pixel streams for displayport Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-dp_mst_bindings-v8-9-7526f0311eaa@oss.qualcomm.com> References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> In-Reply-To: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=29696; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=BHy8R6zn9dlPybx4a7I3nYQEeZm+V78yb5qchN6Fzlw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBouC1Zx3Tb68JybHq39fSVlQiIz0hDAdyriECHr OoQPQocIMOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaLgtWQAKCRCLPIo+Aiko 1S79CACbIZuAe75U8NO4kX13IKyT/JGuIqju9bJNnV/K8tp17XlRFt4V2JPcTNM9J67qLMX6Suu g1zYzGfW0lbxlSox5HwRs5screyYySt/cXUVLmyOFFfJ9yQ7ZckbVIXqO3/GdGPhwKJXlaqnMKv ZWbklZnjHRVEeBd2B2ZRgzaROJKi2oux1B7lyvFP1GOd2rF7qddr6dFKO0R8oDCRdRCw3lWaOgL xT1o2bVdKWbnsj4YoZO0oVJl7PC3ltV9i698bRQhgq00tmUq1i4vhRq07MOJ8qqG8RChf8PGO6c E9OFgEtn4fMuQ9KTAJBqFyLncsrN0sZ7WsCZK3hZuLbPKkpU X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: tgCGvDagI6OyNZRBm9MZcGw10gryu9uU X-Proofpoint-GUID: tgCGvDagI6OyNZRBm9MZcGw10gryu9uU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyMCBTYWx0ZWRfXy5WYNjEwU1Zd 6MHC+SsdE6K0Ad4wTmvE3SK+fzLp6+a7HxONJh1ahILQYTsbgW1lOgpl6IkyID3/HPxOoQWLKlM u+EmgcF34SE80Y0+jeH0fiNwmfZ4sr0D+eNblcBXNyHs+EZUViLtWLC2huZ20smWIWbAt0/PGb+ 7RVPhcsJVuhMrYzGvcUQSUFIWqzslLlvKG1+hcLUgVXRinZwu2iXJCcVB8zTSlMKuc1OuA/xqbs cBdOy1x6mVzHK0gvIZsrpL6Vp4LwEFkxEwGwJUYmOUiX83P1sfSmK2gtKjB248ARKHu0UoLD1Xi uYYY/nGylS0GSWXqbenDyMvqVHDAVbf/UEwtmycSkz2nTu5k3Y+hhWE0HHoRON/vw06649zOewh IfJqiSRK X-Authority-Analysis: v=2.4 cv=VNndn8PX c=1 sm=1 tr=0 ts=68b82d71 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=1HNNWeqUXF9djYgkd-QA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300020 From: Jessica Zhang Update Qualcomm DT files in order to declare extra stream pixel clocks and extra register resources used on these platforms to support DisplayPort MST. The driver will continue to work with the old DTS files as even after adding MST support the driver will have to support old DTS files which didn't have MST clocks. Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/lemans.dtsi | 46 +++++++++++++++++----- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 23 +++++++---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-------= ---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++-- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++----- 13 files changed, 185 insertions(+), 74 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 64f5378c6a4770cee2c7d76cde1098d7df17a24a..a1e033089860504844727fd9cd8= 87f0808de1607 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4694,7 +4694,11 @@ mdss0_dp0: displayport-controller@af54000 { <0x0 0x0af54200 0x0 0x0c0>, <0x0 0x0af55000 0x0 0x770>, <0x0 0x0af56000 0x0 0x09c>, - <0x0 0x0af57000 0x0 0x09c>; + <0x0 0x0af57000 0x0 0x09c>, + <0x0 0x0af58000 0x0 0x09c>, + <0x0 0x0af59000 0x0 0x09c>, + <0x0 0x0af5a000 0x0 0x23c>, + <0x0 0x0af5b000 0x0 0x23c>; =20 interrupt-parent =3D <&mdss0>; interrupts =3D <12>; @@ -4703,15 +4707,28 @@ mdss0_dp0: displayport-controller@af54000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; =20 @@ -4773,7 +4790,11 @@ mdss0_dp1: displayport-controller@af5c000 { <0x0 0x0af5c200 0x0 0x0c0>, <0x0 0x0af5d000 0x0 0x770>, <0x0 0x0af5e000 0x0 0x09c>, - <0x0 0x0af5f000 0x0 0x09c>; + <0x0 0x0af5f000 0x0 0x09c>, + <0x0 0x0af60000 0x0 0x09c>, + <0x0 0x0af61000 0x0 0x09c>, + <0x0 0x0af62000 0x0 0x23c>, + <0x0 0x0af63000 0x0 0x23c>; =20 interrupt-parent =3D <&mdss0>; interrupts =3D <13>; @@ -4782,15 +4803,20 @@ mdss0_dp1: displayport-controller@af5c000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp1_phy 0>, + <&mdss0_dp1_phy 1>, + <&mdss0_dp1_phy 1>; phys =3D <&mdss0_dp1_phy>; phy-names =3D "dp"; =20 diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/q= com/sar2130p.dtsi index 38f7869616ff01ece3799ced15c39375d629e364..62bd535d7f14bed10fae329b20a= c97cb63f3761b 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0dd6a5c91d109c78333f6b90104fa51fcf3bd64c..375e890f02c7d1cb06845293f17= deb6ec45f9c5a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5047,7 +5047,8 @@ mdss_edp: edp@aea0000 { reg =3D <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, <0 0x0aea0400 0 0xc00>, - <0 0x0aea1000 0 0x400>; + <0 0x0aea1000 0 0x400>, + <0 0x0aea1400 0 0x400>; =20 interrupt-parent =3D <&mdss>; interrupts =3D <14>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 70c87c79e1325f4ab4c81f34e99c0b52be4b3810..e6a7248040095077d6f98d632f4= e8a1868432445 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3241,16 +3241,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; @@ -3319,16 +3323,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; @@ -3389,7 +3397,8 @@ mdss_edp: displayport-controller@ae9a000 { reg =3D <0 0xae9a000 0 0x200>, <0 0xae9a200 0 0x200>, <0 0xae9a400 0 0x600>, - <0 0xae9aa00 0 0x400>; + <0 0xae9aa00 0 0x400>, + <0 0xae9b000 0 0x400>; interrupt-parent =3D <&mdss>; interrupts =3D <14>; clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 421693208af0d5baeaa14ba2bbf29cbbc677e732..ad04868763d00221ed9939c7613= 2977b83762cd7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 { <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; @@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 { <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 { <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss0>; interrupts =3D <14>; phys =3D <&mdss0_dp2_phy>; @@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp2_phy 1>; operating-points-v2 =3D <&mdss0_dp2_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5675,10 +5688,12 @@ mdss1_dp0: displayport-controller@22090000 { <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <12>; phys =3D <&mdss1_dp0_phy>; @@ -5686,8 +5701,11 @@ mdss1_dp0: displayport-controller@22090000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; operating-points-v2 =3D <&mdss1_dp0_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5750,10 +5768,12 @@ mdss1_dp1: displayport-controller@22098000 { <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <13>; phys =3D <&mdss1_dp1_phy>; @@ -5761,8 +5781,11 @@ mdss1_dp1: displayport-controller@22098000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; operating-points-v2 =3D <&mdss1_dp1_opp_table>; =20 #sound-dai-cells =3D <0>; @@ -5825,10 +5848,12 @@ mdss1_dp2: displayport-controller@2209a000 { <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent =3D <&mdss1>; interrupts =3D <14>; phys =3D <&mdss1_dp2_phy>; @@ -5836,8 +5861,11 @@ mdss1_dp2: displayport-controller@2209a000 { power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents =3D <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp2_phy 1>; operating-points-v2 =3D <&mdss1_dp2_opp_table>; =20 #sound-dai-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 828b55cb6baf10458feae8f53c04663ef958601e..816987906ca51b8c7eb834d8b85= 0839941eadb6b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names =3D "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names =3D "dp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 4b347ee3244100a4db515515b73575383c5a0cb7..e0beb5373cdc8ff92f165d7a971= f8f7dce31bca8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 244339cfbed5c32708c282de18f5655535e2ff45..272b41214ab31edd2c0c695cf29= 4f0959167585a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 9a4207ead6156333b8b6030fb0fbc1d215948041..136f40a3b9767133d6a4fe52753= 530bccced3391 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 2baef6869ed7c17efb239e86013c15ef6ef5f48f..1b482dc5f574acd5ea938c9953a= 35164e51c6cb3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 38d139d1dd4a994287c03d064ca01d59a11ac771..2d085680afd1bed2bd2477c21ae= 4b798efe6a066 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3755,16 +3755,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index d6794901f06b50e8629afd081cb7d229ea342f84..887b2ea055e8d969ba9ad07e738= dcb6feccc0e61 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5657,16 +5657,20 @@ mdss_dp0: displayport-controller@af54000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&dp_opp_table>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index f293b13ecc0ce426661187ac793f147d12434fcb..7c5f6c101ac10ce6fbc5eead177= 246ce77c668bf 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5338,16 +5338,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp0_opp_table>; @@ -5421,16 +5425,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp1_opp_table>; @@ -5504,16 +5512,20 @@ mdss_dp2: displayport-controller@ae9a000 { <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; =20 operating-points-v2 =3D <&mdss_dp2_opp_table>; --=20 2.47.2