From nobody Fri Oct 3 08:49:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA8E3043A9 for ; Wed, 3 Sep 2025 12:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; cv=none; b=QhPfY5bWyEY2fKFa6apXgJVYS4hpjEp7bifo7v+mp2/Vv2Bifh/4TF2SnL62uu09qNwS8OCSpEtCDDvBKUM7AlYN1hk+LrpBXgNDROVCFZf/KTqBad45XFSMjL7rLmIJMk2z5fvnKQvP5YN8zqB9X3GovXhe/dE3Sc8n2+v84Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; c=relaxed/simple; bh=kGI9vrMnZ8OMv3ozZlNZdXDHDwL02sNWL/GPUnr19TA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hUZYsT9O16H9hPsIbOAmCDG06IHWuNaR+wAH2nEPzE0I7puxhBZmIW3cuzeSiqvpFdS/kQsM3gZYf+tqA8qIilZ5qW2hUYvKYDEtZTPZf4AutXK2gNSmydQIwFqSf7QK7FnehMFLk2Iee0hZrXikm+DDYEW/Ues/DlTUp2mvE2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ukmIk4/k; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ukmIk4/k" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 395B91A08EC; Wed, 3 Sep 2025 12:47:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 11D7D606C3; Wed, 3 Sep 2025 12:47:47 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 712381C22CD91; Wed, 3 Sep 2025 14:47:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903666; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=hIuBi/1rFuUwp8AeM1BPzxwcWp+eQE6OQjarXfBjdmM=; b=ukmIk4/koyR30YSdaO1nYxVxYMNGFrNvT2+sFAsgltlhws0uBsYVv4rqN3KUNQkcJyprVy fWyVQlGSEZmUa3vWfPxYl5l5FtxHZLbht//vyiIJzyWpA7HjQ3jXBrWni4qKZHtjWQIPDW 9CUJCeV71MflVeFxC2Pj+0UnVdTpb4JSMs9i1G4RcUtzGw3THToW9seuHgVPEtms4WVugE pLOZvCmtFkVW1bHXdPgt+gbrjekVPdiHttxjnQGKg354NdfmI7cReiGZDbG8vwzpERe7tQ ccRYbL03l7eTHTNFVlCAS6jYJ/XUeFuZpUca7adx208p68553P8by27oBmB2ew== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:13 +0200 Subject: [PATCH 06/19] reset: eyeq: add eyeQ7H compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-6-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add support for the reset controllers found in the eyeQ7H OLB. For this, three new types of reset domain are added to the driver. The EQR_EYEQ7H_ACRP reset domain is similar to the EQR_EYEQ5_ACRP domain with a different registers layout. The EQR_EYEQ7H_CFG reset domain is similar to the EQR_EYEQ5_PCIE domain, again with a different registers layout. The EQR_EYEQ7H_ACC reset domain is similar to the EQR_EYEQ6H_SARCR domain, with a different registers layout and no busy waiting. Signed-off-by: Sari Khoury Signed-off-by: Beno=C3=AEt Monin --- drivers/reset/reset-eyeq.c | 248 +++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 246 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c index 02d50041048b42921e3e511148cd29f215b5fc5e..322c05d7e6b818e5b0d395787c6= 9ad91616820e0 100644 --- a/drivers/reset/reset-eyeq.c +++ b/drivers/reset/reset-eyeq.c @@ -1,10 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms. + * Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platform= s. * * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ= 6L * have a single OLB instance for a single reset controller. EyeQ6H has se= ven - * OLB instances; three host reset controllers. + * OLB instances; three host reset controllers. EyeQ7H has fourteen OLB in= stances; + * eleven host reset controllers. * * Each reset controller has one or more domain. Domains are of a given ty= pe * (see enum eqr_domain_type), with a valid offset mask (up to 32 resets p= er @@ -61,6 +62,40 @@ * 9. PMA0 10. PMA1 11. MPC0 12. MPC1 * 13. MPC2 14. MPC3 15. PERIPH * + * Known resets in EyeQ7H south (type EQR_EYEQ7H_CFG) + * 0. PCI_PHY 1. PCI_CTL 2. S_NOC 3. GBE_PHY + * 4. GBE_CTL 5. XSPI 6. UFS 7. VDIO + * + * Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG) + * 0. ISP 2. VEU 3. LBIST + * + * Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG) + * 0. GPU 2. CAU 3. LBIST 4. GPU_LBIST + * + * Known resets in EyeQ7H periph (type EQR_EYEQ5_SARCR) + * 0. gpio 1.EXT TIMER 3.UART 4. SPI + * 5. I2C0 6. I2C1 7.I2C2 8. I2S + * + * Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG) + * 0. APB 2. DMI 3. DFI 4. PHY_SMS + * 5. CTL_SMS + * + * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACRP) + * 1. VMP0 2. XVMP1 3. VMP2 4. VMP3 + * 5. MPC0 6. MPC1 7. PMA0 8. PMA1 + * + * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACC) + * 1. NCORE0 2. NCORE1 3. NCORE0_M 4. NCORE1_M + * 5. NCORE_NOC 6. VMP_NOC 7. MPC_NOC 8. PMA_NOC + * + * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACRP) + * 1. XNN0 2. XNN1 3.XNN2 + * + * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACC) + * 1. XNN0 2. XNN1 3. XNN2 4. XNN3 + * 5. NCORE 6. I2_0 7. I2_1 8. SMS_0 + * 9. SMS_1 + * * Abbreviations: * - PMA: Programmable Macro Array * - MPC: Multi-threaded Processing Clusters @@ -102,6 +137,9 @@ enum eqr_domain_type { EQR_EYEQ5_ACRP, EQR_EYEQ5_PCIE, EQR_EYEQ6H_SARCR, + EQR_EYEQ7H_ACRP, + EQR_EYEQ7H_CFG, + EQR_EYEQ7H_ACC }; =20 /* @@ -126,6 +164,21 @@ enum eqr_domain_type { #define EQR_EYEQ6H_SARCR_RST_STATUS (0x008) #define EQR_EYEQ6H_SARCR_CLK_REQUEST (0x00C) =20 +/* + * Domain type EQR_EYEQ7H_ACRP register masks. + * Registers are: base + 4 * offset. + */ +#define EQR_EYEQ7H_ACRP_PD_REQ BIT(0) +#define EQR_EYEQ7H_ACRP_MBIST_CFG GENMASK(3, 1) +#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN BIT(13) +#define EQR_EYEQ7H_ACRP_ST_ACTIVE BIT(14) + +/* + * Domain type EQR_EYEQ7H_ACC register masks. + */ +#define EQR_EYEQ7H_ACC_CLK_EN (0x000) +#define EQR_EYEQ7H_ACC_RST_EN (0x004) + struct eqr_busy_wait_timings { unsigned long sleep_us; unsigned long timeout_us; @@ -134,7 +187,10 @@ struct eqr_busy_wait_timings { static const struct eqr_busy_wait_timings eqr_timings[] =3D { [EQR_EYEQ5_SARCR] =3D {1, 10}, [EQR_EYEQ5_ACRP] =3D {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeo= ut. */ + [EQR_EYEQ7H_ACRP] =3D {1, 40 * USEC_PER_MSEC}, /* EQR_EYEQ5_PCIE does no busy waiting. */ + /* EQR_EYEQ7H_CFG does no busy waiting. */ + /* EQR_EYEQ7H_ACC does no busy waiting. */ [EQR_EYEQ6H_SARCR] =3D {1, 400}, }; =20 @@ -209,6 +265,17 @@ static int eqr_busy_wait_locked(struct eqr_private *pr= iv, struct device *dev, sleep_us, timeout_us); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + if (assert) + mask =3D EQR_EYEQ7H_ACRP_ST_POWER_DOWN; + else + mask =3D EQR_EYEQ7H_ACRP_ST_ACTIVE; + + ret =3D readl_poll_timeout(reg, val, !!(val & mask), + sleep_us, timeout_us); + break; + case EQR_EYEQ5_PCIE: ret =3D 0; /* No busy waiting. */ break; @@ -229,6 +296,14 @@ static int eqr_busy_wait_locked(struct eqr_private *pr= iv, struct device *dev, &rst_status, &clk_status); break; =20 + case EQR_EYEQ7H_CFG: + ret =3D 0; /* No busy waiting. */ + break; + + case EQR_EYEQ7H_ACC: + ret =3D 0; /* No busy waiting. */ + break; + default: WARN_ON(1); ret =3D -EINVAL; @@ -261,6 +336,11 @@ static void eqr_assert_locked(struct eqr_private *priv= , u32 domain, u32 offset) writel(readl(reg) | EQR_EYEQ5_ACRP_PD_REQ, reg); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) | EQR_EYEQ7H_ACRP_PD_RE= Q, reg); + break; + case EQR_EYEQ5_PCIE: writel(readl(base) & ~BIT(offset), base); break; @@ -273,6 +353,18 @@ static void eqr_assert_locked(struct eqr_private *priv= , u32 domain, u32 offset) writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST); break; =20 + case EQR_EYEQ7H_CFG: + writel(readl(base) & ~BIT(2 * offset) & ~BIT(2 * offset + 1), base); + break; + + case EQR_EYEQ7H_ACC: + /* RST_REQUEST and CLK_REQUEST must be kept in sync. */ + val =3D readl(base + EQR_EYEQ7H_ACC_RST_EN); + val &=3D ~BIT(offset); + writel(val, base + EQR_EYEQ7H_ACC_RST_EN); + writel(val, base + EQR_EYEQ7H_ACC_CLK_EN); + break; + default: WARN_ON(1); break; @@ -315,6 +407,11 @@ static void eqr_deassert_locked(struct eqr_private *pr= iv, u32 domain, writel(readl(reg) & ~EQR_EYEQ5_ACRP_PD_REQ, reg); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) & ~EQR_EYEQ7H_ACRP_PD_R= EQ, reg); + break; + case EQR_EYEQ5_PCIE: writel(readl(base) | BIT(offset), base); break; @@ -327,6 +424,18 @@ static void eqr_deassert_locked(struct eqr_private *pr= iv, u32 domain, writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST); break; =20 + case EQR_EYEQ7H_CFG: + writel(readl(base) | BIT(2 * offset) | BIT(2 * offset + 1), base); + break; + + case EQR_EYEQ7H_ACC: + /* RST_REQUEST and CLK_REQUEST must be kept in sync. */ + val =3D readl(base + EQR_EYEQ7H_ACC_RST_EN); + val |=3D BIT(offset); + writel(val, base + EQR_EYEQ7H_ACC_RST_EN); + writel(val, base + EQR_EYEQ7H_ACC_CLK_EN); + break; + default: WARN_ON(1); break; @@ -368,11 +477,19 @@ static int eqr_status(struct reset_controller_dev *rc= dev, unsigned long id) case EQR_EYEQ5_ACRP: reg =3D base + 4 * offset; return !(readl(reg) & EQR_EYEQ5_ACRP_ST_ACTIVE); + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE); case EQR_EYEQ5_PCIE: return !(readl(base) & BIT(offset)); case EQR_EYEQ6H_SARCR: reg =3D base + EQR_EYEQ6H_SARCR_RST_STATUS; return !(readl(reg) & BIT(offset)); + case EQR_EYEQ7H_CFG: + return !(readl(base) & BIT(2 * offset)); + case EQR_EYEQ7H_ACC: + reg =3D base + EQR_EYEQ7H_ACC_RST_EN; + return !(readl(reg) & BIT(offset)); default: return -EINVAL; } @@ -537,6 +654,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_dat= a =3D { .domains =3D eqr_eyeq6h_acc_domains, }; =20 +static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x1F, + .offset =3D 0x070, + }, + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x7, + .offset =3D 0x074, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_south_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_south_domains), + .domains =3D eqr_eyeq7h_south_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x7, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_east_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_east_domains), + .domains =3D eqr_eyeq7h_east_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0xf, + .offset =3D 0x068, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_west_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_west_domains), + .domains =3D eqr_eyeq7h_west_domains, +}; + +/* Periph OLBs each have an instance. */ +static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] =3D { + { + .type =3D EQR_EYEQ6H_SARCR, + .valid_mask =3D 0xFF, + .offset =3D 0x030, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_per_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_per_domains), + .domains =3D eqr_eyeq7h_per_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0x1F, + .offset =3D 0x008, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_ddr_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_ddr_domains), + .domains =3D eqr_eyeq7h_ddr_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0xFF, + .offset =3D 0x000, + }, + { + .type =3D EQR_EYEQ7H_ACC, + .valid_mask =3D 0xFF, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_acc_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_acc_domains), + .domains =3D eqr_eyeq7h_acc_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0x7, + .offset =3D 0x000, + }, + { + .type =3D EQR_EYEQ7H_ACC, + .valid_mask =3D 0x1FF, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_xnn_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_xnn_domains), + .domains =3D eqr_eyeq7h_xnn_domains, +}; + /* * Table describes OLB system-controller compatibles. * It does not get used to match against devicetree node. @@ -547,6 +771,17 @@ static const struct of_device_id eqr_match_table[] =3D= { { .compatible =3D "mobileye,eyeq6h-west-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-east-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-acc-olb", .data =3D &eqr_eyeq6h_acc_da= ta }, + { .compatible =3D "mobileye,eyeq7h-south-olb", .data =3D &eqr_eyeq7h_sout= h_data }, + { .compatible =3D "mobileye,eyeq7h-east-olb", .data =3D &eqr_eyeq7h_east_= data }, + { .compatible =3D "mobileye,eyeq7h-west-olb", .data =3D &eqr_eyeq7h_west_= data }, + { .compatible =3D "mobileye,eyeq7h-periph-east-olb", .data =3D &eqr_eyeq7= h_per_data }, + { .compatible =3D "mobileye,eyeq7h-periph-west-olb", .data =3D &eqr_eyeq7= h_per_data }, + { .compatible =3D "mobileye,eyeq7h-ddr0-olb", .data =3D &eqr_eyeq7h_ddr_d= ata }, + { .compatible =3D "mobileye,eyeq7h-ddr1-olb", .data =3D &eqr_eyeq7h_ddr_d= ata }, + { .compatible =3D "mobileye,eyeq7h-acc0-olb", .data =3D &eqr_eyeq7h_acc_d= ata }, + { .compatible =3D "mobileye,eyeq7h-acc1-olb", .data =3D &eqr_eyeq7h_acc_d= ata }, + { .compatible =3D "mobileye,eyeq7h-xnn0-olb", .data =3D &eqr_eyeq7h_xnn_d= ata }, + { .compatible =3D "mobileye,eyeq7h-xnn1-olb", .data =3D &eqr_eyeq7h_xnn_d= ata }, {} }; MODULE_DEVICE_TABLE(of, eqr_match_table); @@ -556,6 +791,15 @@ static const struct auxiliary_device_id eqr_id_table[]= =3D { { .name =3D "clk_eyeq.reset_west" }, { .name =3D "clk_eyeq.reset_east" }, { .name =3D "clk_eyeq.reset_acc" }, + { .name =3D "clk_eyeq.reset_south" }, + { .name =3D "clk_eyeq.reset_periph_east" }, + { .name =3D "clk_eyeq.reset_periph_west" }, + { .name =3D "clk_eyeq.reset_ddr0" }, + { .name =3D "clk_eyeq.reset_ddr1" }, + { .name =3D "clk_eyeq.reset_acc0" }, + { .name =3D "clk_eyeq.reset_acc1" }, + { .name =3D "clk_eyeq.reset_xnn0" }, + { .name =3D "clk_eyeq.reset_xnn1" }, {} }; MODULE_DEVICE_TABLE(auxiliary, eqr_id_table); --=20 2.51.0